JPS648512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for determining phase coincidence between two signals that have a constant relationship in frequency but are independent in phase, and in particular, a circuit for determining phase coincidence between two signals that have a fixed relationship in frequency but are independent in phase, and in particular, a circuit for determining phase coincidence between two signals that have a constant relationship in frequency but are independent in phase. The present invention relates to a phase coincidence determination circuit used in a frame synchronizer (frame combining device) that converts signals into signals.

In a frame synchronizer, the counter is operated using a clock pulse synchronized with the burst signal included in the video signal, but the start phase of this counter is based on the horizontal synchronization signal (the signal that determines this start phase is the start phase specified pulse). ). However, due to noise, synchronization separation circuits, etc., the horizontal synchronization signal after being separated from the video signal often has a jitter amount of one clock period or more. In this case, the counter start phase changes each time. Then, since the frame synchronizer determines the write address based on the output of this counter, the video read from the frame synchronizer flickers. In order to avoid this, the counter output is decoded to create a pulse (inhibition pulse) whose center is at the counter start phase and whose time width is several times the clock period, and this pulse inhibits the start phase regulation pulse. (Of course, even while the start phase regulation pulse is prohibited, the counter returns to the start phase at a predetermined period by its own self-clear pulse).

In such a conventional system, the wider the inhibit pulse, the more stable the start phase of the counter becomes with respect to jitter in the horizontal synchronizing signal. However, if the inhibit pulse is set to n times the clock period, when the power is turned on, etc., the clock period will be n times the phase difference unit.
Since counter start phases are created,
It also applies to the video read from the frame synchronizer.
The disadvantage is that there are several start phases, and the address of the readout image cannot be uniquely determined. Furthermore, if jitter exceeding the prohibited pulse width occurs even momentarily in the horizontal synchronizing signal, the counter start phase will change, resulting in a disadvantage that the image read out from the frame synchronizer will flicker.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase coincidence determination circuit for a frame synchronizer that stabilizes the video read from the frame synchronizer and also allows the address of the read video to be uniquely determined.

The phase coincidence determination circuit for a frame synchronizer according to the present invention includes a circuit that detects a phase mismatch between an inhibit pulse synchronized with the start phase of a counter that counts clock pulses and a pulse synchronized with a horizontal synchronization signal, and an output of this mismatch detection circuit. a first retriggering monostable multivibrator triggered by the output of said first retriggering monostable multivibrator; and a second retriggering monostable multivibrator triggered by the output of said first retriggering monostable multivibrator; and a circuit that supplies a start phase defining pulse to the counter when the outputs of the first and second retrigger monostable multivibrators match.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. However, in this figure, the phase matching determination circuit 50
In addition, there is a terminal 1 that receives the video signal 101, a clock pulse generator 2 that generates a clock signal 102 synchronized with the burst signal included in the video signal 101, a counter (ring counter) 4 that counts this clock signal 102, and the video signal. An H-pulse generator 3 is shown which generates a pulse (referred to as an H-pulse) 103 synchronized with the horizontal synchronizing signal contained in 101. The prohibition pulse generator 5 is connected to the counter 4
An inhibit pulse 105 synchronized with the start phase of (the start phase is included within the pulse time width) is generated from the counter output 104. The gate circuit 8 generates a trigger pulse 1 having the same waveform as the H pulse 103 only when the prohibition pulse 105 and the H pulse 103 are out of phase.
Outputs 06. The retrigger monostable multivibrator 10 generates a trigger pulse 10 in a stable state.
6, the period T1 of the H pulse 103 is 2~
A rectangular wave signal 107 having three times the time width T2 is output. Next retrigger monostable multivibrator 1
2 generates a rectangular wave signal 108 whose time width T3 is more than twice T2 when it receives a trigger pulse (output of the retrigger monostable multivibrator 10) 107 in a stable state. The gate circuit 14 sends a start phase regulation pulse 109 to the counter 4 for the time period during which the signals 106, 107 and 108 match.

FIG. 2 is a timing chart of various signals in the embodiment shown in FIG. 1 when the counter start phase does not need to be changed. Even if the H pulse 103 does not match the phase of the inhibit pulse 105 for a short period (less than T3) due to jitter or the like (times P and Q), the start phase regulation pulse 109 does not appear at the output of the gate circuit 14. Therefore, the starting phase of the counter 4 remains unchanged (the retriggered monostable multivibrator 12 is triggered at time Q and becomes metastable).

FIG. 3 is a timing chart of various signals when the counter start phase is changed in the embodiment of FIG. 1. Inhibition pulse 105 and H pulse 10
If the phase with 3 deviates over a long period (T3 or more), the start phase regulation is applied to the output of the gate circuit 14 after the time T3 set in the retrigger monostable multivibrator 12 has elapsed from the initial deviation. Pulse 109 is output for the first time and counter 4
(time point B in FIG. 3).
At time C in FIG. 3, the start phase of the counter 4 is changed to time B, and as a result, the phases of the next H pulse 103 and inhibition pulse 105 match.

The output width T2 at one trigger in the retrigger monostable multivibrator 10 is set to H pulse 103.
The reason why the pulse interval T1 is set to 2 to 3 times the pulse interval T1 is that, as shown at time A in FIG. This is to prevent the start phase regulation pulse 109 from not being output forever if the retrigger monostable multivibrator 10 becomes stable (the output 107 is at a low level).

FIG. 4 is a block diagram of a frame synchronizer constructed using the embodiment of FIG. 1. The heterogeneous synchronous television video signal 20 enters the analog signal input terminal 19, and after the signal component of half or more of the clock frequency (14 MHz) in the signal is removed by the input side low-pass filter 21, it is input to the A/D converter 23. sampled at the clock frequency,
It is converted into PCM data 24. Meanwhile, a write clock pulse 31 synchronized with the color burst in the television video signal 20 is generated by a write clock pulse generator 30.
A write address 33 synchronized with a synchronization signal of 0 is generated by a write address generator 32. Information for one frame period of the PCM data 24 is then written into the digital memory 25 at a location determined by the write address 33.

On the other hand, a read clock pulse 31' synchronized with the color burst of the read timing reference signal (black burst signal) 38 is applied to the read clock generator 3.
A read address 33', which is generated with 0' and synchronized with the synchronization signal of the read timing reference signal 38, is generated by the read address generator 32'. Then, the PCM data in the memory 25 is read out using the read address 33' and the read clock pulse 31', and is converted into a PAM signal by the D/A converter 27, and the frequency component of half or more of the clock frequency is removed by the output side low-pass filter 21'. The television signal 29 is synchronized with the read timing reference signal 38, that is, the television signal 29 is synchronously converted.

The write address generator 32 and the read address generator 32' are divided into an H address section and a V address section, and the address 0 is determined by the synchronization signal of the television video signal and the read timing reference signal 38, respectively. The V address 0 can be stably determined by the V synchronization phase and the H synchronization phase, but for the H address 0, it must be considered that the amount of jitter in the horizontal synchronization signal is longer than the clock cycle (70nsec or more) in the worst case. Therefore, it must be assumed that it often changes. As a result, in the frame synchronizer output 29, the vertically straight line at the input 20 is twisted only where the H address 0 is shifted. The phase matching judgment circuits 50, 5 can overcome these drawbacks.
By inserting 0', the H address 0 becomes stable and the problem can be solved. Note that the clock pulse generator 2 in FIG. 1 corresponds to the write (read) clock generators 30, 30' in this figure, and the counter 4 is included in the write (read) address generators 32, 32'. .

As described in detail above, according to the present invention, it is possible to obtain a phase coincidence determination circuit for a frame synchronizer that stabilizes the video read out from the frame synchronizer and also allows the address of the read video to be uniquely determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a timing diagram of the signals of each part in the embodiment of FIG. 1 when the counter start phase does not need to be changed, and FIG. 3 is a timing diagram of the signals of each part of the embodiment of FIG. 1 when the counter start phase is changed. FIG. 4 is a block diagram of a frame synchronizer constructed using the embodiment shown in FIG. 1...Video signal input terminal, 50, 50'...Phase coincidence determination circuit.

Claims (1)

[Claims] 1. A circuit that detects a phase mismatch between an inhibit pulse synchronized with the start phase of a counter that counts clock pulses and a pulse synchronized with a horizontal synchronization signal, and a first retrigger monostable triggered by the output of this mismatch detection circuit. a multivibrator, a second retriggering monostable multivibrator triggered by the output of the first retriggering monostable multivibrator, and an output of the mismatch detection circuit and the first and second retriggering monostable multivibrator; A phase match determination circuit for a frame synchronizer, comprising: a circuit that supplies a start phase regulation pulse to the counter when the outputs of the vibrators match.