JPS648838B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument, and more particularly, to an electronic musical instrument that has a plurality of pitch specifying means or a plurality of musical tone generation sequences, and generates sound by adding reverberant sound with different characteristics to each keyboard or each musical tone signal generation sequence. It is related to. BACKGROUND ART Conventionally, some electronic musical instruments are equipped with multiple keyboards such as an upper keyboard, a lower keyboard, a pedal keyboard, and a solo keyboard, so that each keyboard can produce performance sounds with different tones. In addition, there is a system in which a plurality of musical tone signal generation sequences are provided so that a plurality of musical tones having different musical tone elements such as pitch and timbre can be simultaneously generated in response to one pressed key. By the way, when adding reverberation to the musical tones corresponding to the pressed keys of each keyboard or the musical tones of each musical sound signal generation series in such an electronic musical instrument, the musical tone elements such as the timbre of the musical sounds are different for each key or each musical sound signal generation series. Therefore, richer performance effects can be achieved by varying the reverberation time, reverberation depth, and other characteristics of the reverberant sound depending on each musical tone element. Therefore, in such an electronic musical instrument, a configuration is desired in which the reverberation characteristics can be freely varied for each keyboard or for each tone signal generation series. The present invention has been made in view of the above points, and its object is to provide an electronic musical instrument that can add reverberant sound with a desired reverberation characteristic to each pitch specifying means or each musical tone signal generation sequence. There is a particular thing. To this end, the present invention provides a plurality of reverberant sound adding devices for adding reverberant sound corresponding to each of the plurality of sound specifying means or each of the plurality of musical sound signal generation sequences, and adjusts the reverberation characteristics of each reverberant sound adding device. This can be set arbitrarily. By the way, when configuring a reverberation sound adding device using an electronic circuit, BBD (Bucket
Brigade Device) and CCD (Charge Coupled Device)
There are devices that use analog delay elements such as Device). However, in devices using such analog delay elements, the longer the reverberation time, the more
That is, as the number of series-connected analog delay elements increases, the output signal level decreases and the S/N ratio decreases more significantly, making it impossible to obtain natural reverberation. Another drawback is that once the reverberation characteristics, including the reverberation time, are set, they cannot be easily changed thereafter. Therefore, in this invention, in order to prevent the S/N from decreasing even if the reverberation time is increased and to easily change the reverberation time, a plurality of pitch specifying means and each pitch specifying means are provided. A musical sound generating means that generates a plurality of series of digital musical sound signals each corresponding to a specified pitch, and a plurality of digital reverberation devices that add and output reverberant sounds having different characteristics for each series to the digital musical sound signals of each series. and a sound addition channel, the digital reverberation sound addition channel comprising: reverberation sound instruction means for selectively instructing reverberation characteristics of reverberation sound from among a plurality of reverberation characteristics; and each of the reverberation characteristics that can be specified by the reverberation sound instruction means. A control program memory 30 stores a plurality of control programs for forming reverberant sound corresponding to the reverberation characteristics, and outputs a control program corresponding to the reverberation characteristics instructed by the reverberation characteristics instruction means.
0, a sound effect forming means including a calculation means 40 and a data memory 190 having a plurality of addresses, and controlling the delay time-related parameters and calculation coefficient-related parameters corresponding to the reverberation characteristic instructed by the reverberation characteristic instruction means. The parameter generation means 20 generates data according to the output of the program memory 300, and writes and reads data to and from the data memory 190 based on the output of the control program memory 300 and parameters related to the delay time.
The reverberation sound forming means includes a control means 303 for outputting a memory control signal for address designation as well as an arithmetic control signal for the arithmetic means 40 based on the output of the control program memory 300; By performing a predetermined operation on the signal read out from the data memory 190 in accordance with the control signal, the calculation coefficient, and the digital musical tone signal, the reverberation characteristics instruction means specifies the reverberation characteristic instruction for the digital musical tone signal. It is designed to output with reverberation characteristics added. Hereinafter, this invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument according to the present invention, in which an upper keyboard 1, a lower keyboard 2,
Pedal keyboard 3, key press detection circuit 4, sound generation assignment circuit 5, musical tone signal generation circuit 6, tone setting circuit 7, musical tone data accumulator 8, first series reverberant sound adding device 9, second series reverberant sound adding device 10 , adder 1
1, DA converters 12 and 14, and sound systems 13 and 15. The upper keyboard 1, lower keyboard 2, and pedal keyboard 3 each have a plurality of keys and a plurality of key switches that operate when each key is pressed, and the operation of each key switch is determined by a key press detection circuit 4. detected. The pressed key detection circuit 4 detects the operation of each key switch on the upper keyboard 1, lower keyboard 2, and pedal keyboard 3, and generates and outputs a key code KC representing the pressed key. In this case, the key code KC is composed of a keyboard code KBC representing the type of keyboard, an octave code OC representing the range of the key, and a note code NC representing the note name, and the key code KC is supplied to the pronunciation assignment circuit 5. . The sound generation assignment circuit 5 assigns a key code supplied from the key press detection circuit 4 to one of the plurality of time-division sound generation channels in the musical tone signal generation circuit 6.
Assign the pronunciation of the musical tone corresponding to the pressed key indicated by KC,
The key code KC of the pressed key is time-divisionally output at the channel timing corresponding to this assigned channel. It is assumed here that 12 time-division sounding channels are provided. in this case,
The sound generation assignment circuit 5 generates a key-on signal that controls the sound generation of musical tones assigned to each sound generation channel in synchronization with the time-division output timing of the key code KC.
It outputs KON and supplies it to the musical tone signal generation circuit 6. As mentioned above, the musical tone signal generation circuit 6 includes, for example,
It has 12 time-division pronunciation channels, and when the key code KC of the pressed key is supplied from the pronunciation allocation circuit 5 in synchronization with the timing of each channel, the tone set by this key code KC and the tone setting circuit 7 is generated. Based on the information TSD, musical sound data GD (digital musical sound signal) with a pitch corresponding to the code KC (octave code OC and note code NC) and a timbre corresponding to the timbre information TSD is formed for each sounding channel. Output in parts. This musical tone signal generation circuit 6 generates musical tone data GD using musical tone signal forming methods such as a waveform memory read method, a harmonic synthesis method, a frequency modulation method, and an amplitude modulation method. In addition, musical tone data for each pronunciation channel
GD is given an amplitude envelope from attack to decay by the key-on signal KON of its own channel. In this case, the timbre setting circuit 7 is capable of setting timbres for each of the upper keyboard 1, lower keyboard 2, and pedal keyboard 3, and outputs timbre information TSD corresponding to each keyboard. and,
In each sound generation channel in the musical tone signal generation circuit 6, the keyboard code KBC of the own channel is
The musical tone data GD of the tone corresponding to the tone color information TSD regarding the keyboard indicated by is formed. As a result, musical tone data GD is formed with different tones for each keyboard. In this manner, the musical tone signal generation circuit 6 forms and outputs musical tone data GD regarding the pressed keys assigned to each sound generation channel in a time-division manner, and supplies the generated musical tone data to the musical tone data accumulator 8. The musical sound data accumulator 8 synthesizes the musical sound data GD formed by each sound generation channel of the musical sound signal generation circuit 6 every time the timing of the 12 sound generation channels goes around (every cycle of 1 channel timing x 12). The synthesized musical tone data ΣGD of the musical tones corresponding to the pressed keys of keys 1 to 3 is output. Also,
Musical sound data GD related to pressed keys of the upper keyboard 1 are synthesized every time the sound generation channel timing completes one cycle and output as upper keyboard musical sound data ΣGD _U. Furthermore, the musical tone data GD regarding the pressed keys of the lower keyboard 2 and the pedal keyboard 3 are synthesized every time the sound generation channel timing goes around and output as the lower pedal keyboard musical tone data ΣGD _LP . In this case, a maximum of 12 musical tone data formed in each sound channel
The allocation of GD to each keyboard is performed by the keyboard code KBC supplied from the sound generation assignment circuit 5. The synthesized musical tone data ΣGD related to all the pressed keys of the keyboards 1 to 3 synthesized in the musical tone data accumulator 8 is converted into an analog musical tone signal in the DA converter 12 and then sent to the sound system 15.
It is pronounced as a musical tone. On the other hand, the upper keyboard musical tone data ΣGD _U is supplied to the first series reverberant sound adding device 9, and reverberant sound having a desired reverberation characteristic is added thereto. Further, the lower pedal keyboard musical sound data ΣGD _LP is supplied to the second series reverberation sound adding device 10 to add reverberation sound having a desired reverberation characteristic. The first series reverberant sound adding device 9 and the second series reverberant sound adding device 10 use digital memory as a delay element, as will be described later, to add reverberant sound having desired reverberation characteristics to each musical tone data ΣGD _U and ΣGD _LP . The reverberation characteristics are configured so that they can be freely set using delay time information that defines the delay time of musical tone data and coefficients that control the amplitude level. Therefore, by making the delay time information and amplitude control coefficients different in the reverberation sound adding devices 9 and 10 of each series, different reverberation sounds can be produced between the upper keyboard 1, the lower keyboard 2, and the pedal keyboard 3. can be added. The musical sound data ΣGD _U ′ and ΣGD _LP ′ to which the reverberation sound has been added in the reverberation sound adding devices 9 and 10 of each series are synthesized in the adder 11 and then added to the DA
is supplied to converter 14. The DA converter 14 converts the signal into an analog musical tone signal, and the sound system 15 outputs it as a musical tone with reverberation. Here, a reverberation sound with a short reverberation time and shallow reverberation depth is added as a reverberation sound for the musical tone of the pressed key of the upper keyboard 1, and a sound with a short reverberation time and a shallow reverberation depth is added, and
If you add a reverberation sound with a long reverberation time and deep reverberation depth to the musical sound of the pressed key, the melody performance sound on the upper keyboard 1 will be mixed with the accompaniment sound on the other keyboards 2 and 3. On the other hand, it is possible to achieve a performance effect in which the sound is pushed to the front and is heard floating. FIG. 2 is a circuit diagram showing a specific configuration of the musical tone data accumulator 8, in which the synthesized musical tone data ΣGD is generated by an adder 8A, a register (delay flip-flop) 8B, a latch 8C and an AND gate 8.
It is formed by a circuit consisting of D. That is, the tone data GD formed by each sound generation channel is supplied to the addition input A of the adder 8A. The adder 8A is connected to the first to twelfth sounding channels.
Store the musical sound data GD of the pronunciation channel in register 8.
The output value of the register 8B is supplied to the addition input B via the AND gate 8D only when the timing signal ₁ is "1". As shown in the time chart of FIG. 3, timing signal ₁ is a timing signal that becomes "1" at the channel timing corresponding to the first sound generation channel among the 12 channel timings defined by clock pulse φ _A. T ₁ (This is the inverted signal (Fig. 3 e) of Fig. 3 d, and this timing signal ₁ is supplied to the AND gate 8D as a gate control signal. Therefore, the timing signal 1 is supplied to the addition input B of the adder 8A. The output value of the register 8B is continuously inputted at channel timings other than the channel timing corresponding to the first sounding channel.Therefore, the adder 8A inputs the output value of the register 8B continuously for the musical tone data GD of the first sounding channel. The register 8B takes in the musical tone data GD of the first sound generation channel at the timing of the clock pulse φ _A shown in FIG. 3a, and outputs it as is and supplies it to _{the register 8B} . The register 8B outputs the input data at the generation timing.In other words, the register 8B outputs the input data with a time delay corresponding to one channel timing.Then, when the channel timing corresponding to the second sound generation channel arrives, the timing signal ₁ becomes "1".
, the AND gate 8D becomes open, so the musical tone data GD of the first sound channel held in the register 8B is stored in the AND gate 8.
It is input to the addition input B of the adder 8A via D. At this time, since the musical tone data GD of the second sound generation channel is input to the addition input A of the adder 8A, the adder 8A outputs the sum of the musical tone data of the first and second sound generation channels. This added value is held in register 8B. By repeating this operation until the channel timing corresponding to the 12th sound channel, the 12th
At the end of the channel timing, the total addition value ΣGD of the musical tone data GD of the 12 sounding channels is obtained. This total addition value ΣGD is determined by the latch 8C at the rising edge of the timing signal _T1 .
While the channel timing goes through this latch 8C (until the next signal _T1 rises)
The signal is held and output from the output of the latch 8C as synthesized musical tone data ΣGD. Figure 3 f shows synthesized musical tone data ΣGD(t) and ΣGD(t
+1). On the other hand, musical tone data ΣGD _U and ΣGD _LP for each keyboard are also formed using a similar circuit. However, since the adder 8E, which adds new musical tone data and already accumulated musical tone data, is shared by the accumulation circuit series for each keyboard, the input stage of the addition input B of the adder 8E is is provided with a selector 8J, and registers 8G and 8 that hold respective total values of musical tone data for each keyboard.
Selectors 8F and 8K are provided at the input stage of L, respectively. Note that the circuit consisting of adder 8E, selectors 8J, 8F, register 8G, latch 8H, and AND gate 8I constitutes an accumulation circuit series that forms upper keyboard tone data ΣGD _U , and adder 8E, selector 8J , 8K, a register 8L, a latch 8M, and an AND gate 8N constitute an accumulation circuit array that forms the lower pedal keyboard musical tone data ΣGD _LP . First, the musical tone data GD of the first pronunciation channel
is added, this musical tone data GD is sent to adder 8
is fed to the addition input A of E. At this time, AND gates 8I and 8N of each accumulation circuit series are both closed by timing signal ₁ , so
The two selection inputs A and B of the selector 8J are all "0", and the input value of the addition input B of the adder 8E is "0". Therefore, the adder 8E outputs the musical tone data GD of the first sound generation channel supplied to the addition input A as it is, and supplies it in common to the selection input A of the selectors 8F and 8K of each accumulation circuit series. The selectors 8F and 8K select and extract the musical tone data GD output from the adder 8E for each keyboard. In other words, selector 8F is the keyboard code
When the upper keyboard signal UC indicating the upper keyboard 1 obtained by decoding KBC by the decoder 8R is "1", the musical tone data input from the adder 8E to the selection input A
GD selects this musical tone data GD as relating to the pressed key of the upper keyboard 1 and supplies it to the register 8G. In addition, when either the lower keyboard signal LC indicating the lower keyboard 2 obtained by decoding the keyboard code KBC by the decoder 8R or the pedal keyboard signal PC indicating the pedal keyboard 3 is "1", the selector 8K outputs "1" from the OR gate 8P. Signal is select control input
Since the musical tone data GD input from the adder 8E to the selection input A is related to the pressed key of the lower keyboard 2 or the pedal keyboard 3, this musical tone data GD is selected and supplied to the register 8L. Therefore, the musical tone data GD of each sound generation channel output from the adder 8E is divided into two series, the upper keyboard 1 series and the lower keyboard 2 and pedal keyboard 3 series, according to the keyboard code KBC, and is stored in the register. It is distributed and supplied to 8G and 8L respectively. here,
If the musical tone data GD of the first sound generation channel is related to the pressed key of the pedal keyboard 3,
This musical tone data GD is supplied to a register 8L via a selector 8K and held in this register 8L. Next, when the timing signal ₁ becomes "1" at the channel timing corresponding to the second sound generation channel, the AND gates 8I and 8N of each accumulation circuit series are opened. Therefore, the values held in the registers 8G and 8L of each accumulation circuit series are fed back to the selection inputs B of the selectors 8F and 8K of the own series via the open AND gates 8I and 8N, and These are supplied to selection inputs A and B of selector 8J, respectively. When the upper keyboard signal UC is "1", the selector 8J selectively outputs the musical tone data GD related to the upper keyboard 1 that is supplied to the selection input A via the AND gate 8I, and also outputs the lower keyboard signal LC or the pedal keyboard signal PC. When either of these is "1", a "1" signal is input from the OR gate 8Q to the selection control input SB, so the musical tones related to the lower keyboard 2 and pedal keyboard 3 are supplied to the selection input B via the AND gate 8N. Data GD is selectively output, and this selected output data is supplied to addition input B of adder 8E. Therefore, the musical tone data of the second sounding channel
When GD is related to the pressed key of the upper keyboard 1, the musical tone data GD held in the register 8G is supplied to the addition input B of the adder 8E, and the musical tone data GD held in the register 8G is supplied to the addition input A. Musical tone data GD of the pronunciation channel is supplied. However, in this example, as mentioned above, the first sound channel is related to the pedal keyboard 3, so the register 8G is
Since the musical tone data GD is not yet stored and held, the adder 8E outputs the musical tone data GD of the second sound generation channel regarding the upper keyboard 1 as is. And this musical tone data GD is the selector 8F.
It is held in register 8G via. Next, the musical tone data GD of the third pronunciation channel
is also related to upper keyboard 1, register 8
Since the tone data GD of the second tone generation channel related to the upper keyboard 1 is already stored in G, the adder 8E outputs the sum value of the tone data GD of both the second tone generation channel and the third tone generation channel. do. The added value of these two tone data GD is supplied to the register 8G via the selector 8F and held in this register 8G. in this case,
The data in the register 8 of the accumulation circuit series regarding the lower keyboard 2 and pedal keyboard 3 is held by the output of the register 8L being fed back to its own input via the AND gate 8N and the selection input B of the selector 8K. It is being done. By performing this operation in the same way for each musical tone data GD of the 12 sounding channels, when the channel timing completes the cycle, registers 8G and 8L contain the total value ΣGD _U of the musical tone tenter GD related to the upper keyboard 1. Musical sound data GD regarding the lower keyboard 2 and pedal keyboard 3
The total values ΣGD _LP are respectively stored and held. The musical tone data ΣGD _U and ΣGD _LP for each keyboard thus obtained are supplied to the reverberation sound adding devices 9 and 10 of FIG. 1 via latches 8H and 8M, respectively. FIG. 4 is a block diagram showing an embodiment according to the second invention in which reverberant sound having a desired reverberant characteristic is added to each series of musical tone signal generators. In the figure, an upper keyboard 1, a lower keyboard 2, a pedal keyboard 3, a key press detection circuit 4, a sound generation assignment circuit 5, a first series reverberant sound adding device 9, a second series reverberant sound adding device 10, and a DA converter 1
2 and 14, sound system 13 and 15
is the same as the embodiment shown in FIG. 1, but a first series musical tone signal generation circuit 6A and a first series musical tone data accumulator are provided between the sound generation assignment circuit 5 and the two series of reverberant sound adding devices 9 and 10. 16A, a second series musical tone signal generation circuit 6B, and a second series musical tone data accumulator 16B. First series and second series musical tone signal generation circuit 6
A and 6B are musical tone signal generation circuits 6 in FIG.
Similarly, it has, for example, 12 time-division sounding channels, and the sounding assignment circuit 5 forms musical tone data GD regarding pressed keys assigned to each sounding channel, and synchronizes this musical tone data GD with the timing of each channel. Although it is a time-division output, the first
The musical tone data GD _A formed by each sound generation channel of the series musical tone signal generation circuit 6A and the musical tone data GD _B formed by each sound generation channel of the second series musical tone signal generation circuit 6B have musical tone elements such as pitch and timbre. configured differently. Therefore, when the tone generation circuits 6A and 6B of these two systems are assigned to generate musical tones related to the pressed keys, 1
Two musical tone data GD _A and GD _B with different musical tone elements are simultaneously formed for each pressed key. The musical tone data GD _A and GD _B formed in each sound generation channel of each series in this way are supplied to musical tone data accumulators 16A and 16B, respectively, and are synthesized every time the channel timing goes around, and the first series is synthesized. The musical tone data ΣGD _A and the second series synthesized musical tone data ΣGD _B are output. The first series synthesized musical tone data ΣGD _A and the second series synthesized musical tone data ΣGD _B are supplied to the first series reverberant sound adding device 9 and the second series reverberant sound adding device 10, respectively, and these devices 9 and 10 perform reverberation. Reverberation sounds with different characteristics are added. First and second series reverberation sound adding devices 9, 1
Similarly to the embodiment shown in FIG. 1, reverberation characteristics can be freely set using delay time information that defines the delay time of musical tone data and coefficients that control the amplitude level. The musical sound data ΣGD _A ′, ΣGB to which reverberant sounds with different reverberation characteristics are added for each series in this way are
After being converted into analog musical tone signals in the DA converters 12 and 14, respectively, the sound systems 13 and 14 produce musical tones with reverberation. Here, the first musical tone data GD _A has a low pitch such as 16 feet or 32 feet, and the second series musical tone data GD A has a low pitch such as 16 feet or 32 feet.
If the series musical sound data GD _B has a high pitch such as 4 feet or 2 feet, a reverberation sound with a long reverberation time and deep reverberation depth is added to the first series musical sound data GD _A. However, if a reverberation sound with characteristics of short reverberation time and shallow reverberation depth is added to the second series musical sound data GD,
The musical tones of the second series are pushed to the front, making it possible to obtain a performance effect similar to that performed in a concert hall or the like. Note that the musical tone data accumulators 16A and 16B in this embodiment are constructed in the same manner as the circuit for forming the synthesized musical tone data ΣGD shown in FIG. FIG. 5 shows a reverberation sound adding device 9 used in this invention.
FIG. 6 is a functional block diagram showing the configuration of this embodiment functionally. FIGS. 7 and 8 are block diagrams showing reverberation sound with a desired delay time using digital memory. FIG. 2 is a block diagram showing the basic configuration of a delay circuit for generating a signal. For convenience of explanation, we will first explain the basic configuration and operation of the delay circuit shown in FIGS. 7 and 8,
Next, the process of forming reverberant sound will be explained with reference to the functional block diagram of FIG. 6, and then the specific structure and operation of the embodiment shown in FIG. 5 will be explained. Basic configuration of a delay circuit using a digital memory When musical tone data GD(t) of an input musical tone signal sampled sequentially at a predetermined sampling period _T0 is sequentially stored in a digital memory as time elapses, the time ( In order to read the musical tone data GD(t-i) stored at time t-i) at time t after i time has elapsed, the address information ADR(t) when the sampling time is t must be changed during i time. Add or subtract the address interval ΔADR, as shown in the following equation (1) or (2), to obtain address information ADR (t-i) at time (t-i).
This address information ADR(t-i) can be given to the address input of the digital memory. ADR (t-i) = ADR (t) + ΔADR ... (1) ADR (t-i) = ADR (t) - ΔADR ... (2) This allows the memory to be stored at time (t-i). Musical tone data GD(t-i) can be read out with a delay of i time expressed as i=ΔADR×T ₀ (3).
That is, if the address interval ΔADR corresponding to the desired delay time i is given as delay time information, musical tone data GD(t-
i) can be read with a delay of i time. In this case, to obtain the address information ADR(t-i) at time (t-i) using equation (1) above, the musical tone data GD(t) is transferred from a high-order address to a low-order address as time passes. This is applied when sequentially storing the Further, the second formula is applied when musical tone data GD(t) is stored sequentially from a low address to a high address. Therefore, the delay circuit in the embodiment is a digital memory DM that sequentially stores musical tone data GD(t).
, an address information generation circuit AG that forms the read address information ADR (ti) shown by the above equation (1) or (2), and the above address interval ΔADR.
A delay length data memory DDM is basically provided which generates delay time information DLD. FIG. 7 is a block diagram showing an example of a delay circuit based on this concept, which includes a digital memory DM, an address information generation circuit AG, a delay length data memory DDM, and a multiplier M. The digital memory DM stores musical tone data GD sampled at a predetermined period _T0 according to the sampling pulse _Ts , as shown in the time chart of FIG.
(t) is stored in each address from ``0'' to ``9'' in order from the high address ``9'' to the low address ``0.'' Ru. Musical sound data in this digital memory DM
Designation of the write address and read address of GD(t) is performed by address information generation circuit AG. In other words, the address information generation circuit
AG includes an address counter AC and an adder AD, and the write address information ADR(t), ADR(t+
1), ADR(t+2), . Output as DM/ADR. i.e. address counter AC
counts (down counts) the sampling pulse T _S with period T ₀ , and calculates the count value as musical tone data GD(t) at the current sampling time t.
output as write address information ADR(t),
This information ADR(t) is supplied to the adder AD. On the other hand, the delay length data memory DDM stores time information DLD (ΔADR=
i/T ₀ ) to the other addition input of the adder AD. Then, at the sampling time t, the adder AD first performs the calculation expressed by the above-mentioned equation (1), and uses the calculated value as the musical tone data GD of i time before.
(t-i) read address information ADR(t-i)
Then, the output information ADR (t) of the address counter AC is directly used as the write address information ADR of the musical tone data GD (t) at the current time t.
Output as (t). As a result, from the digital memory DM,
At time t, musical tone data GD(t-i) stored at time i hours ago (t-i) is read out, and musical tone data GD(t) at current time t is read out.
is stored at the address specified by address information ADR(t). The musical tone data GD(t-i) read out from the digital memory DM with a delay of i time in this way is
The signal is multiplied by a coefficient K for amplitude level control in a multiplier M and output after level control. Such operations are performed at each sampling time.
As a result, it is possible to generate reverberant sound delayed by i hours from the input musical tone. In this case, multiple pieces of delay time information that differ at one sampling time
If DLD is applied sequentially in a time-sharing manner, information regarding multiple reverberant sounds with different delay times can be extracted within the same sampling time. Therefore, the delay circuit shown in Figure 7 is used to form early reflected sounds with complex reverberation characteristics that randomly vary in amplitude level and delay time depending on the distance to the surrounding wall or other reflecting body. be done. FIG. 8 is a block diagram showing another example of the delay circuit, in which the address counter AC of the address information generation circuit AG is constructed with a preset type down counter. Then, by presetting delay time information DLD corresponding to a desired delay time i for address counter AC and performing a down-count operation from this preset value (DLD), address information ADR (t ), ADR(t+1),...
The repetition period of ADR (t+i) is delay time information
The musical tone data GD(t) at the current time t is set to match the delay time specified by DLD.
The tone data GD(t-i) stored i hours ago is read from the address at which it is to be stored. In other words, when the digital memory DM consists of 10 words as shown in Figure 8, the maximum value of the address interval is " ₁₀ ", so the musical tone data GD (t- 10), it is possible to read out the desired delay time i, for example, 6·T ₀
In this case, the output information of address counter AC
DM/ADR 5, 4, 3, 2, 1, 0, 5,...
... 0 is repeated, and the address range used in the digital memory DM is set to the desired delay time i.
(i=6・T ₀ ), and the address to which the musical tone data GD(t) sampled at the current time t is to be written is changed to the musical tone data GD(t−i ) to match the written address, and the musical tone data GD at the current time t.
Musical tone data GD(t-i) written i hours ago is read from the address where data (t) is to be written. For this reason, in the delay circuit of FIG. 8, the output information DM of the address counter AC is
A maximum value detection circuit MXD is provided which detects that ADR changes from "0" to "9" and presets the time information DLD output from the delay length data memory DDM into the address counter AC based on this detection signal. There is. On the other hand, the delay circuit shown in FIG. 8 does not directly write the musical tone data GD(t) sampled at the current time t into the digital memory DM, but returns the musical tone data GD(t-i) from i hours ago at a predetermined rate. Then, the feedback value K・GD(t−i) and the musical tone data GD sampled at the current time t
(t) is written.
For this purpose, a coefficient K
A multiplier M multiplies the multiplier M and returns it to the data input side of the digital memory DM, and the output data K・GD(t−i) of the multiplier M and the musical tone data GD at the current time t.
(t) and the added value “GD(t)+K・
An adder AD is provided which supplies "GD(t-i)" to the data input of the digital memory DM. Therefore, in the delay circuit configured in this way, when the desired delay time i is 6·T ₀ ,
When the output information DM/ADR of the counter AC changes from "0" to the maximum value ("9" in this example), the delay time information DLD expressed as DLD=6-1=5 is stored in the address counter AC. Preset. As a result, the address counter AC changes to 5, 4, 3, 2, 1, 0, 5, . . . (every sampling period T ₀ ) as the sampling time progresses.
Address information that changes from 0 to DM・
ADR will be output repeatedly. and,
At each sampling time, address information
Musical tone data GD(t-i) from i hours ago stored at the address specified by DM/ADR is first read out, and then musical tone data GD(t-i) from i hours ago is read from the same address as this read address. i)
and the musical sound data GD sampled at the current time t.
(t) and added at a predetermined ratio, the data “GD
(t)+K·GD(t−i)” is written. Therefore, in the delay circuit configured in this way, musical tone data GD at the current sampling time t
(t) write address and musical tone data i hours ago
Since the read address of GD(t-i) is the same and the musical sound data GD(t-i) from i hours ago is fed back, data related to reverberant sound whose amplitude level and delay time regularly change can be collected. It can be taken out. Therefore, the delay circuit shown in FIG. 8 is used to generate reverberant sound with regular reverberation characteristics. Furthermore, when the musical tone data is multiplied by the coefficient K,
The level of the final reverberant sound data will be higher than the original musical sound data, so
In reality, data regarding this reverberant sound is led to the reverberant sound output section through an attenuator. In this case, if the coefficient K is set to "-1<K<0", an attenuator is not required. Next, the process of forming reverberant sound will be explained using the functional block diagram shown in FIG. Process of Forming Reverberant Sound First, the process of forming reverberant sound in the embodiment shown in FIG. The process of forming reverberant sound in which the delay time changes regularly. Here, these early reflected sounds and reverberant sounds are formed by mutually independent delay circuit series. In Fig. 6, input musical tone data (ΣGD _U ,
Musical sound data GD(t) obtained by sampling ΣGD _LP , ΣGD _A , ΣGD _B ) at a predetermined period T ₀ is supplied to an early reflected sound forming section 1000 which is a first delay circuit series. The early reflected sound forming section 1000 utilizes the delay circuit shown in FIG. , i _o hours (n=1-10) 10 before
Types of musical sound data GD (t-i ₁ ), GD (t-i ₂ ),...
...multiplier M1 to multiply GD (t-i ₁₀ ) by an arbitrary amplitude level control coefficient K _o (n=1 to 10)
M10 and the multiplier outputs of these multipliers M1 to M10
K ₁・GD (t-i ₁ ), K ₂・GD (t-i ₂ ), ...K ₁₀・
Find the sum of GD (t-i ₁₀ ) ₁₀ 〓 ⁿ⁼¹ K _o・GD (t-i _o ),
The adder SUM1 outputs the sum ₁₀ 〓 ⁿ⁼¹ K _o ·GD (t-i _o ) as the instantaneous value ECH (t) of the early reflected sound at the current time t. Note that the adder SUM1 calculates the above sum ₁₀ 〓 ⁿ⁼¹ K _o・GD
It has a built-in register R0 that temporarily stores (t-i _o ) until the next sampling time (t+1). In the early reflected sound forming section 1000 having such a configuration, the musical tone data GD(t) sampled at the current time t is written to the address corresponding to the current time t among the 2048 word storage addresses of the memory D0. Next, the register R0 in the adder SUM1 stores the total sum ₁₀ 〓 ⁿ⁼¹ K _o · GD (t-1 - i _o ) at the previous sampling time (t-1), so this register R0 The contents of will be reset.
Next, 10 types of amplitude data GD (t-i ₁ ) before i _o time
〜GD (t−i ₁₀ ), musical tone data with delay time i ₁
In order to read GD (t-i ₁ ) from memory D0, the address of memory D0 corresponding to delay time i ₁ is specified,
Musical tone data GD (t-i ₁ ) sampled i ₁ hours ago is read from the address. In this case, i ₁
The address for reading the previous musical tone data GD (t-i ₁ ) is determined by the above-mentioned equation (1). The musical tone data GD (t-i ₁ ) with a delay time i ₁ read out in this way is input to a multiplier M1, and in this multiplier M1, the first reflected sound ECH ₁ with a delay time i ₁ is inputted into the multiplier M1.
is multiplied by a coefficient K ₁ for amplitude level control corresponding to . Then, the multiplied value K ₁ ·GD (ti ₁ ) is input to the adder SUM1 and added to the current value of the register R0, and the added value is stored again in the register R0. In this case, the contents of the register R0 are reset immediately after writing the musical tone data GD(t) at the current time t, so the contents written to the register R0 at this time are the data _K1 ·GD(t-i ₁ ). In this way, musical tone data GD with delay time i ₁
When the readout process and level control process for (t-i ₁ ) are completed, that is, when the process regarding the first reflected sound ECH ₁ is completed, the second reflected sound with delay time i ₂ is
The reading process and level control process of the musical tone data GD(t-i ₂ ) regarding ECH ₂ are performed in the same manner as the process of forming the first reflected sound ECH ₁ . As a result, register R0 in adder SUM1 contains the first reflected sound.
The sum of the data _{K 1 ·} GD (t-i ₁ ) regarding ECH 1 and the data K ₂ · GD (t-i ₂ ) regarding the second reflected sound ECH ₂ is "K ₁ · GD (t-i ₁ ) + K ₂・GD(t−i ₂ )” is stored. Such processing is similarly performed for the third reflected sound _ECH3 to the tenth reflected sound _ECH10 . As a result, the register R0 contains musical tone data _K1 ·GD(t- _i1 )- related to the first reflected sound _ECH1 to the tenth reflected sound _ECH10 .
The total sum of K ₁₀ ·GD (t-i ₁₀ ) ₁₀ 〓 ⁿ⁼¹ K _o ·GD (t-i _o ) is stored. And this total ₁₀ 〓 ⁿ⁼¹ K _o・GD(t−
i _o ) is outputted via the switch circuit SW as the instantaneous value ECH(t) of the initial reflected sound consisting of the first reflected sound ECH ₁ to the tenth reflected sound ECH ₁₀ . As shown in Table 1 below, the switch circuit SW selectively outputs the output of the register R0 at the initial reflected sound formation processing time Ta within one sampling period _T0 , At Tb, the output of the second delay circuit series is selectively output.

[Table] The data ECH(t) selectively output by this switch circuit SW is converted into an analog signal by the DA converter shown in FIG. 1 or the DA converters 12 and 14 shown in FIG. ,13
It is added to the input musical tone and is pronounced as an early reflection sound for the input musical tone. Therefore, the first reflected sound ECH ₁ to the 10th reflected sound ECH ₁₀
By varying the delay time i _o and the coefficient K _o for amplitude level control, it is possible to obtain an early reflected sound whose amplitude level and delay time randomly change as shown in FIG. 10. Here, the sampling period T ₀ of the input musical tone is
When setting the frequency to 0.04ms (25KHz), if musical tone data GD(t-1626) stored at an address 1626 words away from the write address ADR(t) of musical tone data GD(t) at current time t is read. , the delay time i is i=1626×0.04≒6.5ms, and the early reflection sound is delayed by about 65ms from the input musical tone.
Can generate ECH _o . On the other hand, the musical tone data GD(t) obtained by sampling the input musical tone at a predetermined period T ₀ is also supplied to the second delay circuit series that forms the reverberant sound after the initial reflected sound is generated. This second delay circuit series is connected to the musical tone data GD.
(t) is delayed by j hours to create a bandpass filter BPF.
Delay memory D10 supplied to
Musical tone data GD with delay time j supplied from D10
A digital band-pass filter BPF consists of a low-pass filter LPF and a high-pass filter HPF that pass only a predetermined frequency band component of (t-j), and musical tone data GD (t-j) that has passed through the band-pass filter BPF. A first reverberation sound forming unit 2000 having a comb filter configuration forms reverberation sound data RVD ¹ with a coarse delay time interval based on the reverberation sound data RVD ¹ , and reverberation sound data RVD 2 with a dense delay time interval is formed based on the reverberation sound data RVD ¹ . The second reverberation sound forming section 3000 has an all-pass filter configuration. In such a configuration, the musical tone data GD(t) at the current time t is the address corresponding to the current time t among the 2048 word storage addresses in the memory D10.
Written to ADR(t). Next, among the musical tone data GD(t) stored in the memory D10, data GD(t-j) from j hours ago is read out, so the delay time j
The address of memory D10, corresponding to is specified,
Musical tone data GD (t-j) sampled j hours ago is read from the address. in this case,
The address for reading the musical tone data GD (t-j) of j hours ago is determined by the above-mentioned equation (1), as in the case of forming the early reflected sound. The delay time j here is set to be slightly larger than the delay time i ₁₀ regarding the 10th reflected sound ECH ₁₀ (j>i ₁₀ ). The musical tone data GD(t-j) of delay time j read from the memory D10 in this manner is input to the multiplier M11 of the low-pass filter LPF, where it is multiplied by a predetermined coefficient _K11 . Then, the multiplied value _K11 ·GD(tj) is temporarily stored in the register R1. Next, musical tone data GD (t-j-1) written one sampling time (1·T ₀ ) before is read from memory SD0 having a storage address of one word, and this data GD (t-j- 1) is multiplied by a predetermined coefficient _K12 in a multiplier M12. Next, the multiplier output _K12・GD(t-i-
1) and musical tone data K ₁₁ · GD (t-j) from j hours ago, which is temporarily stored in register R1, are added, and the added value is "K ₁₂ · GD (1-j-1) + K ₁₁ ·
GD(t-j)'' is temporarily stored again in register R1 and also temporarily stored in register R2. Next, one sampling time (1・
T ₀ ) Previously written musical tone data GD (t-j-1)
is read out again from memory SD0, and this data GD
(t-j-1) is multiplied by a predetermined coefficient _K13 in a multiplier M13. And this multiplier K ₁₃・
GD (t-j-1) is the value temporarily stored in register R2 "K ₁₂・GD (t-j-1) + K ₁₁・GD (t
−i)” and the added value K ₁₂・GD (t−j−1) + K ₁₁・GD (t−j) +K ₁₃・GD (t−j−1) is temporarily stored again in register R2. Ru. Next, the value “K ₁₂・GD(t
−j−1)+K ₁₁・GD(t−j)” in the next sampling period (t+1), this value “K ₁₂・GD(t−j−1)+K ₁₁・GD(t−j )” is written to memory SD0. By performing such an operation every sampling period _T0 , the low pass filter LPF
The register R2 outputs musical tone data GD (t-j) of j hours ago from which high frequency components in a predetermined band have been removed, and this musical tone data GD (t-j) is sent to a high-pass filter HPF. Then, the high-pass filter HPF removes low frequency components in a predetermined band from the musical tone data GD (t-j) of j hours ago in the same way as the low-pass filter LPF. In other words, the register of the low pass filter LPF
The output data GD(t-j) of R2 is inputted to a multiplier M14, and in this multiplier M14, a predetermined coefficient K ₁₄
is multiplied by Then, the multiplication value K ₁₄・GD(t
-j) is temporarily stored in register R3. next,
Musical tone data GD (t-j-1) written one sampling time (1・T ₀ ) ago is read from memory SD1 having a storage address of one word, and this data GD (t-j-1) is Predetermined coefficient K ₁₅ multiplier
Multiplied in M15. Next, the multiplication value _K15 ·GD(t-j-1) obtained from the multiplier M15 is added to the musical tone data _K14 ·GD(t-j) from j hours ago, which is temporarily stored in the register R3. , the added value “K ₁₄・GD(t−j)+K ₁₅・GD(t−j−1)” is temporarily stored in register R3 and also
It is also temporarily stored in R4. Next, the data GD (t-j-1) written one sampling time (1·T ₀ ) before the current time t is read out again from the memory SD1, and this read data GD (t-j-1) is multiplied by a predetermined coefficient _K16 in a multiplier M16. And this multiplication value K ₁₆・GD(t-j-1)
is the value temporarily stored in register R4 “K ₁₄・
GD (t-j) + K ₁₅・GD (t-j-1)'', and the added value K ₁₆・GD (t-j-1) + K ₁₄・GD (t-j) +K ₁₅・GD ( t-j-1) is temporarily stored in register R4. Next, the value “ _K14・GD(t−
j)+K ₁₅・GD(t-j-1)" is used in the next sampling period (t+1), so this value "K ₁₄・GD(t-j)+K ₁₅・GD(t-j-1) ” is written to memory SD1. By performing such an operation every sampling period _T0 , the register R4 of the high-pass filter HPF outputs musical tone data GD (t-j) of j hours ago, from which low frequency components in a predetermined band have been removed. Note that register R1 of the low-pass filter LPF is
After the contents of this register are written to the memory SD0, it is not used until the next sampling period, so it can be shared with the register R3 of the high-pass filter HPF. In this way, the bandpass filter BPF removes the low frequency components and high frequency components of a predetermined band from musical tone data GD(t-j) j hours ago.
is input to the first reverberant sound forming section 2000. The first reverberation sound forming section 2000 includes delay circuits 2000A and 20 having comb-type filter configurations having different delay times.
00B and 2000C are provided in parallel. 3
delay circuits 2000A, 2000B, 2000
The reason why C is provided in parallel is to flatten the frequency characteristics of a delay circuit with a comb-type filter configuration, which would be wavy as shown by symbols A, B, and C in Fig. 11 if it were used alone. It's for a reason. In other words, three delay circuits 2000A and 2000 with different delay times
By providing 00B and 2000C in parallel,
The overall frequency characteristic can be flattened as shown by symbol D in FIG. In this case, the degree of flattening improves as the number of parallel connection of delay circuits increases. In this embodiment, the delay time of delay circuit 2000A is set to be the longest, followed by the longest delay time of delay circuit 2000B, and the delay time of delay circuit 2000C is set to be the shortest. And each delay circuit 200
0A, 2000B, and 2000C have the same configuration except for the delay time settings. Therefore, in the figure, circuits 2000B and 20
Regarding 00C, only the numbers of the multipliers, registers, and memories are shown, and only the delay circuit 2000A is shown in detail. In the first reverberation sound forming section 2000 having such a configuration, the j that has passed through the bandpass filter BPF is
The previous musical tone data GD (t-j) is first multiplied by a coefficient _K17 for amplitude level control in a multiplier M17. Then, the multiplication value K ₁₇・GD(t−
j) is temporarily stored in register R5 in multiplier M17. Next, musical tone data GD ( _t
-x ₁ ), the address of memory D1 corresponding to the delay time x ₁ is specified. By this,
Musical tone data GD from memory D1 x ₁ hour ago (t-x ₁ )
is read out. Then, this musical tone data GD(t
−x ₁ ) is supplied to the adder SUM2, and this adder
In SUM2, the output data of the other memories D2 and D3 and the output data of the memories D4 to D6 and D7 to D9 of the delay circuits 2000B and 2000C are added and temporarily stored in the register R11 in the adder SUM2. In this case, the read operation of the memories D1 to D9 is performed sequentially in time division from the memories D1 to D9, and when the read operation of the memory D1 is performed, no data is output from the other memories D2 to D9. Therefore, the content written to the register R11 in the adder SUM2 becomes the data GD (t-x ₁ ) read from the memory D1. On the other hand, musical tone data GD read from memory D1
(t-x ₁ ) is multiplied by K ₁₈ for amplitude level control in multiplier M18 and then fed back to the input side of memory D1. Then, this multiplication value K ₁₈・GD(t−x ₁ )
is added to the data K ₁₇ · GD (t-j) temporarily stored in register R5 at the current time t, and the added value K ₁₇ · GD (t-j) + K ₁₆ · GD (t-x ₁ ) is Temporarily stored in R6. Next, the musical tone data “K ₁₇・GD(t-
j)+ _K18 ·GD(t-x1)" is written to the same address where the musical tone data GD(t- _x1 ) x ₁ hours ago was stored. After this, register
The contents of R6 are reset. The reason why the contents of register R6 are reset is because this register R6 will also be used for the processing of the memory D2 system in the next stage. When the processing of the memory D1 system is completed in this way, the processing of the memory D2 system is performed in the same manner. i.e. memory with 2048 word addresses
Musical tone data GD ( _t-
x ₂ ), the memory corresponding to the delay time x ₂
The address of D2 is specified. As a result, the musical tone data GD (t-x ₂ ) sampled x ₂ hours ago is read from the memory D2. Then, this musical tone data GD(t-x ₂ ) is added to the contents of the register R11 (the contents read from the memory D1) GD(t-x ₁ ) in the adder SUM2, and the added value ``GD(t-x <sub>1</sub> )+GD(t- <sub>x2</sub> )" is temporarily stored in register R11. On the other hand, musical tone data GD read from memory D2
(t-x <sub>2</sub> ) is multiplied by a coefficient K <sub>18</sub> for amplitude level control in a multiplier M <sub>19</sub> and then fed back to the input side of the memory D <sub>2</sub> . Then, the multiplication value K <sub>19</sub>・GD(t
−x <sub>2</sub> ) is the value temporarily stored in register R5
<sub>K17.GD</sub> (t-j) is added, and the added value " <sub>K17.GD</sub> (t-j)+ <sub>K19.GD</sub> (t- <sub>x2</sub> )" is temporarily stored in register R6. The data stored in this register R6 is ``K ₁₇・GD(t-j)+K ₁₉・GD
(t-x ₂ )" is the data GD (t-x ₂ ) x ₂ hours ago
is stored at the same address where it was stored. After this, the contents of register R6 are reset. Next, processing of the memory D3 system is performed in the same manner as the processing of the memory D2 system. Therefore, at the stage when the processing of the memory system D1 to D3 is completed, if the delay time of the memory system D3 is x ₃ , the content stored in the register R11 is GD (t-x ₁ ) + GD (t- x ₂ )+GD(t−x ₃ ), and the content stored in the memory D3 is K ₁₇ ·GD(t−j)+K ₂₀ ·GD(t−x ₃ ). Such processing is performed by the delay circuits 2000B and 200
The same operation is performed at 0C. Therefore, the delay times of the memories D4, D5, D6 in the delay circuit 2000B are x ₄ , x ₅ , x _6, respectively, and the memories D7, D8, D6 in the delay circuit 2000C are
Assuming that the delay times of each musical style of D9 are x ₇ , x ₈ , and x ₉ , respectively, the contents of register R11 at the stage when all processes of delay circuits 2000A to 2000C are completed are RVD ¹ = ₁₀ 〓 ⁿ⁼¹ GD (t-x _o ) = GD (t-x ₁ ) + GD (t-x ₂ ) + GD (t-x ₃ ) + GD (t-x ₄ ) + GD (t-x ₅ ) + GD (t-x ₆ ) + GD (t- _x7 )+GD(t- _x8 )+GD(t- _x9 ). As a result, following the early reflected sound, a reverberant sound is obtained in which the delay time interval is coarse and the amplitude level and delay time change regularly, as shown in FIG. Note that in FIG. 12, the reverberant sound for only the delay circuit 2000A is illustrated because the time relationship is complicated. The reverberant sound data RVD ¹ with a coarse delay time interval formed as described above is transmitted to the second reverberant sound forming unit 30.
00 is input. The second reverberation sound forming section 3000 includes a delay circuit 300 having an all-pass filter configuration with flat frequency characteristics.
0A, 3000B, and 3000C are provided in series. 3 delay circuits 3000A, 3000B, 30
00C is provided in series with the reverberant sound data RVD ¹ obtained in the first reverberant sound forming section 2000.
This is to form reverberant sound data RVD ² with closer delay time intervals. Therefore, each delay circuit 3000A, 30 in this second reverberation sound forming section 3000
The delay times of 00B and 3000C are the delay times of each delay circuit 2000A and 2 in the first reverberation sound forming section 2000.
The delay time is set shorter than the delay time of 000B and 2000C. And each delay circuit 3000A, 300
0B and 3000C have the same configuration except for the delay time setting. Therefore, in the figure, only the numbers of multipliers, registers, and memories are shown for delay circuits 3000B and 3000C, and the detailed configuration of only delay circuit 3000A is shown. First, the reverberant sound data RVD ¹ output from the first reverberant sound forming section ²⁰⁰⁰ is supplied to the register R12 of the delay circuit 3000A. To read data RVD ¹ (t-y ₁ ) written y ₁ hour ago in memory MD0 having
The address of memory MD0 corresponding to delay time y ₁ hour is specified. As a result, the data written y ₁ hour ago from memory MD0 RVD ¹ (t-y ₁ )
is read out. Next, this data RVD ¹ (t−y ₁ )
is multiplied by a coefficient K ₃₀ for amplitude level control in a multiplier M30, and the multiplier value K ₃₀ ·RVD ¹ (t-
y ₁ ) is fed back to the input side of memory MD0. Then, this feedback data K ₃₀ ·RVD ¹ (t−y ₁ ) and the data RVD ¹ (t) supplied from the first reverberation sound forming section 2000 at the current time t are added, and the added value “RVD ¹ (t)+K ₃₀ ·RVD ¹ (t−y ₁ )” is temporarily stored in register R12. Next, the address of memory MD0 corresponding to delay time y ₁ is specified again,
Memory MD0 to y Data written ₁ hour ago
RVD ¹ (t-y ₁ ) is read out again, and the read data RVD ¹ (t-y ₁ ) is temporarily stored in register R13. Next, the data “RVD ¹ (t)+K ₃₀ ·RVD ¹ (t−y ₁ )” temporarily stored in the register R12 is multiplied by a constant K ₂₉ for amplitude level control in a multiplier M29. Then, the multiplied value K ₂₉ · {RVD ¹ (t) + K ₃₀ · RVD ¹ (t−y ₁ )} is the value RVD ¹ (t
−y ₁ ), and the added value RVD ¹ (t−y ₁ )+K ₂₉ ·{RVD ¹ (t)+K ₃₀ ·RVD ¹ (t−y ₁ )} is temporarily stored in register R13. Next, the data “RVD(t)” temporarily stored in register R12
+K ₃₀・RVD ¹ (t−y ₁ )” is used at the sampling time (t+y ₁ ) that is y ₁ hour behind the current time t, so the data “RVD ¹ (t)+K ₃₀・
RVD ¹ (t- _{y 1} )" is the data RVD ¹ (t-
y ₁ ) is written to the same address where it was stored. When the processing by the delay circuit 3000A is completed in this way, the data RVD ¹ (t-y ₁ ) + K ₂₉ · {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y)} stored in the register R13 is delayed. is sent to circuit 3000B, and this delay circuit 3
In 000B, the same processing as in the case of circuit 3000A is performed. Here, delay circuits 3000A, 3000B, 3
000C output data as RVD ^2A , RVD ^2B ,
Expressed as RVD ^2C , the delay time of circuit 3000B is
y ₂ , and the delay time of circuit 3000C is y ₃ , the output data of registers R13, R15, and R17 of circuits 3000A, 3000B, and 3000C are expressed by the following equation (4) ~
It is expressed by equation (6). RVD ^2A = RVD ¹ (t-y ₁ ) + K ₂₉・{RVD ¹ (t) + K ₃₀
・RVD ¹ (t-y ₁ )}...(4) RVD ^2B = RVD ^2A (t-y ₂ )+K ₃₁・{RVD ^2A (t)+K _3
2・RVD ^2A (t−y ₂ )}……(5) RVD ^2C = RVD ^2B (t−y ₃ )+K ₃₃・{RVD ^2B (t)+K _3
4・RVD ^2B (t-y ₃ )}...(6) And the output data of the delay circuit 3000C
RVD ^2C is output via the switch circuit SW as data for generating reverberant sound following the initial reflected sound. Here, each delay circuit 3000A, 3000B,
When the delay time of 3000 C is set in the relationship y ₁ > y ₂ > y ₃ , reverberant sound with dense delay time intervals can be formed as shown in FIG. That is, the delay circuit 3000A generates the first reverberation sound at a time interval y 1 shorter than the delay time interval of the first reverberation sound formation unit 2000 based on the reverberation sound data RVD ¹ with a coarse delay time interval formed by the first reverberation sound formation unit ₂₀₀₀ . 1 reverberant sound data RVD ^2A , and the delay circuit 3000B generates the second reverberant sound data at a time interval _y2 shorter than the delay time interval _y1 of the circuit 3000A.
Form RVD ^2B . Therefore, the delay circuit 300
As the reverberation sound formation process from 0A to 3000C progresses, reverberation sounds with dense delay time intervals are formed. In addition, the delay circuits 3000A, 3000B, 30
Registers R12, R14, and R16 at 00C are not used until the next sampling period after the processing related to their own circuit is completed, so that they can be shared in a time-division manner. Next, the specific configuration and operation of the embodiment shown in FIG. 5 will be explained. In addition, in the following explanation,
The following description will be made assuming that the apparatus shown in FIG. 5 forms reverberation sound according to the function shown in FIG. 7 described above. Specific Structure of the Embodiment The reverberation sound adding device of the embodiment shown in FIG. 5 is roughly divided into a storage section 19, a time information generation section 20, an address information generation section 30, and a calculation section 40. The storage section 19 corresponds to the delay digital memory DM in FIG. 8, and here is composed of a data memory 190 having a plurality of memory blocks and a latch 191. The data memory 190 uses a plurality of memory blocks to store 1 word (16 bits) memories SD0 to SD15 and 512 word (1 word 16 bits) memories MD0 to MD15, as shown in FIG. and memories D0 to D15 for 2048 words (one word is 16 bits) are provided. And this memory SD0~SD15, MD0~
The data to be stored in MD15, D0 to D15 is the calculation unit 4
The data storage address and read address are specified by the address information DM/ADR output from the address information generating section 30, and the data read from each memory SD0 to D15 is given from the latch 191. The configuration is such that the data is supplied to the calculation unit 40. The time information generating section 20 corresponds to the delay length data memory DDM in FIG. Depending on the instructions, each data delay memory D0 to D15,
Delay time information regarding MD0 to MD15 DLD ^m [n]
(n: Indicates D0 to D15, MD0 to MD15 memory,
m: designates types 1 to 8), and is configured to selectively output any one type.
That is, the delay length data memory 201
As shown in FIG.
(MD0) to MB (MD15), and each memory block MB (D0) to MB (MD15) has eight memory addresses "0" to "7" corresponding to the eight types of reverberant sounds described above. and each memory block MB
(D0) ~ Each memory address "0" of MB (MD15) ~
"7" has different delay time information DLD ¹
[D0] ~ DLD ⁸ [D0], DLD ¹ [D1] ~ DLD ⁸ [D1],
...DLD ¹ [D15] ~ ^{DLD 8} [D15], DLD ¹ [MD0]
~DLD ⁸ [MD0],...DLD ¹ [MD15] ~DLD ⁸
[MD15] is stored in advance. Then, 3-bit parameter designation information PSL indicating the reverberation characteristics of the reverberant sound to be generated is supplied from the parameter designation circuit 200 as lower address information, and memory numbers "0 to 15" of the memories MD0 to MD15 and D0 to D15 are supplied as low-order address information. ” 4-bit memory number information DL _o (n: 0 to 15) and 2-bit memory type information DL _k (k: D, MD, SD) that specifies the memory type “D, MD, SD.” SD) is supplied from the address information generation unit 30 as upper address information, one of the memory blocks (MB (D0) to MB (MD15) specified by the information DL _o and DL _k
among them), the delay time information DLD ^m [n] stored in the memory address (one of "0" to "7") specified by the information PSL is read out and The information is supplied to the address information generating section 30 as information defining the delay time relationship of reverberant sound having desired reverberation characteristics. In addition, memory SD0
~For SD15, the delay time is fixed (1・T ₀ )
Therefore, delay time information for the memories SD0 to SD15 is not required. Further, from the parameter designation circuit 200, along with the parameter designation information PSL, 3-bit program selection information PGS for selecting one of the desired control programs from among the eight types of control programs for forming reverberant sound is provided.
is output. Next, the address information generation section 30 generates the delay time information DLD ^m [n] output from the time information generation section 20.
Based on the program selection information PGS and the master clock pulse φ ₀ that determines the cycle of one step of the control program, address information DM/ADR for the data memory 190 for forming reverberant sound with desired reverberation characteristics is generated. It also generates various control signals to control the operation of each circuit, and includes a program memory 300, a program counter 301, and a program decode memory 3.
02, control signal output register 303, selector 3
04, address counter 305, latch 306,
It includes a subtraction circuit 307, a maximum value detection circuit 308, and an address information output circuit 309. Eight types of control programs are stored in advance in the program memory 300 in order to form reverberant sounds with eight types of reverberation characteristics, and the parameter specifying circuit 200 determines which type of control program should be output.
It is designated by program selection information PGS starting from 0. Then, the contents of the designated control program are sequentially read out step by step by the output information PC of the program counter 301 that counts the master clock pulse φ ₀ . In this case, all processes of the early reflected sound forming section 1, band pass filter BPF, first reverberant sound forming section 2000, and second reverberating sound forming section 3000 explained in FIG. 6 are performed within one sampling period (T ₀ ). To finish, if the sampling frequency is 25KHz and the frequency of master clock pulse φ ₀ is 4.8MHz,
The number of steps in one control program is within 4800/25=192, and the contents of the 192-step control program are executed every sampling period _T0 . As for the control program for each step, as shown in Table 2, one step consists of 16
Three types of content, Type 1, Type 2, and Type 3, consisting of bit information are prepared, and the formation of early reflected sound, filter processing, and reverberation sound are determined by the output order of these three types of control programs and each bit. This is done by appropriately combining information contents.

[Table] In this case, the one-step control program consisting of 16 bits is the information OF・ADR _o , RG _o , DL _o ,
Control signal output register 303 like ADR [K _o ]
There are two types of signals: those that are output as they are through the memory write control signal WR1, and those that are decoded by the program decode memory 302 and then output via the control signal output register 303, such as the memory write control signal WR1. The code OPC is given from program memory 300 to program decode memory 302. Note that details of the contents of Table 2 will be described later together with an explanation of the overall operation. On the other hand, the address counter 305 is connected to delay memories D0 to D15, MD0 to
Address counter compatible with each MD15
AC (D0) ~ AC (D15), AC (MD0) ~ AC
(MD15). Each counter AC (D0) to AC in this address counter 305
(D15), AC (MD0) to AC (MD15) are selectively brought into operation according to memory number information DL _o and memory type information DL _K. Address counter AC _(o) activated by information DL _o and DL _k
Count output information ADR[n] of (n: D0 to D15, MD0 to MD15) is supplied to the address information output circuit 309 via the latch 306 and also to the subtraction circuit 307. In this case, the output information ADR[n] of address counter AC _(o) is from memory D0 to
Among D15, MD0 to MD15, memory D0 to D15 is 2048
Since the address length is 1 word, it is composed of 11 bits so that an address range of up to 2048 words can be specified. Note that the address counter 305 is
Consists of RAM. The subtraction circuit 307 receives the output content ADR of the address counter AC _(o) inputted via the latch 306.
Subtract “1” from [n] and calculate the subtracted value “ADR [ _o ] - 1” at the next sampling period (t
+1) is fed back to the A-side input of selector 304 for use. At the same time, the maximum value detection circuit 308
supply to. The maximum value detection circuit 308 corresponds to the detection circuit MXD in FIG. 8, and outputs the output information ADR[n] of the address counter AC _(o) specified by the memory number information DL _o and the memory type information DL _k .
When it is detected that the information "ADR[n]-1" obtained by subtracting "1" from "ADR[n]-1" has reached the maximum value (all bits are "1"), a select control signal SLB is sent to the selector 304 to select the B side input. Output. In the selector 304, the output information "ADR[n]-1" of the subtraction circuit 307 is inputted to the A side input, and the output information DLD ^m [n] of the delay length data memory 201 is inputted to the B side input, and the output is supplied to the data input of address counter 305 to input the information
Address counter specified by DL _o and DL _k
The configuration is such that data is written (preset) to AC _(o) by a write control signal WR3.
Therefore, in the address counter AC _(o) specified by the information DL _o and DL _k , the maximum value detection circuit 3
Under the condition that the select control signal SLB is not generated from 03 onwards, the current value is
ADR[n] - the value obtained by subtracting "1" from ADR[n]
1” will be written, and the output information
ADR[n] decreases toward "0" as time passes. However, when the value "ADR(n)-1" reaches the maximum value, the select control signal SLB is generated from the maximum value detection circuit 308, so the delay time information DLD is sent to the address counter AC _(o) via the selector 304. ^m [n] is input and written. Therefore, the contents of the address counter AC _(o) become "DLD ^m [n]" due to the generation of the select control signal SLB, and then sequentially change toward "0" as the sampling time elapses. That is, selector 304, address counter 305, latch 3
06, the part consisting of the subtraction circuit 307 and the maximum value detection circuit 308 calculates the delay time information at the address counter AC _(o) specified by the information DL _o and DL _k .
Address information ADR [n] that goes around in a cycle equal to the delay time corresponding to DLD ^m [n] is formed. This address information ADR[n] is supplied to the address information output circuit 309. The address information output circuit 309 outputs memories SD0 to
It outputs address information for reading and writing information to and from SD15, memories D0 to D15, and memories MD0 to MD15. This address information output circuit 309 outputs address information ADR[D0] regarding memory D0 when reading information delayed by i _o time from memory D0 to form early reflected sound ECH _(t).
and 11-bit address information OF corresponding to each delay time i _o of the first reflected sound ECH ₁ to the tenth reflected sound ECH ₁₀ .
The added value of ADR _o (=OF・ADR ₁ to OF・ADR ₁₀ : output from the control signal output register 303) is used as the lower address information, and the memory number information DL _o (=DL ₀ ) and memory type are placed above it. Information DL _k (=
DL _D ) is added, and this set of information ADR [D0] +
OF・ADR _o , DL _o , DL _k as address information DM・
Output as ADR. In addition, when writing musical tone data GD _(t) sampled at the current time to memory D0, the address counter AC corresponding to memory D0 is
(D0) output information ADR [D0] is the lower address information, and information that specifies memory D0 above it DL _o
(=DL ₀ ) and DL _k (=DL _D ), and this 1
Set information ADR [D0], DL _o , DL _k as address information
Output as DM/ADR. Also, memory SD0~
When writing and reading data to and from SD15, all bits of the lower address information are set to "0", and information DL _o (=DL 0 to DL 15 ) and DL k (=DL ₀ to DL ₁₅ ) and DL _k ( =DL _SD ) is added and output as address information DM/ADR.
In addition, when forming reverberant sounds RVD ¹ and RVD ² ,
Address counters AC (D1) to AC (D15) corresponding to memories D1 to D15, MD0 to MD15, respectively,
AC (MD0) to AC (MD15) output information ADR
[D1] ~ ADR [D15], ADR [MD0] ~ ADR
[MD15] is the lower address information, information DL _o and DL _k are added to the upper part, and this set of information
Output ADR [n] and DL _k as address information DM/ADR. In this case, when the information ADR [D0] + OF・ADR _o should be added to the lower part of the information DL _o and DL _k , a control pulse is sent from the control signal output register 303.
GP1 is output. Also, when all bits of the lower address information added to the lower part of the information DL _o and DL _k should be set to "0", the control signal output register 3
Control pulse GP2 is output from 03. Note that the address information output circuit 309 outputs information
It has internal registers to temporarily store DL _o and DL _k . Next, the calculation unit 40 stores memories D0 to D15, MD0.
It controls the amplitude level of the data stored in ~MD15, SD0~SD15 and the data read from each memory, and the coefficient memory 400 and selector 40
1, arithmetic circuit 402, temporary register 40
3, a latch 404. Like the delay length data memory, the coefficient memory 400 has eight memory blocks corresponding to eight types of reverberant sounds with different reverberation characteristics, and each memory block has the memory blocks necessary to form each type of reverberant sound. A set of coefficients K _o (n: 1 to 64) is stored in advance. And the parameter specification circuit 200
When the parameter specification information PSL is supplied from the control signal output register 303 and the address information ADR [K _o ] specifying the coefficient K _o is supplied from the control signal output register 303, the information
Information about memory blocks specified by PSL
The coefficient K _o is read from the address specified by ADR [K _o ] and is supplied to the arithmetic input (A) of the arithmetic circuit 402. The selector 401 inputs musical tone data to the A side input.
GD _(t) is input, read data MRD from the storage unit 10 is input to the B side input, output data RGD of the temporary register 403 is input to the C side input via the latch 404, and these input data GD _(t) , MRD, and RGD are the select control signal SL1 output from the control signal output register 303
(2-bit configuration), one of them is selected and supplied to the calculation input (X) of the calculation circuit 402. The arithmetic circuit 402 has a coefficient memory 4 at the arithmetic input (A).
The coefficient K _o read from 00 is input, the output data RGD of the temporary register 403 is input to the calculation input (B) via the latch 404, and the selected output data (SPD) of the selector 401 is input to the calculation input (X).
(t), MRD, RGD) is input, and the calculation control signal is output from the control signal output register 303.
With CTL (3-bit configuration), (Y)=(A)・(X)+(B)...(7-1) (Y)=(X)+(B)...(7-2) (Y )=(X) ……(7-3) (Y)=(B) ……(7-4) (Y)=(O) ……(7-5) and calculate the calculated value ( Y) as temporary register 403, storage section 19, output register 50
0. The temporary register 403 stores the early reflection sound.
ECH (t), the calculation value (Y) of the calculation circuit 402 in the process of forming the reverberant sounds RVD ¹ and RVD ² is temporarily stored, and the stored contents are set as register output data RGD and input to the C side of the selector 401 and the calculation circuit 40
It has 32 registers R0 to R31 specified by 5-bit register designation information RG _o (n: 0 to 31), and the input data is fed back to the calculation input (B) _of No. 2. The data is written to the register (R0 to R31) specified by the write control signal WR1 under the control of the write control signal WR1. Next, the output register 500 is connected to the arithmetic circuit 402.
The instantaneous value ECH (t) of the early reflected sound obtained as the calculated value (Y) of output via the device 501. Note that the select control signal SL1 in the selector 401 and the calculation control signal CTL in the calculation circuit 402 are included in the operation code OPC output from the control signal output register 303. Next, the operation of the above configuration will be explained. Operation explanation a Early reflection sound formation operation (1) First, in order to write the musical sound data GD (t) sampled at the current time t to the memory D0, SL1; SELECT (A) CTL; (Y) = (X) The select control signal SL1 and calculation control signal CTL with the contents shown are the operation code.
It is output from the control signal output register 303 as OPC. Thereby, the selector 401 supplies musical tone data GD(t) to the calculation input (X) of the calculation circuit 402. In addition, the arithmetic circuit 402
is the musical tone data input to the calculation input (X)
Output GD(t) as a calculated value (Y). (2) Next, specify the address of the memory D0 corresponding to the current sampling time (t), and then input the output data GD of the arithmetic circuit 402 to this address.
(t), the memory type information DL k with the contents indicated by DL _o ; DL ₀ DL _k ; DL _D WR4; “1” (WRITE) L3; _“ 1” (LATCH), the write control signal WR4, The latch control signal L3 is outputted from the control signal output register 303 as the operation code OPC, and the memory number information _DLO is outputted. As a result, the output information ADR [D0] of the address counter AC (D0) corresponding to the memory D0 is latched in the latch 306 as the lower address information for writing the musical tone data GD (t) at the current time t. . Then, this latched lower address information ADR [D0] is sent to the address information output circuit 309 where memory number information is sent to the upper level.
DL _o (=DL ₀ ) and memory type information DL _k (=
DL _D ) is added to write address information DM of musical tone data GD(t) to memory D0.
Output as ADR. As a result, the memory of the data memory 190 is transmitted through the arithmetic circuit 402
The current time t given to the data input of D0
The musical tone data GD(t) is the write control signal WR4
is written to the address corresponding to the current time t. (3) Next, in order to clear the register R0 that stores the composite value of early reflection sounds for each sampling time, the contents indicated by RG _o ; R0 CTL; (Y) = 0 WR1; “1” (WRITE) The arithmetic control signal CTL and write control signal WR1 are output as the operation code OPC, and the register number information RG _o is output from the control signal output register 303. As a result, "0" is written into register R0. That is, register R0 is cleared. (4) Next, in order to form the first reflected sound ECH ₁ , the memory with the contents indicated by OF・ADR _o ;OF・ADR ₁ DL _k ;DL _D GP1; “1” L2; “1” (LATCH) Type information DL _k , control pulse GP1, latch control signal L2 as operation code OPC, and address information OF/ADR ₁ corresponding to delay time i ₁ of first reflected sound ECH ₁
is output from the control signal output register 303. In this case, the address information output circuit 309 contains the memory number information DL _o in step (3).
(=DL ₀ ) is held. As a result, address information output circuit 309
Adds the address information ADR [D0] latched in the latch 306 and the address information OF・ADR ₁ corresponding to the delay time i ₁ , sets the added value as lower address information, and sets the memory number information DL _o
(=DL ₀ ), memory type information DL _k (=DL _D ) as upper address information, and address information DM for reading amplitude data SPD (t-i ₁ ) written i ₁ hour ago from memory D0.・Output as ADR.
As a result, musical tone data GD (ti ₁ ) from i ₁ hour ago is read from memory D0, and this read data
GD(t-i ₁ ) is latched into latch 191 by latch control signal L2. (5) Next, latch 404 the current value of register R0.
In order _to transfer to
RG _o is output from the control signal output register 303. This causes the current value of register R0 to be transferred to latch 404 and stored. (6) Next, the musical tone data GD (t-i ₁ ) of _one hour before i is multiplied by the coefficient K ₁ for amplitude level control, and _{the instantaneous value K 1 ·} GD (t-i ₁ ), calculate the select control signal SL1 shown by ADR[K _o ]; ADR[K ₁ ] SL ₁ ; SELECT(B) CTL; (A)・(X)+(B)=(Y) The control signal CTL is the operation code OPC,
Also, address information ADR for reading constants [K _o ]
is output from the control signal output register 303. As a result, the coefficient K ₁ related to the first reflected sound ECH ₁ is read from the coefficient memory 400 and supplied to the calculation input (A) of the calculation circuit 402 . In addition, the selector 401 has a latch 191 at the B side selection input.
Musical sound data GD from i ₁ hour ago supplied by
(t-i ₁ ) is selected and the data GD (t-i ₁ ) is supplied to the calculation input (X) of the calculation circuit 402 . Further, the arithmetic circuit 402 performs the arithmetic operation expressed as (Y)=(A)*(X)+(B)= _K1 *GD(t- _i1 )+[R0]. In this case, the register
Since the contents of R0 have been cleared in step (3) above, the instantaneous value _K1 ·GD(t- _i1 ) regarding the first reflected sound _ECH1 is now sent to the arithmetic circuit 40.
It is obtained as the calculated value (Y) of 2. (7) Next, the instantaneous value _{K 1 ・}GD(t
−i ₁ ) to be stored in register R0, the write control signal WR1 with the contents indicated by RG _o ; R0 WR1; “1” (WRITE) is used as the operation code OPC, and the register number information RG _o is It is output from the control signal output register 303. As a result, output data (Y)=K ₁ ·GD (ti ₁ ) of the arithmetic circuit 402 is written into the register R0. By completing the steps up to this point,
Register R0 contains the instantaneous value of the first reflected sound ECH ₁ .
K ₁ ·GD (ti ₁ ) is obtained. (8) Next, 2nd reflected sound ECH ₂ ~ 10th reflected sound ECH ₁₀
Instantaneous value K ₂・GD (t-i ₂ ) ~ K ₁₀・GD
(t-i ₁₀ ) is formed in the same manner as steps (4) to (7) above. Therefore, when the operation of step (7) regarding the 10th reflected sound ECH ₁₀ is completed, the register R0 contains the 1st reflected sound ECH ₁ to the 10th reflected sound.
The sum of the instantaneous values of ECH _{10 10} 〓 ⁿ⁼¹ K _o · GD (t− _io ) is obtained. And this total ₁₀ 〓 ⁿ⁼¹ K _o・GD(t−
i _o ) is written to the output register 500 by the write control signal WR2 and transferred to the attenuator 501. b Filter operation (1) First, musical tone data from memory D10 j hours ago
To read GD (t-j), DL _o ; DL ₁₀ DL _k ; DL _{DL 3} ; “1” (LATCH) L2; “1” (LATCH) DL _k of memory type information, Latch control signals L3 and L2 are operation codes
Memory number information DL _o is also output from the control signal output register 303 as OPC. As a result, the output information ADR [D10] of address counter AC (D10) corresponding to memory D10
is used as the latch 306 as lower address information for reading musical tone data GD (t-j) j hours ago.
is latched to. Then, this latched lower address information ADR [D10] is outputted to the upper part of the address information output circuit 309 by memory number information DL _o (=DL ₁₀ ) and memory type information DL _k
(=DL _D ) is added and output to the memory D10 of the data memory 190 as read address information DM.ADR of musical tone data GD(tj). As a result, the musical tone data GD (t-j) of j hours ago is read from the memory D10, and this read data GD (t-j) is controlled by the latch control signal L2.
The signal is latched by the latch 191. (2) Next, in order to write the musical tone data GD (t) sampled at the current time t to the same address as the read address of the data GD (t-j), SL1; SELECT (A) CTL; (Y) = ( The select control signal SL1 and calculation control signal CTL with the contents shown in X) are the operation code.
It is output from the control signal output register 303 as OPC. Thereby, the selector 401 supplies musical tone data GD(t) to the calculation input (X) of the calculation circuit 402. In addition, the arithmetic circuit 402
is the musical tone data input to the calculation input (X)
Output GD(t) as a calculated value (Y). (3) Next, in order to write musical tone data GD(t) to memory D10, the contents indicated by DL _o ; DL ₁₀ DL _k ; DL _D WR4; “1” (WRITE) L3; “1” (LATCH) The memory type information DL _k , the write control signal WR4, and the latch control signal L3 are output as the operation code OPC, and the memory number information DL _o is output from the control signal output register 303. As a result, the output information ADR [D10] of address counter AC (D10) corresponding to memory D10
is latched in latch 306 as lower address information for writing musical tone data GD(t) at current time t. Then, this latched lower address information ADR [D10] is outputted in the address information output circuit 309 to its upper level by memory number information DL _o (=DL ₁₀ ) and memory type information DL _k (=
DL _D ) is added to write address information DM of musical tone data GD(t) to memory D10.
Output as ADR. As a result, the memory of the data memory 190 is transmitted through the arithmetic circuit 402
The current time t given to the data input of D10
The musical tone data GD(t) is the write control signal WR4
is written to the address corresponding to the current time t. (4) Next, in the low-pass filter LPF, calculate [R1] + K ₁₁ · GD (t - j) using the contents of register R1, coefficient K ₁₁ , and musical tone data GD (t - j) of j hours ago, In order to store this calculated value again in register R1, first, the latch control signal L1 indicated by the contents of RG _o ; R1 L1 ; “1” (LATCH) is used as the operation code OPC, and the register number information RG _o is used as the control The signal is output from the output register 303, and the contents of register R1 are latched 404.
will be forwarded to. (5) Next, in order to calculate K ₁₁・GD(t−j), ADR [K _o ]; ADR [K ₁₁ ] SL1; SELECT(B) CTL; (Y)=(A)・(X )+(B) The select control signal SL1 and calculation control signal CTL are the operation code OPC.
as well as address information for constant reading.
ADR [K _o ] is output from the control signal output register 303. As a result, the coefficients are stored in the coefficient memory 400.
_K11 is read and input to the calculation circuit 402 (A)
is supplied to In addition, the selector 401 is
- In step (1), the musical tone data GD (t-j) latched in the latch 191 is selected and supplied to the calculation input (X) of the calculation circuit 402. Thereby, the calculation circuit 402 performs the calculation (Y)=(A)·(X)+(B)=K ₁₁ ·GD(t−j)+R1. In this case, the contents of register R1 were cleared at the stage when the filter processing at the previous sampling time (t-1) was completed, so at this step _K11・GD(t-j)
is obtained as the calculated value (Y). (6) Next, this calculated value (Y) = K ₁₁・GD (t-j)
To store in register R1, the write control signal WR1 indicated by the contents of RG _o ; R1 WR1; “1” (WRITE) is output as the operation code OPC, and the register number information RG _o is output from the control signal output register 303. be done. As a result, the output data of the arithmetic circuit 402
_K11 ·GD(t-j) is stored in register R1. (7) Next, in order to read musical tone data GD (t-j-1) of (j-1) hours ago from memory SD0, DL _o ; DL ₀ DL _k ; DL _SD GP2; "1"L2;" 1” (LATCH), the memory type information DL _k , the latch control signal L 2 , and the gate pulse signal GP 2 are output as the operation code OPC, and the memory number information DL _o is output from the control signal output register 303 . Then, the memory information output circuit 309
sets all bits of the lower address information to “0” and stores the memory number information DL _o (=DL ₀ ) above it.
and memory type information DL _k (=DL _SD ),
Output as address information DM/ADR for memory SD0. As a result, musical tone data GD (t-j-
1) is read out and latched in latch 191. (8) Next, the contents of register R1 K ₁₁・GD(t−j),
Calculate _K12・GD(t-j-1)+[R1] using the coefficient _K12 and the musical tone data GD(t-j-1) latched in the latch 191, and store this calculated value in register R1 again. To do this, first, the latch control signal L1 with the contents indicated by RG _o ; R1 L1 ; "1" (LATCH) is output as the operation code OPC, and the register number information RG _o is output from the control signal output register 303, and the latch control signal L1 with the content indicated by RG o ;R1 L1; Contents of K ₁₁・GD(t-
j) is transferred to latch 404. (9) Next, in order to calculate K ₁₂ · GD (t-j-1) + [R1], ADR [K _o ]; ADR [K ₁₂ ] SL1; SELECT (B) CTL; (Y) = Signals SL1 and CTL with contents shown in (A)・(X)+(B) are used as operation code OPC and address information.
ADR [K _o ] is output from the control signal output register 303. As a result, the coefficients are stored in the coefficient memory 400.
_K12 is read and input to the calculation circuit 402 (A)
is supplied to Also, the selector 401 selects the musical tone data GD(t) latched in the latch 191.
-j-1) is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result _{, the} calculation circuit 402 calculates the calculation value (Y ) is output. This calculated value (Y) is then stored in register R1 and
Stored in R2. As a result, the contents of registers R1 and R2 are as follows: [R1]=[R2]= _K12.GD (t-j-1)+ _K11.GD (t-j). (10) Next, the contents of register R2, coefficient K ₁₃ , memory
K ₁₃・GD(t
In order to calculate −j−1)+[R2], first,
In order to transfer the contents of register R2 to latch 404, the contents of register R2 are transferred to latch ₄₀₄ in the same _way as in step b-(8) above.
GD(t-j) is transferred to latch 404. (11) Next, read out the coefficient K ₁₃ and calculate K ₁₃・GD(t−j
−1) + [R2], the above b−
In the same way as step (9), ADR [K _o ]; ADR [K ₁₃ ] SL1; SELECT (B) CTL; signal SL1 with the content shown as (Y) = (A)・(X) + (B) ，CTL as operation code OPC and address information
ADR [K _o ] is output from the control signal output register 303. As a result, the coefficients are stored in the coefficient memory 400.
_K13 is read and the calculation input (A) of the calculation circuit 402
is supplied to Also, the selector 401 selects the musical tone data GD(t) latched in the latch 191.
-j-1) is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result, the arithmetic circuit 402 calculates (Y)=(A)・(X)+(B) =K ₁₃・GD (t-j-1) +K ₁₂・GD (t-j-1) +K ₁₁・GD( The calculated value (Y) of t-j) is output. This calculated value (Y) is then stored in the register R2 in the next step, and is supplied to the high pass filter HPF via this register R2. ( ₁₂ ) In the final step in the low-pass filter LPF, the contents of register R1 are written to memory SD0 and used at the next sampling time (t+1).
(t-j-1)+K ₁₁・SPD(t-j)'' is transferred to the latch 404 in the same way as in step b-(8) above, and then the arithmetic circuit 402 calculates (Y)=(B). The calculation value “(Y)=K ₁₂・
GD(t-j-1)+K ₁₁ ·GD(t-j)'' is written to the memory SD0. This write operation is executed by the operation code OPC as shown in DL _o ; DL ₀ DL _k ; DL _SD GP2; “1” WR4; “1” (WRITE)
This is done by outputting the memory number information DL _o from the control signal output register 303. When the operation of the low-pass filter LPF is completed, the operation of the high-pass filter HPF is performed next, but a description of the operation of this high-pass filter HPF will be omitted. Next, the operation of forming the reverberant sound RVD ¹ with coarse delay time intervals will be explained. c Formation operation of reverberant sound RVD ¹ (1) First, register R4 of high-pass filter HPF
Multiply the stored data GD(t-j) by the coefficient _K17 , and register the multiplied value _K17・GD(t-j).
In order to store it in R5, the latch control signal L1 with the contents indicated by RG _o ; R4 L1 ; “1” (LATCH) and the register number information RG _o are sent to the control signal output register 3.
03 and the contents of register R4 GD(t
-j) is transferred to latch 404. (2) Next, to calculate K ₁₇・GD(t−j), ADR [K _o ]; ADR [K ₁₇ ] SL1; SELECT(C) CTL; (Y)=(A)・(X) Select control signal SL1, calculation control signal CTL, and address information for reading coefficients as shown
ADR [K _o ] is output from the control signal output register 303. As a result, the coefficient K ₁₇ is extracted from the coefficient memory 400.
is read out and supplied to the calculation input (A) of the calculation circuit 402. In addition, the selector 401 is connected to the latch 40.
The data GD (t-j) latched at 4 is selected and supplied to the arithmetic input (X) of the arithmetic circuit 402. As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)·(X)=K ₁₇ ·GD(t−j). This calculated value (Y)
is stored in register R5 in the next step. (3) Next, from memory D1 of data memory 190
x Read the musical tone data GD (t-x1) from ₁ hour ago,
This data GD (t-x ₁ ) is added to the current value of register R11, and the added value is added to register R11 again.
In order to store the data, first, the latch control signals L3 and L2 with the contents shown as DL _o ; DL ₁ DL _k ; DL _D L3; "1" (LATCH) L2; "1" (LATCH),
Memory number information DL _o and memory type information DL _k
is output from the control signal output register 303. As a result, the output information ADR[D1] of the address counter AC(D1) corresponding to the memory D1 is latched in the latch 306 as lower address information for reading out the musical tone data GD(t-x ₁ ). And this lower address information ADR [D1]
The address information output circuit 309 outputs memory number information DL _o and memory type information above it.
DL _k is added and output to the data memory 190 as address information DM/ADR of the memory D1. As a result, the musical tone data GD (t-x ₁ ) x ₁ hours ago is read from the memory D1,
It is latched by latch 191. (4) Next, in order to add this read data GD (t-x1) and the current value of register R11, the contents of register R11 are transferred to latch 404, and then SL ₁ ;SELECT(B) CTL;( The select control signal SL1 and calculation control signal CTL with the contents shown by Y) = (X) + (B) are output to the control signal output register 3.
Output from 03. Then, the selector 401 selects the tone data GD (t-x ₁ ) latched in the latch 191 and supplies it to the calculation input (X) of the calculation circuit 402 . As a result, the arithmetic circuit 402 outputs the arithmetic value (Y) expressed as (Y)=(X)+(B)=[R11]+GD(t- _x1 ). In this case, the contents of the register R11 are cleared at the stage when the operation at the previous sampling time (t-1) is completed. Therefore, this step (4)
The calculated value (Y) in is GD(t-x ₁ ).
Thereafter, the calculated value (Y) is transferred to and stored in register R11. (5) Next, musical tone data GD (t-x ₁ ) from memory D1
is read out, multiplied by the coefficient _K18 , and the added value of the multiplied value _K18・GD(t-x ₁ ) and the contents of register R5 "_K17・GD(t-j)" is stored in register R6. In order to memorize it again, first perform the above c-
Similarly to step (1), the contents of register R5 " _K17.GD (t-j)" are transferred to latch 404. (6) Next, the musical tone data GD(t-x ₁ ) latched in the latch 191, the data "_K17・GD(t-j)" latched in the latch 404, and the coefficient
In order to perform the calculation (Y)=K ₁₈・GD(t-x ₁ ) +K ₁₇・GD(t-j) using K 18, ADR[K _o ]; ADR[K ₁₈ ] SL1; SELECT( _B ) STL; Select control signal SL1, arithmetic control signal CTL, and address information for reading coefficients as shown by (Y)=(A)・(X)+(B)
ADR [K _o ] is output from the control signal register 303. As a result, the coefficient K ₁₈ is extracted from the coefficient memory 400.
is read out and supplied to the calculation input (A) of the calculation circuit 402. In addition, the selector 401 is connected to the latch 19.
Musical tone data GD latched at 1 (t-x ₁ )
is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result, the arithmetic circuit 402 outputs (Y)=(A)*(X)+(B)= _K18 *GD(t- _x1 )+ _K17 *GD(t-j). In the next step, this calculated value (Y) is written to the address corresponding to the current time t in the memory D1 via the register R6. After this, register R6 is cleared in order to process the system in memory D2. (7) Next, processing regarding each system of memories D2 to D9 is performed in the same manner as steps c-(3) to c-(6) described above. When the processing of each system of the memories D1 to D9 is completed, information regarding the reverberant sound RVD ¹ expressed as RVD ¹ (t)= ₁₀ 〓 ⁿ⁼¹ GD (t−x _o ) is obtained in the register R11. Next, the operation of forming reverberant sound RVD ² with dense delay time intervals will be explained. d Formation operation of reverberant sound RVD ² (1) First, in order to read the reverberant sound data RVD ¹ (t-y ₁ ) from memory MD0 y ₁ hour ago, DL _o ; DL ₀ DL _k ; DL _MD L3; 1” (LATCH) L2; Latch control signals L3 and L1 with the content indicated by “1” (LATCH),
Memory number information DL _o and memory type information DL _k
is output from the control signal output register 303. As a result, address information output circuit 309
In step c-(3) above, address information DM/ADR for memory MD0 is obtained.
is formed, and data RVD ¹ (t-y ₁ ) of y ₁ hours ago is read from memory MD0. This data RVD ¹ (ty ₁ ) is then latched in latch 191. (2) Next, the data latched in latch 191
RVD ¹ (t-y ₁ ), output data of register R11
In order to calculate K ³⁰ · RVD ¹ (t-y ₁ ) + RVD ¹ (t) using the RVD 1 (t) coefficient _{K 30} and store the calculated value in register R12, first, the output data of register R11 is
After RVD ¹ (t) is transferred to latch 404, ADR [K _o ]; ADR [K ₃₀ ] SL1; SELECT (B) STL; (Y) = (A)・(X) + (B) The select control signal SL1 containing the contents to be input, the calculation control signal CTL, and the address information ADR [K _o ] for reading coefficients are output to the control signal output register 30.
Output from 3. As a result, the arithmetic circuit 402 has the above-mentioned c-
In the same way as step (6), the coefficient K ₃₀ is input to the calculation.
(A), and data RVD ¹ (ty ₁ ) is supplied to the calculation input (X). As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)·(X)+(B)=K ₃₀ ·RVD ¹ (t−y ₁ )+RVD ¹ (t). This calculated value (Y) is then transferred to register R12 in the next step.
is memorized. (3) Next, the contents of register R12 “K ₃₀・RVD ¹ (t
-y ₁ ) + RVD ¹ (t)'' by the coefficient K ₂₉ , first the contents of register R12 are transferred to latch 404, and then ADR [K _o ]; ADR [K ₂₉ ] SL1; SELECT (C) CTL; (Y)=(A)・(X) The select control signal SL1, calculation control signal CTL, and address information ADR [K _o ] for reading coefficients are sent to the control signal output register 303.
is output from. As a result, the coefficient K ₂₉ is supplied to the calculation input (A) of the calculation circuit 402, and the data “K ₃₀・
RVD ¹ (t-y ₁ ) + RVD ¹ (t)” is the calculation input (X)
is supplied to As a result, the calculation circuit 402 outputs the calculation value (Y) shown as (Y)=(A)・(X)=K ₂₉・{K ₃₀・RVD ¹ (t−y ₁ ) +RVD ¹ (t)} do. This calculated value (Y) is stored in register R13 in the next step.
is memorized. (4) Next, add the contents of register R13 and the data y ₁ hour ago RVD ¹ (t-y ₁ ) (latched in latch 191 in step d-(1) above), and In order to store the added value in register R13 again, the contents of register R13 are changed to ``K ₂₉ · {K ₃₀ · RVD ¹ (t-
y ₁ ) + RVD ¹ (t)} is transferred to the latch 404, the select control signal SL1 with the content shown as SL1; SELECT (B) CTL; (Y) = (B) + (X), calculation control Signal CTL is the control signal output register 303
is output from. As a result, the arithmetic circuit 402
The calculated value (Y) is (Y) = (B) + (X) = RVD ¹ (t-y ₁ ) +K ₂₉ {K ₃₀ · RVD ¹ (t-y ₁ ) + RVD ¹ (t)} Output. This calculated value (Y) is stored in register R13 in the next step.
and output as reverberant sound information RVD ^2A . (5) Next, the contents of register R12 “K ₃₀・RVD ¹ (t
−y ₁ )+RVD ¹ (t)” at the sampling time (t+y ₁ ) delayed by y ₁ hour, the register
The contents of R12 are written to the address corresponding to the current time t in memory MD0. (6) After this, the reverberation sound is denser than the y ₁ hour interval.
RVD ^2B and RVD ^2C are formed in the same manner. In the embodiment shown in FIG. 5 (FIG. 6), a band pass filter BPF is provided, but this may be omitted if necessary. In addition, as shown in the functional block diagram of Fig. 7, the output data of the memory D10 is filtered by a high pass filter HPF, a band pass filter BPF, and a low pass filter LPF.
The first reverberant sound forming unit 20 divides into a series of frequency bands.
00, different reverberation sounds may be formed for each frequency band. This can be easily achieved by simply changing the contents of the control program. In this way, the reverberation sound adding device of this embodiment utilizes digital memory as a delay element, so even if the reverberation time is increased, the S/N ratio remains low.
It is possible to generate reverberant sound with the same quality as natural reverberant sound without reducing the ratio. Another advantage is that the reverberation time can be freely changed by changing the address interval of the digital memory. Furthermore, as shown in FIG. 18, one sampling period T ₀ is divided into two time periods T _0A and T 0B, and the first sequence of reverberant sounds from the 1st step to the 96th step of the control program in the time period T _0A are divided into two time periods T 0A and T _0B . If steps 97 to 192 of the control program in time period _T0B are used to form a second series of reverberant sound, one reverberant sound adding device can generate two series. The reverberation sound can be generated in a time-division manner, and the configuration can be simplified. In this case, the first series of musical tone data GD ₁ (ΣGD _U , ΣGD _A ) and the second series of musical tone data GD ₂ (ΣGD _LP , ΣGD _B ) are
As shown in Figure a, each series of musical tone data GD ₁ ,
Latches 17A and 17B provided corresponding to GD ₂
The latched musical tone data GD ₁ ,
One of the GD ₂ is time-divisionally selected by the selector 17C using the select control signal SL5 output from the control signal output register 303. on the other hand,
Two series of time-divisionally formed reverberant sound data (ECH
(t), RVD ^2C ), as shown in FIG. 19b, the select control signal is
It is divided into two series by SL6, and the reverberant sound data of each series is latched by latch control signals L7 and L8 in latches 17E and 17F, respectively, and the latched data is output as the reverberant sound data of each series. Note that the musical tone signal generation circuits 6, 6A, and 6B form musical tone signals for each sound generation channel at a high sampling frequency, but the reverberation sound adding devices 9,
10, it is not necessary to form the reverberation sound at the same sampling frequency as the formation of musical sound data GD, GD _A , and GD _B. For example, when forming musical sound data at a sampling frequency of 50KHz, the reverberation sound is formed at 25KHz. A sampling frequency of about 100% is sufficient. Therefore, as shown in FIG. 20, a sampling rate conversion circuit 18 is provided between the musical tone data accumulators 8, 16A, 16B and the reverberation sound adding devices 9, 10, and the synthesized musical tone data ΣGD _U (ΣGD _LP , ΣGD _A ,
The sampling rate of ΣGD _B ) may be lowered. i.e. 50KHz timing signal
T ₁ (Fig. 3 d) is divided by 1/2 by the frequency dividing circuit 18A to obtain a 25KHz sampling pulse T _S , and the musical tone data ΣGD _U (ΣGD _LP , ΣGD _LP ,
ΣGD _A , ΣGD _B ) are sampled and held by the latch 18C, and the sampled and held outputs are supplied to the reverberation sound adding devices 9 and 10. By doing so, it is possible to reduce the memory capacity when forming reverberant sound in the reverberant sound adding devices 9 and 10. In addition, the digital filter 18
B is for removing aliasing noise components when converting the sampling rate, and may be unnecessary depending on the frequency band of the musical tone signal. By the way, when adding reverberant sounds of multiple channels with different characteristics, if a dedicated reverberant sound forming circuit or parameters for reverberant sound forming are prepared for each channel, the scale will increase. Therefore, if the circuits or parameters common to the reverberant sound of each channel are shared by each channel, a small-scale configuration can be achieved. As explained above, the electronic musical instrument according to the present invention provides a plurality of reverberation sound addition channels corresponding to each of the plurality of pitch specifying means or musical tone signal generation devices, and arbitrarily sets the reverberation characteristics of each reverberation sound addition channel. This makes it possible to add a different reverberation sound to each pitch specifying means or to each series of musical tone signal generators, thereby further enhancing the performance effect. Further, the reverberation sound addition channel includes a reverberation characteristic indicating means for selectively instructing the reverberant characteristic of the reverberant sound from among a plurality of reverberation characteristics, and a reverberant sound corresponding to each of the reverberation characteristics that can be specified by the reverberation characteristic indicating means. a control program memory that stores a plurality of control programs and outputs a control program corresponding to the instructed reverberation characteristics; a parameter generation means that outputs parameters related to each of the instructed reverberation characteristics according to the control program; a control means for outputting a memory control signal for controlling writing/reading and addressing of the memory according to the control program and an arithmetic control signal for controlling the arithmetic operation; It consists of a calculation means that performs a predetermined calculation corresponding to the instructed reverberation characteristic, and a memory that has a plurality of addresses and writes and reads the output of the calculation means in accordance with the memory control signal, and the combination of these two and a reverberant sound forming means that adds reverberation characteristics instructed by the instruction means to the input digital musical tone signal and outputs the resultant signal.Since it has a digital structure, it has a simple structure and a good S/N ratio. , and reverberant sound whose reverberation characteristics can be easily changed can be added.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the musical tone data accumulator in FIG. 1, and FIG.
The figure is a time chart to explain its operation,
FIG. 4 is a block diagram showing another embodiment of the electronic musical instrument according to the present invention, FIG. 5 is a block diagram showing an embodiment of the reverberation sound adding device used in the present invention, and FIG. 6 is an embodiment of the electronic musical instrument shown in FIG. 7 and 8 are block diagrams showing the basic configuration of the delay circuit. FIG. 9 is a time chart for explaining the operation of the delay circuit in FIG. 10
11 is a diagram showing the frequency characteristics of a delay circuit having a comb filter configuration, and FIGS.
3 is a characteristic diagram of the reverberation sound generated in the embodiment of FIG. 5, FIG. 14 is a diagram showing the structure of the data memory in the embodiment of FIG. 5, and FIG. 15 is a diagram showing the delay in the embodiment of FIG. 5. 16 is a diagram showing the structure of the address counter in the embodiment of FIG. 5, FIG. 17 is a functional block diagram showing another embodiment of the reverberation sound adding device according to the present invention, Figure 18 is a diagram showing time divisions when using the reverberation sound adding device in a time-division manner;
The figure shows a configuration example of an input circuit section and an output circuit section in that case, and FIG. 20 is a diagram showing an example of a sampling rate conversion circuit. 1... Upper keyboard, 2... Lower keyboard, 3... Pedal keyboard, 6, 6A, 6B... Musical tone signal generation circuit, 8,
16A, 16B...musical sound data accumulator,
9, 10... Reverberant sound adding device, 1000... Early reflected sound forming unit, 2000... First reverberant sound forming unit,
3000...Second reverberation sound forming section, BPF...Band pass filter, 19...Storage section, 20...Time information generation section, 30...Address information generation section, 40
...Calculation section.

Claims (1)

[Scope of Claims] 1. A plurality of pitch specifying means; a musical tone generating means for generating a plurality of series of digital musical tone signals corresponding to the pitches respectively specified by the respective pitch specifying means; It is equipped with a plurality of digital reverberation sound addition channels that add and output reverberation sound with different characteristics for each series to musical sound signals, and the digital reverberation sound addition channel selectively selects the reverberation characteristics of the reverberation sound from among the plurality. a reverberant sound instructing means for instructing the reverberant sound, and a plurality of control programs for forming reverberant sounds corresponding to each of the reverberation characteristics that can be instructed by the reverberant sound instructing means, and a control program memory that outputs a control program corresponding to a reverberation characteristic; a reverberation sound forming means including a calculation means and a data memory having a plurality of addresses; and a delay time corresponding to the reverberation characteristic instructed by the reverberation characteristic instruction means. and a parameter generating means for generating parameters related to the control program memory and parameters related to the calculation coefficient according to the output of the control program memory, and for writing, reading, and addressing in the data memory based on the output of the control program memory and the parameters related to the delay time. and a control means for outputting a memory control signal for the arithmetic operation means, and a control means for outputting an arithmetic control signal for the arithmetic means based on the output of the control program memory. By performing a predetermined calculation on the signal read from the memory, the calculation coefficient, and the digital musical tone signal, the reverberation characteristic instructed by the reverberation characteristic instruction means is added to the digital musical tone signal and outputted. An electronic musical instrument characterized by: