JPS648865B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a central processing unit and a main storage device connected to a plurality of input/output devices through a channel device having a bus conversion device, and a plurality of input/output devices connected to the bus conversion device. In a data processing system that uses an asynchronous bus (second bus) to transfer data between devices, a latch means is provided in the bus conversion device to latch data on the asynchronous bus at all times, and the input/output device The present invention relates to a data transfer processing method in which, when data transfer from a computer is started, latching is prohibited, latch output is fixed, and data transfer processing is performed.

[Conventional technology and problems]

FIG. 1 is a diagram showing the configuration of a data processing system. In FIG. 1, 1 is a central processing unit, 2 is a main storage device, 3 is a channel device, and 4-0 to 4
-n indicates an input/output device, BC indicates a bus conversion device, and Buff indicates a data buffer.

In FIG. 1, data transfer between the channel device 3 and the main storage device 2 is performed using the first bus, and data transfer between the channel device 3 and the plurality of input/output devices 4-0 to 4-n is performed. Data transfer is performed using the second bus. Bus conversion device in channel device 3
BC is a data buffer that is connected to the above two buses and can store a certain amount of data transferred from each input/output device 4-0 to 4-n.
Has a buff. Declare that the second bus is an asynchronous bus and is transferring data
It consists of an SRVI signal line (service-in signal line), a bus signal line (address signal line) necessary for data transfer that is established before or at the same time as the SRVI signal is established (rising edge), etc. A synchronized bus conversion device BC having such an asynchronous bus synchronizes the SRVI signal. In this bus conversion device BC, upon confirmation of the synchronized SRVI signal, data transfer processing between the plurality of input/output devices 4-0 to 4-3 is started. At this time, if the signals on the bus signal line necessary for data transfer are directly used, the bus disturbance directly affects the inside of the bus converter BC. Therefore, these signals may be latched within the bus conversion device BC at the start of the data transfer process so that they do not change during the data transfer process. However, in this method, the bus signal line signal is latched when it is confirmed that the data transfer process has started, so the data transfer process is slower than when the bus signal line signal is used directly without latching it. There's a problem.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
The object of the present invention is to provide a data transfer processing method that does not slow down data transfer processing even when a latch circuit is used.

[Structure of the invention]

To this end, the data transfer processing method of the present invention includes a central processing unit, a main storage device, a channel device having a bus conversion device, a plurality of input/output devices, and a communication system between the main storage device and the bus conversion device. A first bus used for data transfer, and a second bus used for data transfer between the bus conversion device and the plurality of input/output devices, and the second bus is used. When data is transferred between the bus conversion device and the plurality of input/output devices, the signal SRVI, which declares that the bus conversion device is transferring data, is synchronized, and the signal SRVI is confirmed. In a data processing system that uses latch means to perform data transfer processing and send out a response signal SRVO, the above bus converter is capable of synchronizing multiple clocks connected in series to which the signal SRVI is input. flip flop 6, 7, 8
and latch means 10, and clock supply means 9, 11, 12, 14 for controlling the supply of latch clocks to the latch means 10.
and a response means 15 for sending out a response signal SRVO, the clock supply means 9, 11, 12, 14
The latch means 1 is activated on the condition that the states of the plurality of flip-flops 6, 7, and 8 reach predetermined states.
The present invention is characterized in that the supply of the latch clock to 0 is prohibited, and the prohibition is canceled on condition that the response signal SRVO is output from the response means 15.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a circuit configuration of one embodiment of the present invention,
FIG. 3 is a time chart explaining the operation of the circuit shown in FIG.

In Figure 2, 5 is a receiver, 6 to 8 are D-FF, 9 is JK-FF, 10 is a latch circuit, 1
1 to 13 are AND gates, 14 is a NOR gate, and 15 is an SRVO generation circuit. The SRVI signal is supplied to the input terminal D of the D-FF 6 through the receiver 5, and the bus signal is supplied to the input terminal of the latch circuit 10. The output terminal Q of D-FF6 is D-FF
7 and the input terminal of AND gate 11. The output terminal Q of D-FF7 is D-FF
The other input terminal of AND gate 11 connected to the input terminal D of JK-FF8 and the input terminal of AND gate 11 is connected to the output terminal of D-FF8, and the output terminal of AND gate 11 is connected to the input terminal of JK-FF9. J and the input terminal of NOR gate 14. The other input terminal of NOR gate 14 is connected to output terminal Q of JK-FF9. One input terminal of AND gate 12 is supplied with a clock signal, the other input terminal is connected to the output terminal of NOR gate 14, and the output terminal of AND gate 12 is connected to the latch clock terminal of latch circuit 10. Connected. The latch circuit 10 has its input terminal supplied with a bus signal, and latches the bus signal according to the output signal of the AND gate 12. The SRVO creation circuit 15 operates when the signal at the output terminal Q of JK-FF9 is high.
The SRVO signal is set to high level 2τ after reaching the level, and when the signal at the output terminal Q of D-FF6 becomes low level, the SRVO signal is set to low level. The SRVO signal is supplied to the input terminal K of the JK-FF 9 and is sent to the second bus through the AND gate 13. The circuit shown in FIG. 2 constructed as described above is provided in a bus control device, and FIG. 3 shows its operating time chart.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to the time chart shown in FIG. SRVI
While the signal is at a low level, the output terminals Q of D-FFs 6 to 8 and JK-FF9 are at a low level. Therefore, the output terminal of NOR gate 14 goes high and the other input terminal of AND gate 12 goes high, so that the clock signal passes through AND gate 12 to the latch clock terminal of latch circuit 10. is supplied to The bus signal is then latched into latch circuit 10 by the clock signal. When the SRVI signal on the asynchronous bus goes high, the next clock signal C
1, D-FF6 is set, and the next clock signal C2 sets D-FF7. At this time, since the output of D-FF8 is at a high level, the AND condition of AND gate 11 is satisfied, and JK-FF9 is set by the third clock signal C3.
Output terminal of AND gate 11 or JK-FF9
While the output terminal Q of the NOR gate 14 is at a high level, the output terminal of the NOR gate 14 is at a low level.
The clock signal to latch circuit 10 is inhibited by AND gate 12. Therefore, the latch circuit 10
is fixed at the contents of the bus signal latched by the second clock signal C2. The SRVO generation circuit 15 sets the SRVO signal to high level when 2τ has elapsed since JK-FF9 was set. Therefore, JK-FF9 is reset by the next clock signal C6. Also, when the SRVO signal is sent to the asynchronous bus, the SRVI signal is set to low level, and the subsequent clock signals C7, C8, and C9 cause D-FF6,
7 and 8 are reset. When JK-FF9 is reset and then D-FF6 is reset, the output terminal of NOR gate 14 is brought to a high level again, and AND gate 1 is set to high level after clock signal C7.
It is again supplied to the latch circuit 10 through 2. When the SRVI signal is set to a low level and the D-FF6 is reset by the clock C7, the SRVO generation circuit 15 sets the SRVO signal to a low level on the condition that the D-FF6 is reset.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a latch clock is constantly supplied to the latch circuit for the signal on the bus signal line to latch the signal, and data transfer from the input/output device is started. By inhibiting the latch clock, the contents of the latch circuit are fixed, eliminating delays in processing speed caused by the provision of the latch circuit, and allowing data transfer processing to be performed without being affected by bus signal disturbances. It can be carried out.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of a data processing system;
FIG. 2 is a diagram showing the circuit configuration of one embodiment of the present invention, and FIG. 3 is a time chart illustrating the operation of the circuit shown in FIG. 1...Central processing unit (CPU), 2...Main storage device, 3...Channel device, 4-0 to 4-n...
...I/O device, 5...Receiver, 6 to 8...
D-FF, 9...JK-FF, 10...Latch circuit,
11 to 13...AND gate, 14...Noah gate, 15...SRVO creation circuit, BC...
Bus converter.

Claims (1)

[Claims] 1. A central processing unit, a main storage device, a channel device having a bus conversion device, a plurality of input/output devices, and a device used for data transfer between the main storage device and the bus conversion device. and a second bus used for data transfer between the bus conversion device and the plurality of input/output devices, and the second bus is used to perform the bus conversion. When data is transferred between the device and the plurality of input/output devices mentioned above, the signal SRVI that declares that data transfer is being performed by the above bus conversion device is synchronized, and the signal SRVI
In a data processing system that uses latch means to perform data transfer processing and send out a response signal SRVO due to the determination of Synchronous flip-flops 6, 7, 8
and latch means 10, and clock supply means 9, 11, 12, 14 for controlling the supply of latch clocks to the latch means 10.
and a response means 15 for sending out a response signal SRVO, the clock supply means 9, 11, 12, 14
The latch means 1 is activated on the condition that the states of the plurality of flip-flops 6, 7, and 8 reach predetermined states.
1. A data transfer processing system characterized in that the supply of a latch clock to 0 is prohibited, and the prohibition is canceled on condition that a response signal SRVO is output from a response means 15.