JPS648922B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a muting circuit.

The present invention was made in order to provide a muting circuit that can obtain a large amount of signal attenuation and operate over a wide power supply voltage range.

In the present invention, an attenuator-type muting circuit made up of a voltage divider circuit of a fixed resistor and a transistor is connected in series at the rear stage of a switch-type muting circuit that utilizes the switching operation of a differential transistor circuit. This is intended to compensate for mute operation in a low power supply voltage region where the circuit cannot operate normally.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 1 denotes a signal source circuit, which is, for example, an electronic switch circuit for switching between a recording signal REC and a reproduction signal PLY in a tape recording device.

A switch-type muting circuit 2 that utilizes the switching operation of a differential transistor circuit is provided as a muting circuit to prevent the switching sound that occurs when switching between recording and playback of this switch circuit. An attenuator-type muting circuit 3 composed of a fixed resistor and a transistor is provided via a coupling capacitor C to obtain an output OUT.

Reference numeral 4 denotes a bias circuit, which forms a bias voltage V _B for the differential transistor circuit constituting the mutating circuit 2.

5 detects the rise/fall of the power supply voltage V _CC and outputs the control signal V _C2 of the mutating circuit 3.
This is a control circuit that forms a

The mutating circuit 2 using the above-mentioned differential transistor circuit turns on/off signal transmission by its switching operation, for example, by switching the emitter constant current source of the differential transistor as described later. A large attenuation of 80dB can be obtained as a monolithic IC.
It has the advantage of being easy to convert.

However, since a differential transistor circuit is used, the lower limit voltage for operation becomes large, and a mute operation cannot be performed in a low power supply voltage region.

Moreover, as the bias voltage V _B requires a high power supply ripple rejection rate, a stabilizing power supply circuit using a large capacity capacitor and a Zener diode is used, so mute operation cannot be performed immediately after power is turned on. There is a drawback that there is no Therefore, it is not possible to eliminate the pop sound (shock sound) when the power is turned on and off.

Therefore, in order to compensate for the drawbacks of the muting circuit 2, an attenuator-type muting circuit 3 is provided downstream of the muting circuit 2 via a coupling capacitor C.

This muting circuit 3 includes a fixed resistor connected in series with a signal line, a transistor between the output side of this resistor and a reference potential terminal, and a signal generated by using the on-resistance r _CS of this transistor and the fixed resistor. The mute operation is performed by dividing the voltage.

This muting circuit 3 operates at a voltage lower than the threshold voltage V _BE of the transistor. Therefore, the control circuit 5 detects the power supply voltage V _CC and turns on the transistor of the mutating circuit 3 for a certain period of time when the power is turned on or cut off, so that the mutating circuit 2 is turned on.
It is possible to reliably eliminate the clicking sound when the power is turned on and off, which cannot be erased with other devices.

That is, in this embodiment, the muting operation under the stable power supply voltage V _CC is mainly performed by the muting circuit 2, and the muting circuit 2 performs the muting operation when the power is turned on and off, which cannot be erased, and when the power supply voltage is low. The muting operation in this area is performed by the muting circuit 3.

This makes it possible to obtain a muting circuit that can operate over a wide power supply voltage range.

Note that in the attenuator-type muting circuit 3, the value of the fixed resistor provided in series with the signal line cannot be increased, so a large amount of attenuation cannot be obtained.
This circuit alone is insufficient in terms of miute attenuation.

FIGS. 2 and 3 are specific circuit diagrams showing one embodiment of the switch-type muting circuit 2, respectively.

In the embodiment circuit shown in FIG. 2, the outputs of the differential pair transistors Q ₁ , Q ₂ and Q ₃ , Q ₄ are made common, and by switching the constant current sources provided at the common emitters of the respective transistors, one of the outputs can be switched. differential pair of transistors Q ₁ ,
This is to obtain the output of Q ₂ or Q ₃ or Q ₄ .

That is, the input signal V _IN is applied to the base of transistor Q ₁ , and the bias voltage is applied through resistor R ₂ .
V _B is applied, and the output is negatively fed back to the base of the transistor Q ₂ forming a differential pair with the transistor Q ₁ to form a voltage follower circuit.

Similarly, bias voltage V _B is applied to the base of transistor Q ₄ , and the output is negatively fed back to the base of transistor Q ₃ forming a differential pair with transistor Q ₄ to form a voltage follower circuit.

Then, the differential pair transistors Q ₁ , Q ₂ and
Transistors Q ₅ and Q ₆ that constitute the constant current source circuit provided at the common emitter of Q ₃ and Q ₄ are diodes (including diode-connected transistors).
A current mirror circuit is formed with Q ₇ and Q ₈ , and the input current to this current mirror circuit is passed through a differential transistor.
The constant current I ₀ is switched and supplied by Q ₉ and Q ₁₀ .

The above current switching is performed using the mute signal V _C1 . When this mute signal V _C1 is set to a low level with respect to the bias voltage V _B , transistor Q ₉ is turned on and transistor Q ₁₀ is turned off, resulting in a constant current.
I ₀ flows into current mirror circuits Q ₇ and Q ₅ , differential transistors Q ₁ and Q ₂ operate, and input signal V _IN is directly transmitted to the collector of transistor Q ₁₂ as an output.

On the other hand, when the mute signal V _C1 is set to high level, transistor Q ₉ is turned off, transistor Q ₁₀ is turned on, and constant current I ₀ flows to current mirror circuits Q ₈ and Q ₆ .
Differential transistors Q ₃ and Q ₄ operate, and bias voltage V _B is output to the collector of transistor Q ₁₂ to mute the input signal V _IN .

The embodiment circuit shown in FIG. 3 has a transistor Q ₁₇ to which an input signal V _IN is applied to the common emitter of the differential pair transistors Q ₁₃ and Q ₁₄ , and causes the differential transistors Q ₁₃ and Q ₁₄ to perform a switching operation. This is used to perform a miute motion. In order to prevent changes in the DC level in this case, the switching outputs of the differential transistors Q ₁₅ and Q ₁₆ , which are provided with a constant current transistor Q ₁₈ that forms a DC current at their common emitter, are reverse-phased to the differential transistors Q ₁₃ and _Q14
is added to the output of

In other words, the mute signal V _C1 is
_A bias voltage V _B is applied to the bases of transistors Q ₁₄ and Q ₁₅ , and the collectors of transistors Q _{13 and Q 15 and} Q ₁₄ and Q ₁₆ are common. , Q ₁₅ , and a load resistor R ₃ is provided at the collector to obtain the output.

Then, the constant voltage formed by resistor R ₃ and diode Q ₁₉ is applied to the above transistor through resistors R ₄ and R ₅ .
A bias voltage is applied to the bases of Q ₁₈ and Q ₁₇ to form a direct current.

The operation of this circuit is that when the mute signal V _C1 is set to a high level with respect to the bias voltage V _B , transistors Q ₁₃ and Q ₁₆ are turned on, and transistors Q ₁₄ and Q ₁₅ are turned on.
turns off. Therefore, a signal output superimposed on the DC current that is the collector output of transistor _Q17 is obtained. On the other hand, when the mute signal V _C1 is set to low level, transistors Q ₁₃ and Q ₁₆ are turned off,
Transistors Q ₁₄ and Q ₁₅ are turned on. Therefore, only the direct current generated by transistor _Q18 can be obtained.

Above transistors Q ₁₇ , Q ₁₈ and emitter resistance
By using the same R ₆ and R ₇ , the above DC current becomes equal, and the DC output does not change due to mute on/off.

FIGS. 4 and 5 are specific circuit diagrams showing one embodiment of the attenuator-type muting circuit 3, respectively.

The embodiment circuit shown in FIG. 4 is a muting circuit composed of a fixed resistor _R9 and a transistor _Q20 . In this circuit, if the base of transistor Q ₂₀ is grounded with low impedance, the base,
There is a drawback that the collector junction is forward biased at a negative signal level, and a leakage current with large distortion due to its nonlinear characteristics flows into the signal line or clamps the negative level.

In addition, when configured with monolithic IC,
Since a pn junction is formed between the collector and the substrate, a leak current with large distortion similar to the above will flow or be clamped due to a negative signal level.

Therefore, as shown in the embodiment circuit of FIG. 5, by using a mute transistor Q ₂₀ ' whose collector and emitter are reversely connected, the parasitic diode between the signal line and the ground is prevented.

Furthermore, a mute signal V _C2 is applied to the base of the transistor Q ₂₀ ′ via a lateral pnp transistor Q ₂₁ whose base is biased by the forward voltage of the diode Q ₂₂ .

In this case, if the mute signal is 2V _BE or less, transistor Q ₂₁ will be turned off, so the transistor
Since the base of Q ₂₀ ' is turned off under high impedance in a floating state, the leakage current can be significantly reduced and distortion of the transmitted signal can be prevented from worsening.

The present invention is not limited to the embodiments described above, and the differential transistor circuit constituting the muting circuit 2 can be modified in various ways. For example, in the circuit of FIG. 2, crosstalk of signals is prevented through transistors that are turned off. For differential transistor
A diode for backflow prevention may be inserted in the emitters of _Q1 to _Q4 . Further, the method of switching the constant current source circuit can be modified in various ways.

The method for extracting the output signal, including the circuit shown in FIG. 3, can be modified in various ways.

Further, the signal source circuit 1 is not limited to the recording/playback switching circuit described above, but may be any circuit as long as it has the possibility of producing a shock sound. In other words, the muting circuit according to the present invention can obtain a large amount of attenuation and can be widely used as a circuit having a wide operating voltage range.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of a switch-type muting circuit showing an embodiment of the invention, and FIGS. 4 and 5 respectively. 2A and 2B are circuit diagrams of attenuator-type muting circuits showing one embodiment of the present invention, respectively. 1... Signal source circuit, 2, 3... Muting circuit, 4... Bias circuit, 5... Control circuit.

Claims (1)

[Claims] 1. A first muting circuit in the form of a switch that utilizes the switching operation of a differential transistor circuit, a fixed resistor connected in cascade after the muting circuit and provided in series with a signal line, and a fixed resistor connected in series with the signal line. an attenuator-type second muting circuit configured with a transistor provided between the output side of the resistor and a reference potential terminal, and the second muting circuit operates according to the operation of the first mutating circuit. A muting circuit characterized in that it operates below a lower limit voltage. 2. A muting circuit characterized in that the second muting circuit according to claim 1 performs mute-on operation only for a certain period of time when power is turned on and/or cut off. 3 Item 2 stated in claim 1 or 2
A muting circuit characterized in that a transistor constituting the muting circuit has a collector and an emitter connected in reverse. 4. The transistors constituting the second muting circuit according to claims 1 to 3 are:
Lateral type with a predetermined bias applied to the base
A muting circuit characterized in that it is controlled by a muting control signal via a PNP transistor.