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JPS649734B2 - - Google Patents
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JPS649734B2 - - Google Patents

Info

Publication number
JPS649734B2
JPS649734B2 JP56213989A JP21398981A JPS649734B2 JP S649734 B2 JPS649734 B2 JP S649734B2 JP 56213989 A JP56213989 A JP 56213989A JP 21398981 A JP21398981 A JP 21398981A JP S649734 B2 JPS649734 B2 JP S649734B2
Authority
JP
Japan
Prior art keywords
package
semiconductor chip
pads
wire
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56213989A
Other languages
Japanese (ja)
Other versions
JPS58114444A (en
Inventor
Hidehiko Akasaki
Takehisa Tsujimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56213989A priority Critical patent/JPS58114444A/en
Publication of JPS58114444A publication Critical patent/JPS58114444A/en
Publication of JPS649734B2 publication Critical patent/JPS649734B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明はセラミツクパツケージを有する半導体
装置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to improvements in semiconductor devices having ceramic packages.

(2) 技術の背景 半導体装置は通常第1図に示すように半導体チ
ツプをセラミツクパツケージ内に気密封止する構
成となつている。図において1a,1b,1cは
半導体チツプ、2a,2b,2cはベース部材2
1とふた部材22とが接着層を介して気密に固着
されたセラミツクパツケージ、3は一端がセラミ
ツクパツケージ2内に固着され、但端がセラミツ
クパツケージ外に引き出された複数個のリード片
(第1図aのみ図示、他は省略)、4は半導体チツ
プ1のボンデイングパツドとリード片3とを電気
的に接続するボンデイングワイヤである。
(2) Background of the Technology Semiconductor devices usually have a structure in which a semiconductor chip is hermetically sealed within a ceramic package, as shown in FIG. In the figure, 1a, 1b, and 1c are semiconductor chips, and 2a, 2b, and 2c are base members 2.
1 and the lid member 22 are airtightly bonded to each other via an adhesive layer, and 3 includes a plurality of lead pieces (the first (Only figure a is shown, the others are omitted), and 4 is a bonding wire that electrically connects the bonding pad of the semiconductor chip 1 and the lead piece 3.

このような半導体装置は、半導体チツプ1a,
1b,1cのサイズが異るとそれに適合する第1
図a,b,cに示すような各種形状のセラミツク
パツケージ2a,2b,2cが用いられている。
しかし最近の半導体チツプサイズの多様化に対処
するためにセラミツクパツケージを改良し、半導
体のチツプサイズが異つても搭載可能で高信頼性
なセラミツクパツケージの実現が要望されてい
る。
Such a semiconductor device includes semiconductor chips 1a,
If the sizes of 1b and 1c are different, the first
Ceramic packages 2a, 2b, and 2c of various shapes as shown in Figures a, b, and c are used.
However, in order to deal with the recent diversification of semiconductor chip sizes, there is a need to improve ceramic packages and create highly reliable ceramic packages that can be mounted even with different semiconductor chip sizes.

(3) 従来技術と問題点 従来のセラミツクパツケージ2a,2b,2c
では、チツプサイズの小さな半導体チツプ1aを
大きなセラミツクパツケージ2cに搭載するとボ
ンデイングワイヤ4の空間に張られる長さが長く
なり、ワイヤ間の接触やワイヤのたれ下りによる
シヨート事故が発生し易くなる欠点があつた。
(3) Conventional technology and problems Conventional ceramic packages 2a, 2b, 2c
Now, when a semiconductor chip 1a with a small chip size is mounted on a large ceramic package 2c, the length of the bonding wire 4 stretched in the space becomes long, which has the drawback that a shoot accident due to contact between the wires or the wire sagging is likely to occur. Ta.

(4) 発明の目的 本発明は上記従来の欠点を解消し、標準化され
た一種類のパツケージにより、多種類の半導体チ
ツプの搭載を可能とすることを目的とする。
(4) Purpose of the Invention It is an object of the present invention to eliminate the above-mentioned conventional drawbacks and to make it possible to mount many types of semiconductor chips using one type of standardized package.

(5) 考案の構成 そしてこの目的は、本発明によればパツケージ
内凹部に配置した半導体チツプ上の複数の電極を
前記パツケージ端部の対応する導電部材のパツド
にワイヤボンデイングして成る半導体装置におい
て、前記凹部内の中央部分に配設され前記半導体
チツプが固着されるダイアタツチ部と、前記ダイ
アタツチ部と前記パツケージ端部のパツドとの間
の前記凹部内に、前記パツケージ端部のパツドに
沿つて複数列状に複数個配列された補助パツドと
を有し、前記半導体チツプが前記複数列状に複数
個配列された補助パツドの内側の列状に複数個配
列された補助パツド上に配設でき、且つ前記半導
体チツプ上の複数の電極と前記パツケージ端部の
対応する導電部材のパツドとがそれぞれ外側の列
状に複数個配列された補助パツドを介してワイヤ
ボンデイングできるように構成されて成ることを
特徴とする半導体装置を提供することによつて達
成される。
(5) Structure of the Device According to the present invention, a semiconductor device is provided in which a plurality of electrodes on a semiconductor chip disposed in a recess in a package are wire-bonded to corresponding pads of a conductive member at an end of the package. , a die attach portion disposed in the center portion of the recess to which the semiconductor chip is fixed; and a die attach portion located in the recess between the die attach portion and the pad at the end of the package along the pad at the end of the package. and a plurality of auxiliary pads arranged in a plurality of rows, and the semiconductor chip can be disposed on the plurality of auxiliary pads arranged in a row inside the plurality of auxiliary pads arranged in a plurality of rows. , and the plurality of electrodes on the semiconductor chip and the corresponding pads of the conductive member at the end of the package are each configured to be wire bonded via a plurality of auxiliary pads arranged in an outer row. This is achieved by providing a semiconductor device characterized by the following.

(6) 発明の実施例 以下本発明の実施例を図面によつて詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明によるパツケージのベース部材
21と搭載した半導体チツプ1とを示す断面図で
あり、第3図はそのベース部材21の上面図であ
る。
FIG. 2 is a sectional view showing the base member 21 of the package according to the present invention and the mounted semiconductor chip 1, and FIG. 3 is a top view of the base member 21.

第2図は最大チツプサイズに適合する凹部21
1を有するパツケージのベース部材21を示して
いる。チツプサイズが小さい場合を示す第2図a
では、半導体チツプ1のボンデイングパツドから
リード片へのボンデイングワイヤ4はベース部材
21の凹部に配設されたワイヤボンデイング補助
パツド6を最短距離で結びながら配線されてい
る。補助パツド6を使用するため空間に張られる
1本当りのワイヤの長さを短くすることができワ
イヤ間やワイヤのたれ下りによるシヨート事故を
無くすることが可能となる。
Figure 2 shows the recess 21 that fits the maximum chip size.
1 shows the base member 21 of the package with 1. Figure 2a shows the case where the chip size is small.
In this case, the bonding wire 4 from the bonding pad of the semiconductor chip 1 to the lead piece is wired while connecting the wire bonding auxiliary pad 6 disposed in the recess of the base member 21 at the shortest distance. Since the auxiliary pad 6 is used, the length of each wire stretched in the space can be shortened, and it is possible to eliminate shoot accidents caused by wire gaps or wires hanging down.

第3図に示した実施例はワイヤボンデイング補
助パツド6を各辺に2列配設したものである。
In the embodiment shown in FIG. 3, two rows of wire bonding auxiliary pads 6 are arranged on each side.

図において31はパツケージに固着されたリー
ド片のボンデイングパツドであり、5は半導体チ
ツプ1をパツケージに固着するダイアタツチ部を
示している。各辺に2列配設した補助パツド6は
リード片のボンデイングパツド31の数と同数で
あるが、これに制限されるものではない。また第
2図bのような半導体チツプ1の場合には補助パ
ツド61はパツケージ凹部211の中央部に配設
されたダイアタツチ部5と同様にダイアタツチと
することが可能である。
In the figure, 31 is a bonding pad of a lead piece fixed to the package, and 5 is a die attach portion for fixing the semiconductor chip 1 to the package. The number of auxiliary pads 6 arranged in two rows on each side is the same as the number of bonding pads 31 on the lead piece, but the number is not limited to this. Further, in the case of the semiconductor chip 1 as shown in FIG. 2B, the auxiliary pad 61 can be a die attach like the die attach section 5 disposed in the center of the package recess 211.

なお本発明はパツケージの実装方法、例えば
DIP(Dual in package)、FP(Flat Package)、
PAP(Pin array package)、LCC(Leadless
chip carrier)などの方法のいづれにも適用可能
である。
Note that the present invention relates to a package mounting method, for example,
DIP (Dual in package), FP (Flat package),
PAP (Pin array package), LCC (Leadless
It is applicable to any method such as chip carrier).

(7) 発明の効果 本発明により従来1種類のパツケージにより搭
載可能な半導体チツプサイズの許容幅は最大約2
mm程度であつたが、これを3倍以上に拡大するこ
とができパツケージ種類の標準化による統一が可
能となり、またシヨート事故が無くなるため高い
信頼性が得られる効果を有する。
(7) Effects of the invention According to the present invention, the allowable width of the semiconductor chip size that can be conventionally mounted with one type of package is approximately 2 at most.
mm, but this can be expanded to more than three times, making it possible to unify package types by standardizing them, and also having the effect of achieving high reliability by eliminating shot accidents.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来技術を説明するためのパツケージ
断面図、第2図は本発明によるパツケージ断面
図、第3図は本発明によるパツケージベース部の
上面図を示している。 図において、1,1a,1b,1cは半導体チ
ツプ、2,2a,2b,2cはパツケージ、21
はパツケージベース部材、22はパツケージふた
部材、211はパツケージ凹部、3はリード片、
31はリード片のボンデイングパツド、4はボン
デイングワイヤ、5はダイアタツチ部、6,6
1,62は補助パツドを示している。
FIG. 1 is a sectional view of a package for explaining the prior art, FIG. 2 is a sectional view of a package according to the present invention, and FIG. 3 is a top view of a package base according to the present invention. In the figure, 1, 1a, 1b, 1c are semiconductor chips, 2, 2a, 2b, 2c are packages, and 21
2 is a package base member, 22 is a package lid member, 211 is a package recess, 3 is a lead piece,
31 is a bonding pad of a lead piece, 4 is a bonding wire, 5 is a die attachment part, 6, 6
Reference numerals 1 and 62 indicate auxiliary pads.

Claims (1)

【特許請求の範囲】 1 パツケージ内凹部に配置した半導体チツプ上
の複数の電極を前記パツケージ端部の対応する導
電部材のパツドにワイヤボンデイングして成る半
導体装置において、 前記凹部内の中央部分に配設され前記半導体チ
ツプが固着されるダイアタツチ部と、 前記ダイアタツチ部と前記パツケージ端部のパ
ツドとの間の前記凹部内に、前記パツケージ端部
のパツドに沿つて複数列状に複数個配列された補
助パツドとを有し、 前記半導体チツプが前記複数列状に複数個配列
された補助パツドの内側の列状に複数個配列され
た補助パツド上に配設でき、且つ前記半導体チツ
プ上の複数の電極と前記パツケージ端部の対応す
る導電部材のパツドとがそれぞれ外側の列状に複
数個配列された補助パツドを介してワイヤボンデ
イングできるように構成されて成ることを特徴と
する半導体装置。
[Scope of Claims] 1. A semiconductor device in which a plurality of electrodes on a semiconductor chip arranged in a recess in a package are wire-bonded to corresponding pads of a conductive member at an end of the package, comprising: a die attach portion to which the semiconductor chip is fixed; and a plurality of pads arranged in a plurality of rows along the pad at the end of the package in the recess between the die attach portion and the pad at the end of the package. auxiliary pads, the semiconductor chips can be disposed on the plurality of auxiliary pads arranged in a row inside the plurality of auxiliary pads arranged in the plurality of rows, and the plurality of auxiliary pads on the semiconductor chips 1. A semiconductor device characterized in that the electrodes and the corresponding pads of the conductive member at the ends of the package can be wire-bonded via a plurality of auxiliary pads arranged in outer rows.
JP56213989A 1981-12-26 1981-12-26 Semiconductor device Granted JPS58114444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56213989A JPS58114444A (en) 1981-12-26 1981-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56213989A JPS58114444A (en) 1981-12-26 1981-12-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58114444A JPS58114444A (en) 1983-07-07
JPS649734B2 true JPS649734B2 (en) 1989-02-20

Family

ID=16648405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56213989A Granted JPS58114444A (en) 1981-12-26 1981-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58114444A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02196448A (en) * 1989-01-25 1990-08-03 Nec Corp Semiconductor device
KR950012290B1 (en) * 1993-05-14 1995-10-16 삼성전자주식회사 Memory module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108369A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Electronic components

Also Published As

Publication number Publication date
JPS58114444A (en) 1983-07-07

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