JPH0113147B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix storage device, and particularly to a matrix storage device suitable for storing data in a processing device that handles two-dimensional array data processing such as image data processing.

In systems that process two-dimensional array data, such as image data processing devices, there is a lot of processing in which data is continuously read out from memory in the vertical or horizontal direction, and much of the processing time is spent in this process from memory. The time is spent on operations to retrieve data in such order.

In order to access (read/write) continuous data at high speed, it is effective to simultaneously access data at consecutive adjacent addresses in parallel.
A method of simultaneous and parallel access was adopted.

However, when two-dimensional array data is accessed continuously, for example, if the addresses are continuous in the horizontal direction, the addresses when accessed continuously in the vertical direction are discrete addresses that span several units in the horizontal direction. Therefore, in the conventional parallel access method, there is no parallelization effect in the operation of successively retrieving vertical data (or horizontal data).
This method has the disadvantage of requiring a large amount of processing time. Even if multiple memory modules arranged in a matrix are arbitrarily accessed vertically or horizontally, the data input/output route for access has not been established, and it has not been possible to efficiently access multiple memory modules. It has become inaccessible.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-described drawbacks of the prior art and to provide a matrix storage device that can access two-dimensional array data in both the vertical and horizontal directions in parallel and simultaneously.

The present invention provides a memory module having a memory section arranged in a matrix, each of which has a two-dimensional array, and a data switch, horizontal and vertical data buses, and the above-mentioned memory module arranged in a matrix, each of which has a two-dimensional array, and a data switch. a control mechanism having a function of selecting an address of a memory module and a memory section therein, and operating the data switch to select which of the data buses each memory section should be connected to according to the access direction; It is characterized by having the following. In other words, the configuration of the data path between each memory module and the data register for writing/reading is such that each memory module belonging to the same row and column is routed through the data switch in the module in the common row direction and column direction. The device is characterized by a configuration in which it is connected to an internal data bus and a data register for writing/reading via a data bus switch.

Hereinafter, the present invention will be explained in detail with reference to Examples.
FIG. 1 is an explanatory diagram of two-dimensional array data and its continuous access, and the array D2 in the figure is assumed to be two-dimensional data stored as it is in a memory having a matrix-like structure. In other words, this memory has a capacity of 16K words and 8 bits, and addresses are divided into x (horizontal) and y (vertical) and represented by a matrix of 128 in the x direction and 128 in the y direction, and the data width of 1 word (1 byte). is expressed in the thickness direction.

For example, when retrieving data from this memory, 1
One is to take out in the horizontal order x ₀ y ₀ , x ₁ y ₀ ...x ₁₂₇ y ₀ , and then change the row and take out in the order x ₀ y ₁ , x ₁ y ₁ ... In some cases, the columns are extracted in the order of x ₀ y ₀ , x ₀ y ₁ , ...x ₀ y ₁₂₇ , or in the order of x ₁ y ₀ , ... by changing the columns. In order to speed up this retrieval, in the present invention, for example, four pieces of consecutive data are accessed in parallel, and the first
As shown by RY (vertical readout) and RX (horizontal readout) in the figure, high-speed readout is possible in either direction.

In addition, in conventional devices, retrieval in only one direction, such as RY in Figure 1, is achieved by dividing the memory into four parts and storing two-dimensional data in them in an interleaved manner. It was also widely used in the main memory of computers.

However, since it can only be parallelized like RY in Figure 1, for example, if you try to obtain continuous data in the horizontal direction, first, as shown in R1 in Figure 2, the first column of array D2 is The second column is sequentially accessed four times, and so on, and the first column of the data string R1 obtained in this way is retrieved again.
The rearrangement operation as shown in 2 was not possible to speed up because it was performed sequentially.

An embodiment of the present invention that solves these problems is shown in the block diagram of FIG. The storage device 1 in this row includes memory modules 300 to 333 (16
), data bus switches 6 and 7 , a memory module control circuit 8 , and a data bus switch control circuit 9 . , and a data register 13.

Data switches 4 and 5 and data bus switches 6 and 7 are connected to RAM 3 and data register 13.
The memory module control circuit 8 is for distributing selection commands to the RAM 3 of each of the memory modules 300 to 333 and opening/closing commands for the data switches 4 and 5. The data bus switch control circuit 9 is for distributing open/close commands to the data bus switches 6 and 7, and the address counters 11 and 12 are for specifying the address of the storage device 1 as a pair. Reference numeral 13 mediates data exchange between the storage device 1 and the processing device 2, and the control circuit 10 issues operation commands to the storage device 1, as well as address counters 11 and 12 and data register 1 related to memory access.
This is for controlling 3.

Each RAM3 of memory modules 300 to 333
The data input/output ports are connected to internal data buses XB0 to XB3 that connect memory modules in the same column via data switch 4, and data switch 5.
Internal data bus YB0 that connects members of the same line via
- YB3, and the internal data buses XB0 to XB3 and YB0 to YB3 are integrated into one parallel data bus DB via data bus switch 7 and data bus switch 6, respectively, and the data register 13 is connected to combined.

On the other hand, the control signal from the control circuit 10 and the address designation signals from the address counters 11 and 12 are distributed to the memory modules 300 to 333 through the memory module control circuit 8 (in FIG. (The signal routes from the control circuit 8 to the memory modules 300 to 333 are omitted from the second example to avoid cluttering the drawings.)

FIG. 4 shows details of each block function in FIG. 3.

RAM3 stores 1K words of 8-bit data, and specifies an address on terminals A1 (5 bits) and A2 (5 bits), a read or write function on terminal WE, and a signal on terminal CS. When given, data is read and written from the data port of terminal D0 (8 bits). Memory module 300~
333, a memory module selection circuit 14 and a data switch control circuit 15 are added for controlling activation of the RAM 3 and opening/closing of the data switches 4 and 5. Decoders 16 and 17 are provided within the memory module control circuit 8, and decode the lower two bits of the address counters 11 and 12, respectively, and distribute the decoders to the module selection circuit 14. The correspondence relationship between the outputs X0 to X3, Y0 to Y3 of the decoders 16 and 17 and the memory modules 300 to 333 is as follows.
For example, the module selection circuit 14 of the memory module 300 is connected to the X0 output of the decoder 16 and the Y0 output of the decoder 17.
The upper five bits of access counters 11 and 12 are commonly connected to RAM 3 of all memory modules, and specify the address of 1K words inside RAM 3. The control signals given from the control circuit 10 to the storage device 1 include a signal W/FUNCTION that specifies the read/write transfer direction, and a signal Y that specifies whether data specific to the storage device of the present invention is to be accessed vertically or horizontally. /MODE signal, and these control signals are sent to the module selection circuit 14 and data switch control circuit 15 of all memory modules.
is sent to the data bus switch control circuit 9,
Start RAM3 with the above X0 to X3, or
In addition to switching the data switches 4 and 5 and the data bus switches 6 and 6,
Controls the opening and closing of 7.

FIG. 5 shows an X address counter 11 and a Y address counter 12 in the above configuration.
address information (x _{0 to 127} ; y _{0 to 127} ) and memory module number (indicated by X0 to X3, Y0 to Y3)
The address correspondence of RAM3 is shown.

That is, first, if the array (two-dimensional data) D2 is 128 x 128 bytes as shown in Figure 1, then this array D
2 is divided into small matrices of 4 bytes by 4 bytes in order from the upper left according to the 4 by 4 arrangement of memory modules. In this way, an array of 32 (=128/4) x 32 small matrices is created, so if we give them the representation (I, J) (I, J = 0 to 31), we get 4 x
Each element of the small matrix (I, J) of No. 4 is allocated one by one to the element in the I-th row and J-th column in each RAM in the memory module shown in FIG. Here each RAM is 1K byte (1024 bytes to be exact), so 32 x 32 =
One element from each of the 1024 submatrices is exactly
Applies to RAM. Each frame in Figure 5 represents one
It represents RAM3, and the allocation result in the interleap method as described above is the address (X ₁ Y ₁ )
It is shown in the form of

Now, with the above configuration, the address counter 11,
12 is set to “0” as the initial value, and the control circuit 1
When Y/MODE of 0 is set to "1", among memory modules 300 to 333, memory modules 300, 310, 320, 330 in the first row
When the RAM 3 of the same memory module is activated, the data switch 4 and the data bus switch 7 of the same memory module are turned on, and are coupled to the data register 13. The data for the row is obtained. Next, when the value of the X address counter 11 is +4, RX
Obtain the data for the second row. When the value of the X address counter 11 reaches 124, the value of the Y address counter 12 is increased by 1, and the value of the X address counter 1 is increased.
When the value of 2 is returned to “0”, memory module 3
Moving to row 01, data in the construction direction shown in RX in FIG. 1 is sequentially obtained.

Next, control circuit 9 sets Y/MODE to “0”.
, and the initial values of address counters 11 and 12 are set to "0", the memory module 30
0, 301, 302, and 303 are activated, and the data switch 5 and data bus switch 6 are closed to be coupled to the data register 13. After the data of the first row is obtained, the value of the Y address counter 12 is incremented by 4, and when the value of the Y address counter 12 reaches 124, the value of the X address counter 11 is incremented by 1. 12 to sequentially obtain data in the vertical direction. It is assumed that the update control of the address counter is included in the control circuit 10, and a detailed explanation of the specific means will be omitted.

The above is a description of continuous reading from the address (x ₀ y ₀ ), but it goes without saying that arbitrary values can be set in the address counters 11 and 12 to allow random access. However, it should be noted that, for example, in the operation mode in the RY direction in FIG. However, this (of course, it includes data at the address in question) occurs not only in the device of the present invention but also in parallel access in general, and does not impede the purpose of the present invention.

Furthermore, although the above embodiments have been described using specific values such as the size of two-dimensional data and the number of memory modules, these can easily be generalized.

As is clear from the above description, according to the present invention, it is possible to access two-dimensional data in parallel in both the vertical and horizontal directions.For example, when the number of parallels is 4, compared to the conventional Compared to parallelization, the average throughput of vertical and horizontal continuous access is
The effect is that it can be improved by 2.5 times.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of two-dimensional array data and its parallel reading, FIG. 2 is an explanatory diagram of a conventional reading method, FIG. 3 is an overall block diagram showing an embodiment of the present invention, and FIG. FIG. 2 is a diagram showing the detailed logical configuration of the embodiment, and FIG. 5 is a diagram showing address assignment of the RAM. 1... Matrix storage device, 2... Processing device, 3...
RAM, 4, 5...Data switch, 6, 7...Data bus switch, 8...Memory module control circuit, 9...Data bus switch control circuit, 10...Control circuit, 11, 12...Address counter, 13...
Data register, 14...Memory module selection circuit, 15...Data switch control circuit, 16, 17
...Address decoder, XB0~XB3, XB0~
YB3...Data bus, 300~303,310~
313,320-323,330-333...Memory module.

Claims (1)

[Claims] 1 A plurality of memory modules arranged in a matrix, each including a memory section having an array structure, a column direction data switch, and a row direction data switch, and a memory module for each column of the memory module arrangement. a column direction data bus coupled to the memory section of the memory module via the column direction data switch; and a row direction data bus coupled to the memory section of the memory module for each row of the memory module array via the row direction data switch. a selection mechanism that selects either the column direction data bus or each row direction data bus and connects it to the processing device; a column-direction or row-direction data bus that activates memory sections in all memory modules in parallel, turns on column-direction switches or row-direction switches in the memory modules, and connects the activated memory modules; and a control mechanism for controlling the selection mechanism so as to connect the memory module to the processing device, and thus configured to be able to access in parallel a number of pieces of data equal to the number of pieces of data in the column direction or row direction of the array of the memory modules. A matrix storage device characterized by: