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JPH0113260B2 - - Google Patents
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JPH0113260B2 - - Google Patents

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Publication number
JPH0113260B2
JPH0113260B2 JP18164083A JP18164083A JPH0113260B2 JP H0113260 B2 JPH0113260 B2 JP H0113260B2 JP 18164083 A JP18164083 A JP 18164083A JP 18164083 A JP18164083 A JP 18164083A JP H0113260 B2 JPH0113260 B2 JP H0113260B2
Authority
JP
Japan
Prior art keywords
circuit
line
signal
receiving
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18164083A
Other languages
Japanese (ja)
Other versions
JPS6072344A (en
Inventor
Masaaki Sasagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP18164083A priority Critical patent/JPS6072344A/en
Publication of JPS6072344A publication Critical patent/JPS6072344A/en
Publication of JPH0113260B2 publication Critical patent/JPH0113260B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/14Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、バースト状のデイジタル信号が双方
向に伝送される時分割方向制御による二線式回線
に挿入され、双方向に再生中継を行う中継器の改
良に関する。
[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a two-wire circuit that is inserted into a two-wire line using time-division direction control in which a burst digital signal is transmitted in both directions, and is regenerated and relayed in both directions. Concerning improvements to repeaters.

〔従来技術の説明〕[Description of prior art]

デイジタル通信網では、時分割方向制御による
二線式回線の伝送が検討されている。これは例え
ば加入者回線として、バースト状のデイジタル信
号が双方向に伝送される二線式回線を利用するも
ので、局装置と宅内装置との間に二線式回線を設
け、局装置が所定のバースト長のデイジタル信号
をこの二線式回線に送信し、宅内装置がこのデイ
ジタル信号を受信すると、宅内装置が所定のバー
スト長のデイジタル信号をこの二線式回線に送信
し、これを局装置が受信すると再び局装置が所定
のバースト長のデイジタル信号をこの二線式回線
に送信するようにして、これを繰り返して双方向
通信を行うものである。この二線式回線が長く伝
送信号が減衰して受信識別が困難になる場合に
は、その回線に伝送される信号を中継増幅するた
めの中継器が必要である。
In digital communication networks, two-wire line transmission using time-division direction control is being considered. For example, this uses a two-wire line as a subscriber line on which burst digital signals are transmitted bidirectionally.A two-wire line is installed between the station equipment and the home equipment, and the station equipment When a digital signal with a burst length of When received, the station device again transmits a digital signal of a predetermined burst length to this two-wire line, and this is repeated to perform two-way communication. If this two-wire line is long and the transmitted signal is attenuated, making reception identification difficult, a repeater is required to relay and amplify the signal transmitted over the line.

第1図にこのための従来例中継器のブロツク構
成図を示す。これは、 J.P.Andry、et al:A long Burst Time−
shared Digital Transmission System for
Subscriber Loops、ISSLS(International
Symposium on Subscriber Loops and
Service)1980年の資料に発表されたものである。
FIG. 1 shows a block diagram of a conventional repeater for this purpose. This is JP Andry, et al: A long Burst Time−
shared Digital Transmission System for
Subscriber Loops, ISSLS (International
Symposium on Subscriber Loops and
Service) This was published in a 1980 document.

第1図は局装置1と宅内装置2との間に二線式
回線3,3′が施設され、その二線式回線の中間
に双方向中継器4が挿入された状態を示す。この
中継器4は上位回線接続端子11は上位側切換回
路12に接続され、下位回線接続端子13は下位
側切換回路14に接続され、この二つの切換回路
12と14は第1図に実線で示す状態と破線で示
す状態とに交互に同期して切換えられて、双方向
の中継を行うように構成されている。
FIG. 1 shows a state in which two-wire lines 3, 3' are installed between the station equipment 1 and the home equipment 2, and a two-way repeater 4 is inserted between the two-wire lines. In this repeater 4, the upper line connection terminal 11 is connected to the upper side switching circuit 12, and the lower line connection terminal 13 is connected to the lower side switching circuit 14, and these two switching circuits 12 and 14 are indicated by solid lines in FIG. It is configured to perform bidirectional relay by alternately and synchronously switching between the state shown and the state shown by the broken line.

すなわち、上位側回線接続端子11に到来する
バースト状のデイジタル信号は上位側切換回路1
2の受信端子Rに現れ、下り用の受信回路16に
より識別再生されて、下り用の送信回路17で線
路送信レベルに増幅され、下位側の切換回路14
の送信端子Tから下位回線接続端子13に送信さ
れる。この下り方向の中継送信が終わると、制御
回路20は上位側切換回路12を送信端子Tに、
下位側切換回路14を受信端子Rにそれぞれ第1
図に破線で示す通路に切換えて、バツフア回路2
1に一時記憶されていた上りのバースト状デイジ
タル信号を読出し、送信回路23から上位回線接
続端子11に送信する。この間に、下位回線接続
端子13に信号が到来すると、下位側切換回路1
4の受信端子Rから上り用の受信回路24がこれ
を受信し、識別再生を行つてフレーム同期回路2
5の制御によりバツフア回路21にこの信号を一
時記憶する。
That is, the burst digital signal arriving at the upper line connection terminal 11 is transmitted to the upper line switching circuit 1.
2, is identified and regenerated by the downstream receiving circuit 16, is amplified to the line transmission level by the downstream transmitting circuit 17, and is transmitted to the lower side switching circuit 14.
is transmitted from the transmission terminal T to the lower line connection terminal 13. When this relay transmission in the downstream direction is completed, the control circuit 20 switches the upper side switching circuit 12 to the transmission terminal T.
The lower side switching circuit 14 is connected to the receiving terminal R, respectively.
Switch to the passage indicated by the broken line in the figure, and
The upstream burst-like digital signal temporarily stored in 1 is read out and transmitted from the transmitting circuit 23 to the upper line connection terminal 11. During this time, if a signal arrives at the lower line connection terminal 13, the lower side switching circuit 1
The uplink receiving circuit 24 receives this from the receiving terminal R of 4, performs identification and reproduction, and sends it to the frame synchronization circuit 2.
5, this signal is temporarily stored in the buffer circuit 21.

この動作を第2図のタイムチヤートに示す。第
2図A〜Dはそれぞれ第1図に示すA〜Dの点の
信号を示す。すなわちこの従来例方式では、下り
の信号については、第2図Bに示すように上位回
線接続端子11に下り受信信号が到来すると、そ
れは受信回路16で受信再生され、第2図Cに示
すように同時に送信回路17から下りの送信信号
として送信される。これに対して上りの信号につ
いては、第2図Bに示すように下りの受信信号の
バーストが終了すると、ガードタイムTgを経過
して上りの送信信号を送信する。この間に宅内装
置2では第2図Dに示すように、受信信号のバー
ストが終了すると同じくガードタイムTg′を経過
して送信信号を送信するので、第2図Bで上りの
送信信号を送信中に、上りの受信信号が受信回路
24に到来することになる。
This operation is shown in the time chart of FIG. 2A to 2D show signals at points A to D shown in FIG. 1, respectively. That is, in this conventional method, when a downlink signal arrives at the upper line connection terminal 11 as shown in FIG. 2B, it is received and regenerated by the receiving circuit 16, and as shown in FIG. 2C. At the same time, the signal is transmitted as a downstream transmission signal from the transmission circuit 17. On the other hand, regarding the upstream signal, as shown in FIG. 2B, when the burst of the downstream reception signal ends, the upstream transmission signal is transmitted after the guard time Tg has elapsed. During this time, as shown in Fig. 2D, the home device 2 transmits the transmission signal after the guard time Tg' has elapsed after the burst of the received signal ends, so in Fig. 2B, the upstream transmission signal is being transmitted. Then, the upstream received signal arrives at the receiving circuit 24.

送信回路23が送信する信号のレベルは回線3
の伝送損失を配慮して高いレベルである。これに
対して受信回路24が受信する信号のレベルは、
回線3′で減衰した信号であり低いレベルである。
したがつて、送信回路23の出力と受信回路24
の入力との間のわずかな回り込みにより、送信回
路23の出力信号が受信回路24の入力信号に漏
洩すると受信回路24の受信信号には雑音とな
る。この回り込みを小さくするには、回路の遮蔽
あるいは電源回路の区分などに設計上の配慮をす
る必要があるが、限られた形状の中継器ではこの
回り込みを小さくすにには限界がある。したがつ
て、この回り込みによる雑音の影響を小さくしよ
うとすれば、送信回路23の送信レベルと受信回
路24の受信レベルとの差を大きくすることがで
きず、すなわちこの中継器4の中継間隔を大きく
することができないことになる。
The level of the signal transmitted by the transmitting circuit 23 is line 3.
This is a high level considering transmission loss. On the other hand, the level of the signal received by the receiving circuit 24 is
This is a signal that has been attenuated on line 3' and is at a low level.
Therefore, the output of the transmitting circuit 23 and the receiving circuit 24
If the output signal of the transmitting circuit 23 leaks into the input signal of the receiving circuit 24 due to a slight wrap-around between the input signal and the input of the receiving circuit 24, noise will be generated in the received signal of the receiving circuit 24. In order to reduce this wraparound, it is necessary to take design considerations into circuit shielding, power circuit division, etc., but there is a limit to reducing this wraparound with repeaters of limited shapes. Therefore, if we try to reduce the influence of noise due to this wraparound, it is impossible to increase the difference between the transmission level of the transmission circuit 23 and the reception level of the reception circuit 24, that is, the relay interval of this repeater 4 cannot be increased. This means that it will not be possible to make it larger.

〔発明の目的〕[Purpose of the invention]

本発明はこれを改良するもので、中継器内の送
信回路から受信回路への回り込みの大きさをある
程度許容しても、回り込みの影響のない中継器を
提供することを目的とする。すなわち本発明は、
中継器内の回り込みによる雑音に起因して、中継
間隔が制約を受けることがない双方向中継器を提
供することを目的とする。
The present invention is an improvement on this, and an object of the present invention is to provide a repeater that is free from the influence of loop-around even if the amount of loop-circuit from the transmitting circuit to the receiving circuit in the repeater is allowed to some extent. That is, the present invention
It is an object of the present invention to provide a bidirectional repeater in which the repeating interval is not restricted due to noise caused by looping within the repeater.

〔発明の特徴〕[Features of the invention]

本発明は、従来方式では上り方向の信号回路の
みに設けられていたバツフア回路を下り方向の信
号回路にも設け、下り用の送信回路が信号を送信
するときには上り用の送信回路も同時に送信を行
い、下り用の受信回路が信号を受信するときには
上り用の受信回路も同時に受信を行うようにし
て、送信回路と受信回路とが同時に動作する時間
をなくして回り込みの影響を排除することを特徴
とする。
In the present invention, a buffer circuit, which was provided only in the upstream signal circuit in the conventional system, is also provided in the downstream signal circuit, so that when the downstream transmitting circuit transmits a signal, the upstream transmitting circuit also transmits at the same time. When the downstream receiving circuit receives a signal, the upstream receiving circuit also receives the signal at the same time, eliminating the time when the transmitting circuit and the receiving circuit operate simultaneously, thereby eliminating the influence of feedback. shall be.

〔実施例による説明〕[Explanation based on examples]

第3図は本発明は実施例装置のブロツク構成図
である。局装置1と宅内装置2との間に、一対の
金属線による二線式回線3,3′が施設され、そ
の回線が長いためにそのほぼ中間に本発明による
双方向中継器4が挿入された状態を示す。局装置
1の方向を上位、宅内装置2の方向を下位とし、
宅内装置2から局装置1に向けて伝送される信号
を上りの信号、局装置1から宅内装置2に向けて
伝送される信号を下りの信号とする。
FIG. 3 is a block diagram of a device according to an embodiment of the present invention. A two-wire line 3, 3' made of a pair of metal wires is installed between the station equipment 1 and the home equipment 2, and since the line is long, a bidirectional repeater 4 according to the present invention is inserted approximately in the middle thereof. Indicates the condition. The direction of the station equipment 1 is the upper one, the direction of the home equipment 2 is the lower one,
A signal transmitted from the home device 2 to the station device 1 is an upstream signal, and a signal transmitted from the station device 1 to the home device 2 is a downstream signal.

二線式回線3は上位回線接続端子11に接続さ
れる。この端子11は上位側切換回路12の共通
端子に接続される。一方下位側の二線式回線3′
は下位回線接続端子13に接続され、この端子1
3は下位側切換回路14の共通端子に接続され
る。上位側切換回路12の受信端子Rは受信回路
16の入力に接続される。この受信回路16は受
信信号を識別再生する機能を有する。その出力は
バツフア回路26の入力に接続される。このバツ
フア回路26の読出し出力は送信回路17の入力
に導かれ、その出力は下位側切換回路14の送信
端子Tに接続される。また、下位側切換回路14
の受信端子Rは受信回路24の入力に接続され、
その受信回路24の出力はバツフア回路21の入
力およびフレーム同期回路25に与えられる。こ
のバツフア回路21はフレーム同期回路25の制
御により受信回路24の出力信号を一時記憶し、
制御回路20の制御によりその内容を読出して送
信回路23の入力にこれを供給する。送信回路2
3の出力は上位側の切換回路12の送信端子Tに
接続される。
The two-wire line 3 is connected to an upper line connection terminal 11. This terminal 11 is connected to a common terminal of the upper switching circuit 12. On the other hand, the two-wire line 3' on the lower side
is connected to the lower line connection terminal 13, and this terminal 1
3 is connected to a common terminal of the lower side switching circuit 14. A receiving terminal R of the upper switching circuit 12 is connected to an input of the receiving circuit 16. This receiving circuit 16 has a function of identifying and reproducing received signals. Its output is connected to the input of buffer circuit 26. The readout output of this buffer circuit 26 is led to the input of the transmission circuit 17, and its output is connected to the transmission terminal T of the lower side switching circuit 14. In addition, the lower side switching circuit 14
The receiving terminal R of is connected to the input of the receiving circuit 24,
The output of the receiving circuit 24 is applied to the input of the buffer circuit 21 and the frame synchronization circuit 25. This buffer circuit 21 temporarily stores the output signal of the receiving circuit 24 under the control of the frame synchronization circuit 25.
The contents are read out under the control of the control circuit 20 and supplied to the input of the transmitting circuit 23. Transmission circuit 2
The output of No. 3 is connected to the transmission terminal T of the switching circuit 12 on the upper side.

ここで本発明の特徴とするところは、下り用の
受信回路16の出力と送信回路17との間にも、
バツフア回路26を設けて、下りの信号をも一時
記憶させ、このバツフア回路26および上り用の
バツフア回路21の読出しを、制御回路20によ
り同期して行うところにある。
Here, the feature of the present invention is that between the output of the downstream receiving circuit 16 and the transmitting circuit 17,
A buffer circuit 26 is provided to temporarily store downstream signals, and reading from this buffer circuit 26 and the upstream buffer circuit 21 is performed synchronously by the control circuit 20.

本発明の装置の動作を第4図に示すタイムチヤ
ートを用いて詳しく説明する。第4図A〜Dは第
3図に示す本発明実施例装置のA〜Dに示す点の
信号タイムチヤートを示す。
The operation of the apparatus of the present invention will be explained in detail using the time chart shown in FIG. 4A to 4D show signal time charts at points A to D of the apparatus according to the embodiment of the present invention shown in FIG.

第4図Aに示すように回線3にバースト状の信
号が送信されると、回線3で遅延されて第4図B
に示すように中継器4の上位回線接続端子11に
到来する。このとき、切換回路12および14は
第3図に示す実線の状態に設定されている。この
信号は切換回路12の受信端子Rから受信回路1
6の入力に与えられ、信号の識別再生が行われ
る。この受信回路16の出力は、制御回路20に
よりそのフレーム同期が検出されて、この制御回
路20の制御により、バツフア回路26に記憶さ
れる。
When a burst signal is sent to line 3 as shown in Figure 4A, it is delayed on line 3 and is shown in Figure 4B.
The signal arrives at the upper line connection terminal 11 of the repeater 4 as shown in FIG. At this time, the switching circuits 12 and 14 are set to the state shown by the solid line in FIG. 3. This signal is transmitted from the receiving terminal R of the switching circuit 12 to the receiving circuit 1.
6, and the signal is identified and reproduced. The frame synchronization of the output of the receiving circuit 16 is detected by the control circuit 20, and the output is stored in the buffer circuit 26 under the control of the control circuit 20.

この受信回路16およびバツフア回路26によ
る受信書込みが、一つのバースト状信号について
実行されてから、制御回路20は切換回路14お
よび12を第3図に破線で示す方向に切換え、あ
らかじめ設定されたガードタイムTgを経過した
ときに、バツフア回路26に一時記憶されていた
信号を読出し、送信回路17で線路送信レベルに
増幅して、第4図Cに示すように、切換回路14
から下位側接続端子13に送信する。
After the receiving circuit 16 and the buffer circuit 26 have performed reception writing for one burst signal, the control circuit 20 switches the switching circuits 14 and 12 in the direction shown by the broken line in FIG. When the time Tg has elapsed, the signal temporarily stored in the buffer circuit 26 is read out, and the signal is amplified to the line transmission level in the transmission circuit 17, and as shown in FIG.
from there to the lower connection terminal 13.

宅内装置2では、第4図Dに示すようにこのバ
ースト状信号を受信し、その受信が完了してから
所定のガードタイムTg′が経過すると、こんどは
二線式回線3′に上りのバースト状信号を送信す
る。このバースト状信号は回線3′で遅延を受け
て、第4図Cに示す上りの受信信号として中継器
4の下位側回線接続端子13に到来する。このと
きには、切換回路14および12は第3図に実線
で示す状態に切換えられていて、受信回路24は
この信号を受信識別再生して、その出力信号を同
期25の制御によりバツフア回路21に一時記憶
する。このとき、下りの信号についても局装置1
からの次のバースト状信号が上位側回線接続端子
11に到来し、受信回路16で識別再生されてバ
ツフア回路26に記憶される。
The in-home device 2 receives this burst signal as shown in FIG. send a signal. This burst signal is delayed in the line 3' and arrives at the lower line connection terminal 13 of the repeater 4 as an upstream received signal shown in FIG. 4C. At this time, the switching circuits 14 and 12 have been switched to the state shown by the solid line in FIG. Remember. At this time, the station equipment 1 also receives the downlink signal.
The next burst-like signal arrives at the upper line connection terminal 11, is identified and reproduced by the receiving circuit 16, and is stored in the buffer circuit 26.

このバースト状信号の受信が完了すると、再び
切換回路12および14は第3図に破線で示す状
態に切換えられて、所定のガードタイムTgの経
過後に、バツフア回路21からその一時記憶され
た内容が読出されて、送信23から線路送信レベ
ルで送信される。このとき同時に、バツフア回路
26からもその一時記憶された内容を読出し送信
回路17から上述のとおりの送信が行われる。こ
の動作を繰り返すことにより、第4図A〜Dに示
すように信号の送受信が行われることになる。
When the reception of this burst signal is completed, the switching circuits 12 and 14 are again switched to the state shown by the broken line in FIG. It is read out and transmitted from transmission 23 at line transmission level. At the same time, the temporarily stored contents are also read from the buffer circuit 26 and transmitted from the transmitting circuit 17 as described above. By repeating this operation, signals are transmitted and received as shown in FIGS. 4A to 4D.

すなわち本発明の中継器では、下り用の受信回
路16がバースト状信号を受信している状態で
は、上り用の受信回路24も信号を受信している
状態であつて、その受信を行つている間に送信回
路17および23からは信号の送信が行われな
い。また、下り用の送信回路17が信号の送信を
行つている間は上り用の送信回路23も送信を行
う時間であり、その時間に受信回路16および2
4の受信は行われない。したがつて、受信回路2
4の入力に送信回路23の出力信号の回り込みが
あつたとしても、そのときには受信回路24は受
信動作を行つていないのでその回り込みの影響は
ない。受信回路16についても、その受信動作中
には送信回路17および23は動作していないの
で、その入力に送信回路からの不要な回り込みに
よる雑音が影響を与えることはない。
That is, in the repeater of the present invention, when the downlink receiving circuit 16 is receiving the burst signal, the uplink receiving circuit 24 is also receiving the signal and is performing the reception. During this period, no signals are transmitted from the transmitting circuits 17 and 23. Further, while the downlink transmitting circuit 17 is transmitting a signal, the uplink transmitting circuit 23 is also transmitting, and at that time, the receiving circuits 16 and 2
4 is not received. Therefore, the receiving circuit 2
Even if the output signal of the transmitting circuit 23 is passed around to the input of the input circuit 4, the receiving circuit 24 is not performing a receiving operation at that time, so there is no effect of the running around. As for the receiving circuit 16, since the transmitting circuits 17 and 23 are not operating during the receiving operation, the input of the receiving circuit 16 is not affected by unnecessary noise from the transmitting circuit.

なお、第4図BおよびCに示す図では、上り下
りの受信動作と、上り下りの送信動作が完全に一
致するように描かれているが、これはこの中継器
4が局装置1と宅内装置2とのちようど中間の位
置挿入され、回線3と回線3′の遅延が等しく、
しかも、中継器4が下りのバースト状信号の受信
を完了してから上りの信号の送信を開始するまで
のガードタイムTgと、宅内装置が信号の受信を
完了してからつぎの信号の送信を開始するまでの
ガードタイムTg′が等しい理想的な場合を示して
いる。中継器4が局装置1と宅内装置2とのちよ
うど中間の位置からずれる場合には、第4図Bに
示す下りの信号の受信中に必ずしも第4図Cに示
す上りの受信信号が到来しないが、これはガード
タイムTgを適当に設けることにより、受信タイ
ミングと送信タイミングが重なることのないよう
に吸収することができる。すなわち、ガードタイ
ムTgの設定の範囲内で中継器4の設置位置を局
装置1と宅内装置2とのちようど中間の位置から
ずらしてもよいことになる。
Note that in the diagrams shown in FIGS. 4B and 4C, the upstream and downstream receiving operations and upstream and downstream transmitting operations are depicted as completely matching, but this is due to the fact that this repeater 4 is connected to the station equipment 1 and the home. After device 2 is inserted at an intermediate position, the delays of line 3 and line 3' are equal,
In addition, there is a guard time Tg from when the repeater 4 completes receiving the downlink burst signal to when it starts transmitting the uplink signal, and from when the in-home device completes receiving the signal to when it starts transmitting the next signal. An ideal case is shown in which the guard times Tg' until the start are equal. If the repeater 4 deviates from the intermediate position between the station equipment 1 and the home equipment 2, the upstream reception signal shown in FIG. 4C does not necessarily arrive while the downlink signal shown in FIG. 4B is being received. However, this can be absorbed by appropriately providing a guard time Tg so that the reception timing and transmission timing do not overlap. That is, the installation position of the repeater 4 may be shifted from the intermediate position between the station device 1 and the home device 2 within the range of the guard time Tg setting.

上述のように、受信回路16および24の受信
動作中には送信回路17および23が送信動作を
行うことがないので、本発明の中継器では回り込
みの影響は、信号レベルの高い送信回路の出力か
ら信号レベルの低い受信回路の入力への回り込み
を問題にする必要がなくなり、ともに信号レベル
の低い上下方向二つの受信回路16および24の
相互の回り込みのみを考慮すればよいことにな
る。すなわち、従来装置で送信回路の出力レベル
と受信回路の入力レベルに40dBのレベル差があ
り、回り込み信号との差を30dB取ろうとすれば、
ハードウエアの回り込み減衰量を70dB取る必要
があつたが、本発明によれば、同一の条件でハー
ドウエアの回り込み減衰量は30dBでよいことに
なり、ハードウエアの設計および製造の条件が著
しく緩和されるとともに、受信回路の入力レベル
と送信回路の出力レベルとの差をさらに大きくし
て、長い区間の中継を行うことのできる効率のよ
い中継器を設計製造することができることにな
る。
As mentioned above, since the transmitting circuits 17 and 23 do not perform the transmitting operation while the receiving circuits 16 and 24 are receiving, the influence of the wraparound in the repeater of the present invention is reduced to the output of the transmitting circuit with a high signal level. It is no longer necessary to consider the loop-around from the signal to the input of the receiving circuit where the signal level is low, and it is only necessary to consider the mutual loop-around between the two receiving circuits 16 and 24 in the upper and lower directions, both of which have low signal levels. In other words, in the conventional device, there is a level difference of 40 dB between the output level of the transmitting circuit and the input level of the receiving circuit, and if you try to remove the difference from the loop signal by 30 dB,
It used to be necessary to provide the hardware with a 70 dB attenuation, but according to the present invention, the hardware only needs to have a 30 dB attenuation under the same conditions, significantly easing the requirements for hardware design and manufacturing. At the same time, it becomes possible to further increase the difference between the input level of the receiving circuit and the output level of the transmitting circuit, and to design and manufacture an efficient repeater capable of relaying over a long distance.

第5図は本発明による効果を説明するための三
次元グラフである。第5図のx方向に上位側回線
の線路損失をとり、y方向に下位側回線の線路損
失をとり、z方向にハードウエアの回り込み減衰
量をとる。単位はいずれもdBである。ハツチン
グで示す二つの平面は第1図で説明した従来例装
置の場合であり、ドツトを表示する二つの平面は
第3図で説明した本発明実施例装置の場合であ
る。
FIG. 5 is a three-dimensional graph for explaining the effects of the present invention. In FIG. 5, the line loss of the upper line is plotted in the x direction, the line loss of the lower line is plotted in the y direction, and the amount of wraparound attenuation of the hardware is plotted in the z direction. All units are dB. The two planes indicated by hatching are for the conventional device explained in FIG. 1, and the two planes showing dots are for the device according to the present invention explained in FIG. 3.

従来例装置では、例えば、上位側および下位側
の回線の線路損失がともに40dBであるとすると、
x方向に40dB、y方向に40dBをとつたP点に対
して、受信回路入力信号のレベルと回り込みによ
つて混入する送信回路出力信号のレベルとが等し
くなる状態は、ハードウエアの回り込み減衰量が
40dBのときであるから、P点から垂直にz方向
に40dBを取つてQ点が得られる。仮に上位側お
よび下位側の回線の線路損失がともに0dBである
とすると、このときには原点Oであり、ハードウ
エア回り込み減衰量が0dBのときに、受信回路入
力信号のレベルと回り込みによつて混入する送信
回路出力信号のレベルとが等しくなるから、回り
込みによつて混入する送信回路出力信号のレベル
とが等しくなる状態は原点Oとなる。さらに、上
位側回線の線路損失が40dBであり、下位側回線
の線路損失が0dBであるならば、同様に受信回路
入力に回り込みによつて混入する送信回路出力信
号のレベルとが等しくなる状態は点Tとなり、下
位側回線の線路損失が40dBであり、上位側回線
の線路損失が0dBであるならば、同様に、受信回
路入力に回り込みによつて混入する送信回路出力
信号のレベルとが等しくなる状態は点Uとなる。
したがつて、平面OTQと平面OUQで区切られた
空間より下の空間で定まる条件では、回り込みに
よる信号が受信信号のレベルを上回ることにな
る。
In the conventional device, for example, if the line loss of both the upper and lower lines is 40 dB,
At point P, which is 40 dB in the x direction and 40 dB in the y direction, the state in which the level of the receiving circuit input signal and the level of the transmitting circuit output signal mixed in due to looping are equal is the amount of hardware looping attenuation. but
Since it is 40 dB, point Q can be obtained by taking 40 dB in the z direction perpendicularly from point P. Assuming that the line loss of both the upper and lower lines is 0 dB, at this time the origin is O, and when the hardware loop attenuation is 0 dB, the signal is mixed in due to the level of the receiving circuit input signal and loop loop. Since the level of the transmitting circuit output signal becomes equal to that of the transmitting circuit output signal, the state where the level of the transmitting circuit output signal mixed in due to looping becomes equal is the origin O. Furthermore, if the line loss of the upper side line is 40 dB and the line loss of the lower side line is 0 dB, the state in which the level of the transmitting circuit output signal mixed into the receiving circuit input by looping is equal to At point T, if the line loss of the lower line is 40 dB and the line loss of the upper line is 0 dB, similarly, the level of the transmitting circuit output signal mixed into the receiving circuit input by looping is equal to The state becomes point U.
Therefore, under the conditions determined by the space below the space divided by the plane OTQ and the plane OUQ, the signal due to wraparound will exceed the level of the received signal.

これに対して本発明の装置では、受信回路入力
に回り込みによつて混入する送信回路出力信号の
レベルとが等しくなる状態は、平面OTPおよび
平面OUPで表され、この二つの平面より下側の
空間ではじめて回り込みによる信号が受信信号の
レベルを上回ることになる。したがつて、第5図
に斜線を付して示す平面とドツトで示す平面の間
の空間に定まる条件が、本発明により完全された
領域になる。
On the other hand, in the device of the present invention, the state in which the level of the transmitting circuit output signal mixed into the receiving circuit input by loop-around is equal to the level is represented by the plane OTP and the plane OUP, and the state below these two planes is represented by the plane OTP and the plane OUP. For the first time in space, the signal due to wraparound exceeds the level of the received signal. Therefore, the conditions defined in the space between the hatched plane and the dotted plane in FIG. 5 are the area perfected by the present invention.

〔応用〕〔application〕

上記実施例では、局装置と宅内装置との間の加
入者線について本発明の中継器を挿入するように
説明したが、加入者線に限らず本発明は、バース
ト状のデイジタル信号が双方向に伝送される時分
割方向制御による二線式回線に挿入され、双方向
に再生中継を行う中継器として実施することがで
きる。上記上りあるいは下り、もしくは上位下位
などの表現は便宜的なものであり、その方向や接
続回線はどのように入れ換えても同様に実施する
ことができる。
In the above embodiment, the repeater of the present invention is inserted into the subscriber line between the station equipment and the home equipment, but the present invention is not limited to the subscriber line. It can be implemented as a repeater that is inserted into a two-wire line with time-division direction control transmitted to the network and performs regenerative relay in both directions. The above-mentioned expressions such as upstream or downstream, upper or lower, etc. are for convenience, and the same implementation can be performed even if the directions and connection lines are changed.

本発明は、一対の金属線による回線のほか、一
本の同軸線、一本の光フアイバなどによるあらゆ
る種類の二線式回線に実施することができる。
The present invention can be implemented in all kinds of two-wire lines, such as a single coaxial line, a single optical fiber, etc., in addition to a line using a pair of metal wires.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、中継器
内部で生じる信号の回り込みによる雑音の影響は
著しく改善される。本発明によれば、中継器ハー
ドウエアの設計製造上の制限が緩和され、経済的
な中継器装置を得ることができるとともに、送信
回路の出力レベルを受信回路の入力レベルに比べ
て高くすることができるので、長い中継間隔の中
継を行うことができる経済的な中継器を得ること
ができる。
As described above, according to the present invention, the influence of noise caused by signal wraparound occurring inside the repeater is significantly improved. According to the present invention, restrictions on the design and manufacture of repeater hardware are relaxed, an economical repeater device can be obtained, and the output level of the transmitting circuit can be made higher than the input level of the receiving circuit. Therefore, it is possible to obtain an economical repeater that can carry out relays with long repeating intervals.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例装置のブロツク構成図。第2図
は従来例装置の動作説明用タイムチヤート。第3
図は本発明実施例装置のブロツク構成図。第4図
は本発明は実施例装置の動作説明用タイムチヤー
ト。第5図は本発明の効果を説明する三次元グラ
フ。 11……上位回線接続端子、12……上位側切
換回路、13……下位回線接続端子、14……下
位側切換回路、16……下り用の受信回路、17
……上り用の送信回路、20……制御回路、21
……上り用のバツフア回路、23……上り用の送
信回路、24……上り用の受信回路、25……フ
レーム同期回路。
FIG. 1 is a block diagram of a conventional device. FIG. 2 is a time chart for explaining the operation of the conventional device. Third
The figure is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of the apparatus according to the embodiment of the present invention. FIG. 5 is a three-dimensional graph explaining the effects of the present invention. 11...Upper line connection terminal, 12...Upper side switching circuit, 13...Lower line connection terminal, 14...Lower side switching circuit, 16...Downlink receiving circuit, 17
...Uplink transmission circuit, 20...Control circuit, 21
...Uplink buffer circuit, 23...Uplink transmitting circuit, 24...Uplink receiving circuit, 25...Frame synchronization circuit.

Claims (1)

【特許請求の範囲】 1 上位側二線回線に接続される上位回線接続端
子と、 この端子の信号の送受を切換える上位側切換回
路と、 下位側二線回線に接続する下位回線接続端子
と、 この端子の信号の送受を切換える下位側切換回
路と、 上記上位側切換回路の受信側端子に到来する信
号を受信し識別再生を行う下り用の受信回路と、 この下り用の受信回路の出力を線路送信レベル
に増幅して上記下位側切換回路の送信端子に送信
する下り用の送信回路と、 上記下位側切換回路の受信端子に到来する信号
を受信し識別再生を行う上り用の受信回路と、 この上り用の受信回路の出力を一次記憶する上
り用のバツフア回路と、 この上り用バツフア回路の読出出力を線路送信
レベルに増幅して上記上位側切換回路の送信端子
に送信する上り用の送信回路と、 上記下り用の受信回路の出力に基づき上記上位
回線接続端子に受信信号が到来しないタイミング
に上記上位側切換回路を送信側に切換える制御手
段を含む制御回路と を備えた二線式デイジタル双方向中継器におい
て、 上記下り用の受信回路の出力を一次記憶してそ
の読出出力を上記下り用の送信回路の入力に与え
る下り用のバツフア回路を設け、 上記制御回路は、上記二つの送信回路の送信が
同時に行われ、上記二つの受信回路の受信が同時
に行われるように、上記二つの切換回路を制御す
るとともに、上記二つのバツフア回路の読出しお
よび書込みのタイミングを制御する手段を含むこ
とを特徴とする二線式デイジタル双方向中継器。
[Scope of Claims] 1. An upper line connection terminal connected to the upper two-line line, an upper switching circuit that switches transmission and reception of signals of this terminal, a lower line connection terminal connected to the lower two-line line, A lower-side switching circuit that switches transmission and reception of signals at this terminal; a downstream receiving circuit that receives and identifies and reproduces signals arriving at the receiving terminal of the upper-side switching circuit; and an output of this downstream receiving circuit. a downlink transmitting circuit that amplifies the signal to a line transmission level and transmits it to the transmitting terminal of the lower switching circuit; and an uplink receiving circuit that receives the signal arriving at the receiving terminal of the lower switching circuit and performs identification and regeneration. , an upstream buffer circuit that temporarily stores the output of this upstream receiving circuit, and an upstream buffer circuit that amplifies the readout output of this upstream buffer circuit to a line transmission level and transmits it to the transmission terminal of the upper switching circuit. A two-wire system comprising: a transmitting circuit; and a control circuit including a control means for switching the upper-level switching circuit to the transmitting side at a timing when a received signal does not arrive at the upper-level line connection terminal based on the output of the downstream receiving circuit. In the digital two-way repeater, a downlink buffer circuit is provided that temporarily stores the output of the downlink receiving circuit and provides its readout output to the input of the downlink transmitting circuit, It includes means for controlling the two switching circuits and controlling the read and write timings of the two buffer circuits so that the transmitter circuit transmits at the same time and the two receiver circuits receive at the same time. A two-wire digital two-way repeater characterized by:
JP18164083A 1983-09-28 1983-09-28 Two-wire type digital two-way repeator Granted JPS6072344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18164083A JPS6072344A (en) 1983-09-28 1983-09-28 Two-wire type digital two-way repeator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18164083A JPS6072344A (en) 1983-09-28 1983-09-28 Two-wire type digital two-way repeator

Publications (2)

Publication Number Publication Date
JPS6072344A JPS6072344A (en) 1985-04-24
JPH0113260B2 true JPH0113260B2 (en) 1989-03-06

Family

ID=16104292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18164083A Granted JPS6072344A (en) 1983-09-28 1983-09-28 Two-wire type digital two-way repeator

Country Status (1)

Country Link
JP (1) JPS6072344A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260330A (en) * 1985-09-10 1987-03-17 Fujitsu Ltd Digital subscriber line transmission system
GB2403101B (en) * 2003-06-18 2005-12-21 Matsushita Electric Industrial Co Ltd Extended dynamic resource allocation in packet data transfer

Also Published As

Publication number Publication date
JPS6072344A (en) 1985-04-24

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