JPH0113310B2 - - Google Patents
Info
- Publication number
- JPH0113310B2 JPH0113310B2 JP9171981A JP9171981A JPH0113310B2 JP H0113310 B2 JPH0113310 B2 JP H0113310B2 JP 9171981 A JP9171981 A JP 9171981A JP 9171981 A JP9171981 A JP 9171981A JP H0113310 B2 JPH0113310 B2 JP H0113310B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- load
- winding
- output
- transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】
本発明はDC−DCコンバータ、特に準安定化リ
ンギングチヨーク型DC−DCコンバータに関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DC-DC converter, and more particularly to a quasi-stabilized ringing chain type DC-DC converter.
従来の準安定化リンギングチヨーク型DC−DC
コンバータに於いては、第１図に示す様に、電圧
検出用の巻線N2を設け、該巻線N2に誘起された
電圧をダイオードD1・コンデンサC1から成る整
流平滑回路で整流平滑して、擬似負荷R1の両端
に発生する擬似出力電圧V1を誤差増幅器AMPに
導き、基準電圧VRと比較し、誤差電圧を増幅し
て、発振コントロール回路CNTによりスイツチ
SW1を断続するタイミングを制御して、負荷Ｌに
印加される出力電圧V0を安定化するという方法
が採られて来た。 Conventional meta-stabilized ringing chain type DC-DC
In the converter, as shown in Figure 1, a winding N2 for voltage detection is provided, and the voltage induced in the winding N2 is rectified by a rectifying and smoothing circuit consisting of a diode D1 and a capacitor C1 . The smoothed pseudo output voltage V 1 generated across the pseudo load R 1 is guided to the error amplifier AMP, compared with the reference voltage V R , the error voltage is amplified, and the oscillation control circuit CNT controls the switch.
A method has been adopted in which the output voltage V 0 applied to the load L is stabilized by controlling the timing at which SW 1 is turned on and off.
しかるにこの様な従来の方法に於いては、巻線
内の固有抵抗や巻線どうしの結合ロス、更には、
ダイオードの順方向電圧の変動などのため、入力
電圧Vinや負荷Ｌ等の変動に対して良好な安定化
出力を得ることが出来なかつた。例えば、重負荷
が印加され多大な出力電流が流れたり、入力電圧
Vinが低下したりすると、出力電圧V0は低下して
しまうが、この場合、従来方法では負荷変動を直
接検出せずに、擬似負荷R1における変動を検出
するだけなので正確な補償を行なうことができな
かつた。 However, in such a conventional method, the specific resistance within the winding, the coupling loss between the windings, and
Due to fluctuations in the forward voltage of the diode, it was not possible to obtain a well stabilized output against fluctuations in the input voltage Vin, load L, etc. For example, if a heavy load is applied and a large amount of output current flows, or if the input voltage
If Vin decreases, the output voltage V 0 will decrease, but in this case, the conventional method does not directly detect load fluctuations, but only detects fluctuations in the pseudo load R 1 , so accurate compensation cannot be performed. I couldn't do it.
本発明はこの様な従来の出力電圧安定化方法の
欠点を解消するためになされたものであり、出力
電圧の変動を忠実に検出して、トランスのー次側
の巻線のスイツチングのタイミングを制御するこ
とにより極めて安定な準安定化リンギングチヨー
ク型DCーDCコンバータを提供しようとするもの
である。 The present invention was made to eliminate the drawbacks of the conventional output voltage stabilization method, and it accurately detects fluctuations in the output voltage and adjusts the switching timing of the secondary winding of the transformer. The aim is to provide an extremely stable quasi-stable ringing chain type DC-DC converter through control.
以下図面に従つて本発明の実施例を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例を示す回路図であ
る。 FIG. 2 is a circuit diagram showing one embodiment of the present invention.
第２図に於いて、Vinは入力電圧源であつて、
トランスの１次側巻線N1及び該巻線N1をスイツ
チング駆動するスイツチSW1に接続されている。
N3は前記トランスの２次側の巻線であり、その
両端は整流平滑用ダイオードD2及びコンデンサ
C2に接続されている。Ｌは負荷であり前記コン
デンサC2の両端に印加される。V0は該負荷Ｌに
印加される出力電圧である。 In Figure 2, Vin is the input voltage source,
It is connected to the primary winding N1 of the transformer and a switch SW1 that switches and drives the winding N1 .
N3 is the winding on the secondary side of the transformer, and both ends of it are connected to a rectifying and smoothing diode D2 and a capacitor.
Connected to C2 . L is a load and is applied across the capacitor C2 . V 0 is the output voltage applied to the load L.
N2は電圧検出用巻線でありトランスの二次側
に捲回され、その両端は周波数変動検出回路FD
に接続されている。なお本実施例では周波数変動
検出回路FDはコンデンサCA及び抵抗器RAを高帯
域通過フイルタとして構成したものである。該周
波数変動検出回路には整流平滑用ダイオードD1
及びコンデンサC1及び負荷Ｌに擬制した擬似負
荷R1が接続されている。V1は擬似負荷R1の両端
に発生した擬似出力電圧であり誤差増幅器AMP
の一方の入力端子に導かれる。該誤差増幅器
AMPの他方の入力端子には基準電圧源VRが接続
されている。誤差増幅器AMPの出力は発振コン
トロール回路CNTに入力され、該発振コントロ
ール回路CNTの出力によつてスイツチSW1のス
イツチングのタイミングを制御する。 N2 is a voltage detection winding wound on the secondary side of the transformer, and both ends of it are connected to the frequency fluctuation detection circuit FD.
It is connected to the. In this embodiment, the frequency fluctuation detection circuit FD is configured by a capacitor C A and a resistor R A as a high band pass filter. The frequency fluctuation detection circuit includes a rectifying and smoothing diode D1 .
A simulated dummy load R 1 is connected to the capacitor C 1 and the load L. V 1 is the pseudo output voltage generated across the pseudo load R 1 and the error amplifier AMP
is led to one input terminal of the the error amplifier
A reference voltage source V R is connected to the other input terminal of the AMP. The output of the error amplifier AMP is input to an oscillation control circuit CNT, and the switching timing of the switch SW1 is controlled by the output of the oscillation control circuit CNT.
次に第２図の実施例の回路の動作を説明する。
ここで、本発明は負荷Ｌの軽重に応じてフイード
バツク系の発振周波数の高低が生ずるというリン
ギング型DC−DCコンバータの特性を利用して目
的を達成するものである。 Next, the operation of the circuit of the embodiment shown in FIG. 2 will be explained.
Here, the present invention achieves the object by utilizing the characteristic of the ringing type DC-DC converter that the oscillation frequency of the feedback system varies depending on the weight and weight of the load L.
いま、仮に重負荷が印加され多大の出力電流が
流れ、あるいは、入力電圧Vinが低下した為に、
出力電圧V0が低下したと仮定する。この場合に
は１次側巻線N1のスイツチング周波数も低下し
ているので、電圧検出用巻線N2を経由して周波
数変動検出回路FDによりスイツチング周波数の
低下が検出され、ダイオードD1・コンデンサC1
を経由して擬似負荷R1の両端の擬似出力電圧V1
も低下し出力電圧の変動が忠実に検出されたこと
となる。 Now, if a heavy load is applied and a large amount of output current flows, or the input voltage Vin drops,
Assume that the output voltage V 0 has decreased. In this case, since the switching frequency of the primary winding N1 has also decreased, the decrease in the switching frequency is detected by the frequency fluctuation detection circuit FD via the voltage detection winding N2 , and the switching frequency is detected by the diode D1 . Capacitor C 1
The pseudo output voltage V 1 across the pseudo load R 1 via
This means that the fluctuation in the output voltage has been faithfully detected.
出力電圧V1が低下したので誤差増幅器AMP及
び発振コントロール回路CNTの働きによりスイ
ツチSW1のスイツチングのタイミングが制御され
出力電圧V0が上昇するようになり出力は安定化
されることとなる。逆に軽負荷となつた場合に
は、検出周波数が高められ、擬似負荷R1の両端
の電圧も高くなるので重負荷時とは逆に出力電圧
V0が低められ、安定化される。 Since the output voltage V1 has decreased, the switching timing of the switch SW1 is controlled by the functions of the error amplifier AMP and the oscillation control circuit CNT, so that the output voltage V0 increases and the output is stabilized. On the other hand, when the load is light, the detection frequency is increased and the voltage across the pseudo load R1 also becomes higher, so the output voltage is lower than when the load is heavy.
V 0 is lowered and stabilized.
第３図は第２図の実施例の誤差増幅器AMP及
び発振コントロール回路CNTの具体的構成例を
示したものである。 FIG. 3 shows a specific example of the configuration of the error amplifier AMP and the oscillation control circuit CNT of the embodiment shown in FIG.
第３図に於いてTrはスイツチング用トランジ
スタであり、そのベースには基準電圧設定用抵抗
器R2・誤差増幅用ツエナーダイオードDZ及び発
振コントロール回路を構成するコンデンサCT・
抵抗器RT・巻線N0が接続されている。コンデン
サCT・抵抗器RTは発振回路の時定数を設定する
ためのものであり、ツエナーダイオードDZはそ
の肩電流特性を利用して誤差増幅器として動作す
る。第３図の回路の他の部分の構成・動作は第２
図の回路と同じであるので説明を省略する。 In Fig. 3, T r is a switching transistor, and its base includes a reference voltage setting resistor R 2 , an error amplifying Zener diode D Z , and a capacitor C T constituting the oscillation control circuit.
Resistor R T and winding N 0 are connected. The capacitor C T and resistor R T are used to set the time constant of the oscillation circuit, and the Zener diode D Z uses its shoulder current characteristics to operate as an error amplifier. The configuration and operation of other parts of the circuit in Figure 3 are as follows.
Since it is the same as the circuit shown in the figure, the explanation will be omitted.
尚、周波数変動検出回路FDの構成は前記実施
例に限定されず、周波数を検出できる機能を有す
るものであればどのような構成であつてもよい。
少なくとも高帯域通過フイルタを構成していれば
本発明の目的を達成できる。 Note that the configuration of the frequency fluctuation detection circuit FD is not limited to the above embodiment, and may be any configuration as long as it has a function of detecting a frequency.
The object of the present invention can be achieved by configuring at least a high bandpass filter.
本発明によれば、以上説明した様に、負荷変動
による周波数の変動を検出する周波数変動検出回
路を設け、出力電圧の変動を正確に検出して、ス
イツチングのタイミングを制御することにより極
めて安定化されたDC−DCコンバータが得られる
ものである。 According to the present invention, as explained above, a frequency fluctuation detection circuit is provided to detect frequency fluctuations due to load fluctuations, and output voltage fluctuations are accurately detected and switching timing is controlled to achieve extremely stable output voltage. A DC-DC converter is obtained.
第１図は従来の準安定化リンギングチヨーク型
DC−DCコンバータを示す回路図、第２図・第３
図は本発明の実施例を示す準安定化リンギングチ
ヨーク型DC−DCコンバータの回路図である。
N0，N1，N2，N3……巻線、D1，D2，DZ……
ダイオード、C1，C2，CA，CT……コンデンサ、
R1，R2，RA……抵抗器、Ｌ……負荷、AMP……
誤差増幅器、CNT……発振コントロール回路、
Tr……トランジスタ、FD……周波数変動検出回
路。
Figure 1 shows the conventional quasi-stabilized ringing chain type.
Circuit diagram showing DC-DC converter, Figures 2 and 3
The figure is a circuit diagram of a quasi-stable ringing chain type DC-DC converter showing an embodiment of the present invention. N 0 , N 1 , N 2 , N 3 ... winding, D 1 , D 2 , D Z ...
Diode, C 1 , C 2 , C A , CT ... Capacitor,
R 1 , R 2 , R A ...Resistor, L...Load, AMP...
Error amplifier, CNT...oscillation control circuit,
T r ...Transistor, FD...Frequency fluctuation detection circuit.
Claims (1)
イツチング手段によつて断続制御して前記トラン
スの２次側巻線から出力を得ると共に、前記トラ
ンスに設けられた電圧検出用巻線に接続された擬
似負荷に印加される電圧を基準電圧と比較し、こ
の比較結果に基づいて前記スイツチング手段を制
御して安定化出力を得るリンギングチヨーク型
DC−DCコンバータにおいて、前記電圧検出用巻
線と擬似負荷との間にコンデンサと抵抗器とによ
つて高帯域通過フイルタを構成してなる周波数変
動検出回路を設けることにより、出力電圧の変動
を補償したことを特徴とするDC−DCコンバー
タ。1 The voltage applied to the primary winding of the transformer is controlled intermittently by a switching means to obtain an output from the secondary winding of the transformer, and the voltage is connected to a voltage detection winding provided in the transformer. A ringing chain type that compares the voltage applied to the simulated load with a reference voltage and controls the switching means based on the comparison result to obtain a stabilized output.
In the DC-DC converter, by providing a frequency fluctuation detection circuit consisting of a high band pass filter with a capacitor and a resistor between the voltage detection winding and the pseudo load, fluctuations in the output voltage can be suppressed. A DC-DC converter characterized by compensation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9171981A JPS57211978A (en) | 1981-06-15 | 1981-06-15 | Dc/dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9171981A JPS57211978A (en) | 1981-06-15 | 1981-06-15 | Dc/dc converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57211978A JPS57211978A (en) | 1982-12-25 |
| JPH0113310B2 true JPH0113310B2 (en) | 1989-03-06 |
Family
ID=14034312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9171981A Granted JPS57211978A (en) | 1981-06-15 | 1981-06-15 | Dc/dc converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57211978A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3751770T2 (en) * | 1986-09-20 | 1996-11-14 | Canon Kk | Power source apparatus |
| CN101478142B (en) | 2008-12-16 | 2011-08-10 | 佛山市顺德区美的电热电器制造有限公司 | Power switch tube protecting circuit in semi-bridge induction heating circuit |
-
1981
- 1981-06-15 JP JP9171981A patent/JPS57211978A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57211978A (en) | 1982-12-25 |
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