JPH0113656B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switch circuit with an anti-chattering function.

FIG. 1 shows the conventional structure of a switch circuit with a chattering prevention function used in electronic watches and the like. Reference numeral 1 denotes a latch circuit constituted by NOR circuits 2 and 3, each of which has its own output signal serving as an input signal to the other NOR circuit. Further, a predetermined voltage, that is, a "1" signal is applied to one NOR circuit 2 via, for example, a time adjustment switch 4, and the other NOR circuit 3 is given a "1" signal as shown in FIG.
A clock pulse φ ₁ shown in FIG. and,
The output of the NOR circuit 2 is applied to the data input terminal D of the delayed flip-flop 5, and the clock input terminal C of the flip-flop 5 is connected to the second
Clock pulse ₂ shown in Figure b is input.

In the above configuration, when the switch 4 is open, the output of the switch 4 is "0", and the output of the NOR circuit 2 of the latch circuit 1 is held at the "1" state. Therefore, flip-flop 5 is in the set state. In this state, when the switch 4 is closed as shown in FIG. 2c, a "1" signal is applied to the NOR circuit 2 through this switch 4, and the output of the NOR circuit 2 becomes the output shown in FIG. 2d. As shown, it becomes "0". The "0" signal output from the NOR circuit 2 is read into the flip-flop 5 in synchronization with the rising edge of the clock pulse ₂ , as shown in FIG.
Its output is inverted from "1" to "0". The "0" output signal of the flip-flop 5 is sent to a processing circuit (not shown) as a switch signal. Therefore _, if chattering CH occurs as shown in FIG. The output is kept in the "0" signal state regardless of the chatter, as shown in FIG. 2f.

However, in the above conventional switch circuit,
Even if a pulse P with a short time width is generated on the output line of the switch 4 as shown in FIG. circuit 2
The output changes from “1” to “0” as shown in Figure 3d.
It is inverted and read into the flip-flop 5 in synchronization with the next clock pulse ₂ . As a result, the output of the flip-flop 5 becomes "0" as shown in FIG. 3f, and is sent to the processing circuit as a switch signal.

In this way, the conventional switch circuit described above can prevent chattering, but it is also possible to eliminate short pulses generated on the output line of the switch 4 due to the influence of static electricity when the switch 4 is opened. This can cause malfunctions.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a switch circuit that can prevent the effects of chattering and reliably prevent the effects of short pulses caused by static electricity etc. with a simple circuit. purpose.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 4, reference numeral 11 denotes a latch circuit, which is composed of a 2-input NOR circuit 12 and a 3-input NOR circuit 13. Each of the NOR circuits 11 uses its own output signal as the input signal of the other NOR circuit, a "1" signal is input to the NOR circuit 12 via the switch 4, and a clock pulse φ ₁ is input to the NOR circuit 13.
is input. The output of the NOR circuit 12 side of the latch circuit 11 is applied to the data input terminal D of the delayed flip-flop 5, and the clock pulse φ ₂ is input to the input terminal C of the flip-flop 5. The Q side output of this flip-flop 5 is input to the NOR circuit 13, and is also sent to a processing circuit (not shown) as a switch signal.
sent to.

Next, the operation of the present invention configured as described above will be explained. When the switch 4 is open, the input of the latch circuit 11 on the switch 4 connection side is “0”.
The output of the NOR circuit 12 is "1". Therefore, a "1" signal is read into the flip-flop 5, and a "1" signal is output from the output terminal Q. When a "1" signal is output from the flip-flop 5, the latch circuit 11 regulates the output of the NOR circuit 13 and maintains the signal state as "0" regardless of the clock pulse φ ₁ and the output level of the NOR circuit 12. . Therefore, the latch circuit 11
In this case, the NOR circuit 13 is equivalently separated from the NOR circuit 12, and the NOR circuit 12 operates as an inverter. The above latch circuit 11
This state continues as long as the flip-flop 5 provides a "1" signal. Therefore switch 4
When a pulse P with a short time width is generated on the output line of the flip-flop due to static electricity or the like as shown in FIG. 5.
However, this signal P' is not read into flip-flop 5 unless it occurs simultaneously with clock pulse ₂ . Therefore, even if a pulse P with a short time width is generated on the output line of the switch 4, the output of the flip-flop 5 does not change, and the latch circuit 11 and the NOR circuit 13 are kept in a separated state.

When the switch 4 is closed in the above state, the operation output S is as shown in FIG. 5c.
becomes “1”, and the NOR circuit 1 in the latch circuit 11
It is inverted to “0” through 2. The operation output of the switch 4 has a sufficiently long time width compared to the period of the clock pulse ₂ , and is therefore read into the flip-flop 5 in synchronization with the clock pulse ₂ . Therefore, the output of the flip-flop 5 is inverted from "1" to "0" as shown in FIG.
It is sent to the processing circuit as a switch signal and is also input to the latch circuit 11. When the signal applied from the flip-flop 5 becomes "0", the output of the NOR circuit 13 becomes "1" as shown in FIG. hold. Therefore, if chattering occurs when switch 4 is closed, this chattering will be caused by clock pulse _2.
If the signal is completed before the rise of , the output of the flip-flop 5 can be kept in the "0" signal state regardless of the chattering as explained in FIG. 1 above.

In the above embodiment, the latch circuit 11 is constructed using NOR circuits 12 and 13, but it is of course possible to use other logic circuits such as a NAND circuit.

As described above, according to the present invention, the latch circuit to which the switch operation output is applied is always operated as an inverter, and when the switch operation signal is detected, the latch circuit is configured to perform the normal latch operation. Therefore, the influence of chattering can be prevented with the number of elements not much different from that of the conventional circuit, and malfunctions due to the influence of pulses caused by static electricity or the like can be reliably prevented.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a conventional switch circuit, FIGS. 2 and 3 are timing charts for explaining the operation of FIG. 1, and FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention. FIG. 5 is a timing chart for explaining the operation of the same embodiment. 4...Switch, 5...Flip-flop, 11...
Latch circuit, 12, 13...NOR circuit.

Claims (1)

[Scope of Claims] 1. First and second NOR circuits each having its own output signal given to the input terminal of another NOR circuit, and a switch operation signal being applied to the input terminal of the first NOR circuit. a data input terminal to which an output signal of the first NOR circuit is supplied, and a clock input terminal to which a first clock signal of a predetermined period is supplied; a flip-flop circuit that reads the output signal of the first NOR circuit applied to the data input terminal in synchronization with a first clock signal and outputs it as a switch operation detection signal from the data output terminal; A switch circuit configured to supply a switch operation detection signal and a second clock signal having the same cycle and a different phase as the first clock signal to the input terminal of the second NOR circuit.