JPH0113799B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a noise absorption method, and more specifically, to a noise absorption method that occurs in signals indicating the status of each communication channel in a time division multiplex communication method such as a PCM communication method. .

Prior Art and Problems In the PCM communication system, signals indicating the status of each communication channel (for example, idle status) are usually transmitted in batches at specific time slots. However, when a time division multiplexed line such as a PCM line is accommodated in a space division switch, the time division multiplexed signal (PCM signal) transmitted through the line is separated into each communication channel and decoded (analog signal At the same time, signals indicating the status of each communication channel are separated for each communication channel, converted into a form suitable for the exchange, and inputted from the corresponding terminals.

However, when a time division multiplexed signal such as a PCM signal is accommodated in a time division digital switch, the time division multiplexed signal can be input as is.
There is no need to separate each communication channel, and signals indicating the status of each communication channel can also be inputted while being multiplexed.

The signals indicating the status of each communication channel described above are affected by noise, and if received by mistake, there is a risk that the switching equipment or the like may malfunction, so it is necessary to absorb the noise. In conventional space-division type exchanges, noise absorption was performed after the above-mentioned signal was separated into each channel. However, when a time division multiplexed line is accommodated in a time division exchange, there is no need to separate the signals, so it would be advantageous if noise absorption processing could be performed on the signals while they remain multiplexed. but,
Conventionally, noise absorption of the signals indicating the status of each communication channel has not been carried out without separating such signals and in a multiplexed state.

Purpose of the Invention The present invention provides an efficient way to absorb noise in signals indicating the status of each channel without separating time-division multiplexed signals into each channel, and to prevent malfunctions caused by noise. The purpose of this study is to provide a noise absorption method that provides a comprehensive noise absorption method.

Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an outline of the configuration of an embodiment of the present invention. In the figure, L is a line carrying a time division multiplexed signal, for example a PCM signal, DT is a digital terminal that receives the PCM signal,
NA is a noise absorption circuit, I is an inserter, SI is a signal input line, SO is a signal output line, TDS is a time division switch, and DNW is its time division digital channel network device.

FIG. 2 shows the structure of the PCM signal transmitted by line L in this embodiment. This signal has a multi-frame structure as shown in FIG. 2a, and one multi-frame MF consists of 16 frames F ₀ to F ₁₅ . FIG. 2b shows details of the configuration of one frame 1F, and shows the details of the structure of one frame 1F.
One frame has 32 frames each as shown on 1F.
Time slots TS ₀ to TS ₃₁ are set.
8 for each time slot TS ₀ to _{TS 31}
Bits are assigned.

In each frame, its time slot T
- 8 bits of S ₀ are used for synchronization signals, and 8 bits of time slot TS ₁₆ are used for the status of 30 channels assigned to time slots TS ₁ to TS ₁₅ and TS ₁₇ to _{TS 31} . Assigned to signals indicating And one multiframe
In MF, the time slot of frame F ₁
A specific position of the 8 bits in TS ₁₆ , for example, bit b ₁ in the first position, is used as a signal indicating the state of channel 1 (time slot TS ₁ ), and another specific position, for example, bit b in the fifth position, is used as a signal indicating the state of channel 1 (time slot TS 1 ). ₅ to channel 16
(time slot TS ₁₇ ) as a signal indicating the state of channel 2 and channel 17 to channel 1 for frames F ₂ to F ₁₅ , respectively.
5. Assign the signal of channel 30. Therefore, one multiframe (including frames F ₀ to F ₁₅ ) can include one signal indicating the status of all channels (channel 1 to channel 30). Here, the state of a channel refers to whether the channel is occupied by the originating subscriber or whether it is idle, such as whether the channel is occupied, or whether the originating subscriber who acquired the channel is off-hook or on-hook. When the originating subscriber who went off-hook acquires the channel, the signal indicating the state of the channel, that is, the bit at the specific position becomes 0, for example, and the originating subscriber goes on-hooked, or It becomes "1" when it is not captured.

In FIG. 1, when a bipolar PCM signal with a multi-frame configuration is input to the digital terminal DT from the line L, the digital terminal DT extracts a clock from the input signal and uses this clock to output the bipolar signal. The signal is converted into a unipolar signal suitable for processing by the switch, and sent to the time division switch TDS via inserter I.
send to In the digital terminal DT, the signals indicating the channel status described above are extracted and separated, and only these signals are sent to the noise absorption circuit NA via the signal input line SI to undergo necessary processing such as noise absorption. , the PCM signal is sent to the inserter I via the signal output line SO, and inserted into the corresponding position in the inserter I. In this way, the PCM signal has a noise-absorbed signal and is input to the time division switch TDS.

FIG. 3 is a diagram showing an example of the configuration of the noise absorption circuit NA in FIG. 1. In the figure, M-
CONT is a memory control circuit, D is an input signal distributor, MEM is a memory, A-A, A-B, A-
C, A-D, A-E, A-F are a plurality of input signal storage areas set in the memory MEM, A-
Similarly, H indicates one output signal storage area.
DC is a signal output circuit, _R1 is a register, A, B,
C, D, E, F, and H each indicate a 1-bit cell, AN ₁ , AN ₂ , and AN ₃ are AND gates, OR is an OR gate, and R ₂ is an output register. Lines SI and SO are the same as the signal input line SI and signal input line SO shown in FIG. 1, respectively.

As already explained in FIG. ₁ , in each multiframe, the time and
Slot TS ₁₆ contains signals indicating the status of channels 1 and 16 (1 bit each), and the frame
F ₂ includes signals of channels 2, 17, etc., and one multi-frame MF (frames F ₀ to F ₁₅
) contains signals indicating the status of all channels, and the digital terminal DT separates these signals from other signals (such as call signals).
Output to signal input line SI.

The above signal is input to the noise absorption circuit NA via the signal input line SI, as shown in FIGS. 1 and 2.

As is clear from the above, while receiving one multiframe MF, all channels (channel 1
- channel 30) are input into the noise absorption circuit NA from the signal input line SI in a fixed order. Memory control circuit M-
CONT controls the distributor D and the memory MEM to transfer the signal indicating the state of the channel included in the first multiframe (MF ₁ ) to one input signal storage area, for example, A-A, in accordance with the channel. Write to position. Note that the above-mentioned signal of the subsequent second multi-frame (MF ₂ ) is similarly written to the next input signal storage area AB. In this way, each time a new multi-frame is received, the above signals are sequentially written into the respective next input signal storage areas AC, AD to AF. After writing to storage areas A-F, the newly received multi-frame signal is overwritten in storage areas A-A where the signal was first written, and in this way the above signal arrives. In turn, data is sequentially and cyclically written into each channel position of the plurality of input signal storage areas A-A to AF. Therefore, the above-mentioned signals carried by the latest six multi-frames are always written in the input signal storage areas A-A to A-F. From the signal input SI, the time and time of a certain frame are
After the above signal is input at slot TS ₁₆ , it is not necessary to write the input signal to the memory MEM until time slot TS ₁₆ of the next frame. Do this. That is, a signal indicating the state of one specific channel (for example, channel 1) into which a signal has been inputted from input signal storage areas A-A to A-F (a bit signal indicating "1" or "0") is read out and stored in register R. Store in corresponding cells A to F of ₁ .

If channel 1 is in an on-hook state and six or more consecutive "0"s have already been received as the above signal, the contents and outputs of cells A to F of register _R1 will all be "0" in the above case. Therefore, the output of AND gate AN ₁ is “0” AN ₂
The output of AND gate AN 2 becomes “1”, and the AND gate AN ₂ output “1” becomes “0”.
AN ₃ becomes non-conductive and outputs "0". Therefore, the OR gate OR receives two inputs "0" and outputs "0", which is temporarily stored in the output register _R2 . This connects the signal output line SO at a predetermined timing.
As shown in FIG.
Channel 1 of the time division multiplexed signal (PCM signal) outputting from the digital terminal DT via
is inserted at that temporal position as a signal indicating the state of.

In addition, at this time, the signal output circuit DC output “0”,
In other words, the output of the OR gate is the memory MEM
The channel 1 status signal is stored in the output signal storage areas A to H at the storage position of the channel 1 status signal.

Continuing to receive time-division multiplexed signals from the other station, each time a multi-frame MF is received, the memory
One input signal storage area of the MEM is rewritten, and for example, suppose that the latest signal indicating the state of channel 1 changes from "0" to "1". At this time, if, for example, the signal indicating the state of channel 1 stored in input signal storage area AA becomes "1" and the others are "0", the buffer register R ₁ is stored in the same manner as above. "1", "0" to "0", "0" are stored in cells A, B, ~F, and H, so the output of AND gate _AN1 is "0" and
Unlike the above, the output of gate AN ₂ is “0”,
Negate “1” of output “0” of AND gate AN ₂
As a result, the AND gate AN ₃ becomes conductive, and the previous output signal "0" stored in the output signal storage area A-H is outputted via the cell H and temporarily stored in the output register R ₂ . Similarly, it is output to the signal output line SO at a predetermined timing.

When six multi-frames in which the signal indicating the state of channel 1 is "1" are successively received, all the above signals stored in each of input signal storage areas A-A to A-F are "1". Therefore, when these signals are read into register _R1 , the contents of each cell A to F become "1", and the contents of cell H are the contents of the previously sent signal, that is, "0".
or “1”. The output of AND gate AN ₁ is "1", and the output of AND gate AN ₂ is "0", as in the case above where the contents of cells A to F are mixed with "0" and "1". Become. Therefore, AND gate AN ₃ outputs “0” from AND gate AN ₂ .
It becomes conductive due to the negation of "1", and outputs the previously sent signal "0" or "1", which is the content of cell H. However, in this case, the output of AND gate AN ₁ is "1", so AND gate AN ₃
Regardless of whether the output is “0” or “1”, the OR gate
The output of OR becomes “1” and this is sent to the output register.
Store in R ₂ and store in memory areas A-H. Buffer register R ₂ at predetermined timing
Sending the signal from the output signal line SO to the output signal line SO is the same as described above.

FIG. 4 is a diagram showing the input and output states of a signal indicating the state of one channel to the noise absorption circuit NA, and in the figure, SI indicates the bit "0" or "1" of the input signal. ”, and SO indicates bit “0” or “1” of the output signal. As can be easily understood from the above explanation and FIG. ), one "0" is output as an output signal as shown in SO b of FIG. 4, and if "0" is received subsequently, "0" is outputted. Also, input signal “0” becomes “1”
When it changes to the memory area A of the memory MEM.
b to c while “0” and “1” are mixed in the signal indicating the state of the channel stored in A to A-F;
Since the AND gate AN ₃ becomes conductive, the previous signal (“0” in this case) stored in the output signal storage area A-H is sent out (b in Figure 2 SO).
~c).

Assume that part of the signal "0" indicating the state of this channel changes to "1" due to noise. In this embodiment, unless six or more signals change continuously, that is, the buffer register R ₁
As long as “0” and “1” are mixed in the signals stored in cells A to F, AND gate AN ₃ will be conductive, including when the signal changes from “0” to “1” due to noise. , and the previous signal stored in cell H of register _R1 , ie, "0", is sent out. 6 consecutive signals “0”
Only after receiving this signal does the signal sent to the output signal line OS change.

If 6 "1"s are continuously received from the signal input line SI as a signal indicating the status of one channel (if it becomes d), "1" is output as shown in e of SO in Figure 4. It outputs it as a signal, and if it subsequently receives a "1", it then outputs a "1".

Also, when the input signal changes from "1" to "0", the input signal storage area A-A~ of the memory MEM is
The signal indicating the state of the channel stored in A-F contains "0" and "1", and while they are mixed, AND gate _AN3 is conductive, so the output signal storage area A-H The previous signal (“0” in this case) stored in is sent out.

Even if a part of the signal “1” indicating the state of this channel changes to “0” due to noise, as long as six or more signals do not change to “1” in succession as described above, the register R The contents of cells A to F of ₁ contain a mixture of “0” and “1”, and the AND gate
AN ₃ becomes conductive, and the previous signal "1" stored in the output signal storage area A-H is sent out through the cell H and the OR gate OR.

In the above embodiment, even if a continuous signal of 5 bits or less indicating the channel status is affected by noise, it can be absorbed and output, but in the case of absorbing short-term noise. , the input signal storage area (A
-A to A-F).

Although one embodiment of the present invention has been described above,
The present invention is not limited to the above-described embodiments, and various modifications can be made within the technical scope thereof.

Effects of the Invention Since the present invention is configured as described above, P
- In time division multiplex communication systems such as CM communication systems, it absorbs noise added to signals indicating the status of each channel in a time division multiplexed state without separating the time division multiplexed signals into each channel. death,
This has the effect of providing an efficient noise absorption method that repairs disturbances caused by noise and prevents malfunctions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a time division multiplexed signal handled in the embodiment of FIG. 1, and FIG. 3 is a diagram similar to that shown in FIG. FIG. 4 is a diagram showing the connection configuration of one example of the noise absorption circuit in the embodiment shown in FIG. L...Transmission line for time division multiplexed signals, DT...
Digital terminal, NA...noise absorption circuit, I...inserter, TDS...time division switch,
DNW...Time division digital communication network equipment, M-
CONT...Memory control circuit, MEM...Memory,
A-A, A-B, A-C, A-D, A-E, A-
F...Input signal storage area, A-H...Output signal storage area, D...Distributor, DC...Signal output circuit, _R1 ...Register, A, B, C, D, E, F,
H...Cell of register _R1 , _AN1 , _AN2 , _AN3 ...
…and gate, OR…or gate, R ₂ …
...output register.

Claims (1)

[Claims] 1. Signals indicating the status of all channels are assigned to specific time slots of frames constituting a multiframe, and one multiframe includes one channel-compatible signal indicating the status of each channel. Receives PCM signals with multi-frame configuration and
A digital terminal extracts and separates a signal indicating the state of each channel from the PCM signal and inputs the signal to the noise absorption circuit, and an inserter that inserts the output of the noise absorption circuit into the PCM signal, and the noise absorption circuit includes a plurality of a memory having input signal storage areas and one output signal storage area; a channel-corresponding signal indicating the state of each channel is stored in one input signal storage area for each multi-frame reception; In the order of arrival, the signals of the corresponding channels are sequentially and cyclically written to the positions corresponding to the respective channels of the plurality of input signal storage areas, and each time a newly received signal is written, the signal of the corresponding channel is written to the position corresponding to each channel of the plurality of input signal storage areas. and a signal output circuit that creates and outputs an output signal with noise absorbed based on the signals corresponding to the channels read from the plurality of input signal storage areas. The memory control device writes the output signal to a channel-corresponding position of the output signal storage area of the memory each time the output signal is output, and the signal output circuit writes the output signal to a channel-corresponding position of the output signal storage area of the memory, and the signal output circuit writes the output signal to a channel-corresponding position of the output signal storage area of the memory. The read signals are all “0” or all “1”
When , "0" or "1" is sent respectively, and when "0" and "1" are mixed, the previous signal stored in the output signal storage area of the memory is sent to the inserter as an output signal, A noise absorption method characterized by inserting the output signal at a temporal position of a signal indicating a channel state corresponding to the output signal.