JPH0114748B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a solid-state image sensor drive circuit that employs an interline transfer method.

Conventional technology Regarding the interline transfer method,
It is disclosed in Publication No. 3067.

FIG. 2 is an explanatory diagram of its principle, showing a large number of light receiving sections 92 arranged in a matrix on a common semiconductor substrate 91, each consisting of one pixel.
, vertical transfer registers 93 extending in the vertical direction and provided in the same number as the number of light receiving sections 92 in the horizontal scanning direction, that is, the number of horizontal picture elements, and a horizontal transfer register for transferring accumulated charges (carriers) to the output terminal side. 94 constitutes this solid-state image pickup body 100.

In order to obtain an image output from this solid-state image sensor 100, first, a minority carrier based on the optical information accumulated in each light receiving section 92 is once transferred to the vertical transfer register 92 for each vertical line (parallel transfer), and then for each vertical line. The transfer register 93 sequentially transfers the stored carriers in the vertical direction (serial transfer), and the stored carriers are read out every horizontal scan through the horizontal transfer register 94. In this way, the desired imaging output can be obtained at the output terminal of the horizontal transfer register 94.

Here, since the vertical columns of light receiving sections 92 and the vertical transfer registers 93 are arranged alternately, this transfer method is generally called an interline transfer method.

Note that the plurality of arrows shown in FIG. 2 indicate the transfer direction of the carrier, but if an interlaced scanning method is employed, the broken line arrows will indicate transfer in a certain even field. Therefore, only solid line arrows are transferred in odd-numbered fields.

In the solid-state image sensor shown in FIG. 2, the odd-numbered picture elements in the horizontal scanning direction are designated as 92a, and the even-numbered picture elements are designated as 92b. Further, odd-numbered horizontal scanning lines are indicated by 95a, and even-numbered ones are indicated by 95b. 96 indicates a gate region. This is each picture element 9
This register is provided for reading the carrier stored in the register 2 and transferring the read carrier to the vertical transfer register 93 when desired.
In this case, the carrier readout direction is a direction perpendicular to the transfer direction a, that is, the horizontal scanning direction.

Now, in the case of a video camera using the interline transfer method, the charge accumulation time can be selected by controlling the period of the readout pulse that reads out the charge of the photodiode that constitutes the light receiving section used as a picture element to the vertical transfer register. It is possible. This read pulse is given at the high level and middle level of the ternary pulse applied to the vertical transfer electrodes, as shown in FIG.

The vertical transfer register has a multiphase structure as shown in FIG. 4, and one electrode is arranged for each register unit (four phases in the figure). The transfer pulse of the vertical transfer register is a multiphase pulse (four phases in the figure) given at the middle level and roll level of the ternary pulse. In a normal video camera, the charge accumulation time is set to either a field period or a frame period. Each of these two accumulation modes has its own advantages and disadvantages. Frame mode has a higher vertical resolution, but the longer accumulation time causes noticeable blurring in video images, while field mode has less blurring in the vertical direction, but The resolution degrades to about 3/4 of that in frame mode. Therefore, it is preferable to use field mode when taking still images, and use field mode when taking moving images, and charge-coupled devices are used as interline transfer solid-state image sensors.
Since this selection is possible when a CCD is used, an accumulation mode changeover switch is often provided in the vertical transfer register drive circuit. Vertical transfer register driving pulse waveforms by the mode switching circuit are shown in FIGS. 5a and 5b.

φ _V1 to φ _V4 are applied to the V1 to V4 electrodes, respectively. As shown in Figure 4, two electrodes correspond to one cell,
Charge read pulses at the V _H -V _M level exist only at φ _V2 and φ _V4 . Read pulse and V _M - V _L
The vertical transfer pulses at the level of are synthesized in the next stage driver section, which is separately created using a logic circuit. As shown in Figure 5a, in the frame accumulation mode, the charge of the photodiode corresponding to the V2 electrode (odd rows) and the charge of the photodiode corresponding to the V4 electrode (even rows) are alternated every vertical period. On the other hand, in the field accumulation mode, as shown in FIG. 5b, odd rows,
Even-numbered rows are read out every field period.

Problems to be Solved by the Invention It has been confirmed that the characteristics of CCD elements include afterimage characteristics and the dependence of dark current characteristics on the readout pulse level.Regardless of the charge accumulation mode, when the readout pulse level is increased, the afterimage characteristics improve and dark current characteristics become better. The current characteristics deteriorate, and when the read pulse level is lowered, the dark current characteristics become better and the afterimage characteristics deteriorate. These are comparative values, but as mentioned above, the usage differs depending on the storage mode, and the priority characteristics differ depending on the application. It seems that the circuit configuration is insufficiently suited to the actual situation.

Means for Solving the Problem: A two-dimensionally arranged array of light receiving sections, a vertical transfer register and a horizontal transfer register for guiding the charges generated in the light receiving sections to an output in time series by a transfer means; Located across the transfer gate section and vertical transfer register that sends charge from the light receiving section to the vertical transfer register, high level transfers charge to the vertical transfer register, and middle and low levels transfer charge within the vertical transfer register. An accumulation mode that is applied to devices equipped with electrodes for applying ternary pulses that perform 3-value pulses, and allows the accumulation time of the light receiving section to be set to the field period or frame period by controlling the application period of the high level of the 3-value pulses. The gist of the present invention is to provide a potential changing means which has a switching means and works in conjunction with the accumulation mode switching means to lower the high level potential of the ternary pulse in the frame mode than in the field mode.

Effect The readout pulse level is high in field accumulation (hereinafter abbreviated as FI) mode, which improves the afterimage characteristics.
Since the level of the read pulse is low in the FR (abbreviated as FR) mode, the S/N ratio caused by the dark current of the element is reduced.

Embodiment FIG. 1 shows an embodiment according to the present invention. Figure 1 shows the driver part of the vertical register drive circuit.
Three types of power sources are applied as voltages that determine each potential of the ternary pulse. Of these, 37 are low level
V _L power supply line, 33 is the middle level V _M power supply line, V _CC is the high level V _H supply line 2
This is a power supply line for applying voltage to 9. As a circuit input, a vertical transfer pulse φ _V is applied to 35 and a charge read pulse Δ _V is applied to 27 as pulses having opposite polarity to the circuit output. _φV is input to the inverting driver 36. The negative power supply of the inverting driver 36 is connected to the V _L power supply line 37, and the positive power supply is connected to the cathode side of the clamp diode 39 and, at the same time, to the output line of the _ΔV inverting driver 38 via the coupling capacitor 15. The anode side of the clamp diode 39 is connected to the V _M power supply line 33. The power line 29 of the _ΔV inverting driver 28 is supplied by an emitter follower 30, and the input potential of the emitter follower 30 is a voltage obtained by dividing Vc.c. by _R1 and _R2 + _R3 . The midpoint between R ₂ and R ₃ is connected to a part of the mode selector switch 32, and the accumulation mode is selected.
When set to FR, _R3 is shot to GND. Nao 4
Reference numeral 1 denotes a synchronous circuit in which a mode changeover switch 32 switches the period of the charge readout pulse _ΔV corresponding to the FI mode and the FR mode. Therefore, the input potential 31 is
In FI mode, V = V _CC (R ₂ + R ₃ )/(R ₁ + R ₂ + R ₃ ),
Also, in FR mode, V=V _CC R ₂ /(R ₁ +R ₂ ).
The emitter follower 30 has a configuration in which the output potential and the input potential are equal, and the output pulse of the _ΔV inverting driver 28 has an amplitude between V _DD and V _SS .
The peak value of the output pulse _ΔV becomes equal to the input potential 31. The output pulse _ΔV is clamped to the middle level V _M by the capacitor 40 and the diode 39 and connected to the power supply line of the φ _V inverting driver 36. Therefore, the output waveform φ _V 38 becomes the V _H voltage determined by the input potential 31 when the read pulse Δ _V exists, and becomes a ternary pulse having an amplitude between the V _M and V _L potentials at other times. Here, V _H is in FI mode V _H = V _M + V _CC (R ₂ + R ₃ ) / R ₁ + R ₂ + R ₃ ) - V _F In FR mode V _H = V _M + V _CC R ₂ / (R ₁ + R ₂ ) -V _F (V _F : diode drop voltage), and the read level will switch in conjunction with the storage mode switch. Therefore, the readout pulse is set high during field accumulation, mainly for moving image observation, to give priority to low afterimage characteristics, and the readout pulse is set low during frame accumulation mode, mainly used for still image observation, to reduce S/N. It is possible to switch the characteristics according to the application.

Effects of the Invention The level of the readout pulse can be increased to improve afterimage characteristics in the field accumulation mode, which is mainly used for observing moving images, and the level of the readout pulse can be lowered in the frame accumulation mode, which is mainly used for observing still images. This makes it possible to automatically switch the characteristics according to the application, which reduces the S/N ratio caused by the dark current of the device.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a principle diagram of the interline shift method according to the present invention, Figure 3 is a principle diagram showing the structure of a unit cell and electrode according to the present invention, Figure 4 is a diagram explaining the configuration of a vertical register, and Figure 5 a. , b are waveform diagrams of vertical register drive pulses. 30, 31... Potential changing means, 32... Accumulation mode switching means.

Claims (1)

[Scope of Claims] 1. A two-dimensionally arranged light receiving array, a vertical transfer register and a horizontal transfer register for guiding the charges generated in the light receiving section to an output in time series by a transfer means, and the light receiving array. a transfer gate section that sends charge from the section to the vertical transfer register;
A ternary value located across the transfer gate section and the vertical transfer register, which transfers charge to the vertical transfer register when the high level is applied, and transfers the charge within the vertical transfer register when the middle level and the low level are applied. A solid-state image sensing device driving circuit comprising an electrode for applying a pulse, the accumulation time of the light receiving section being adjusted to a field period or a frame period by controlling a high level application period of the three-valued pulse. A solid state device characterized in that it has an accumulation mode switching means that can be set to 1, and further includes a potential changing means that works in conjunction with the accumulation mode switching means and lowers the high level potential of the three-valued pulse in the frame mode than in the field mode. Image sensor drive circuit.