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JPH0115153B2 - - Google Patents
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JPH0115153B2 - - Google Patents

Info

Publication number
JPH0115153B2
JPH0115153B2 JP56146866A JP14686681A JPH0115153B2 JP H0115153 B2 JPH0115153 B2 JP H0115153B2 JP 56146866 A JP56146866 A JP 56146866A JP 14686681 A JP14686681 A JP 14686681A JP H0115153 B2 JPH0115153 B2 JP H0115153B2
Authority
JP
Japan
Prior art keywords
aluminum
circuit
copper
foil
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56146866A
Other languages
Japanese (ja)
Other versions
JPS5848432A (en
Inventor
Shinichiro Asai
Kazuo Kato
Tatsuo Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP56146866A priority Critical patent/JPS5848432A/en
Publication of JPS5848432A publication Critical patent/JPS5848432A/en
Publication of JPH0115153B2 publication Critical patent/JPH0115153B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07531Techniques
    • H10W72/07532Compression bonding, e.g. thermocompression bonding
    • H10W72/07533Ultrasonic bonding, e.g. thermosonic bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/352Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Manufacturing Of Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、繁雑な作業の必要なしにエツチング
のみによつて、アルミニウムリード線による半導
体と回路との信頼性の高いワイヤーボンデイング
を可能とした混成集積回路の製法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hybrid integrated circuit that enables highly reliable wire bonding between a semiconductor and a circuit using aluminum lead wires only by etching without the need for complicated operations.

従来、混成集積回路はセラミツクやガラス基板
上に抵抗体やトランジスターの如き回路部品を適
宜付着したもの、あるいはアルミニウムまたは鉄
基板上に絶縁層を設け、この上に回路を組み込む
方式が一般的である。
Conventionally, hybrid integrated circuits have generally been made by attaching circuit components such as resistors and transistors to a ceramic or glass substrate, or by providing an insulating layer on an aluminum or iron substrate and incorporating a circuit on top of this. .

これら基板の上には、半田付による半導体のダ
イボンデイング、外部への端子接続、チツプコン
デンサー等チツプ部品の取付けがなされ、また半
導体と回路との接続は、金線又はアルミニウム線
によるワイヤーボンデイングによりなされてい
る。
On these boards, die bonding of semiconductors is done by soldering, terminal connections to the outside, and chip parts such as chip capacitors are attached, and connections between semiconductors and circuits are made by wire bonding with gold or aluminum wires. ing.

アルミニウムワイヤーの接続については、貴金
属メツキによる処理、ニツケルメツキ(特公昭52
−3461号)、アルミニウム蒸着メツキ(特開昭51
−28662号)及び金属ペレツトの接着(特公昭45
−37110号)、等各種の提案がある。しかしながら
メツキによる場合は、メツキ設備を必要とするほ
かにメツキ表面の精度、層厚みを管理することが
必要である。また、金属ペレツトの接着の場合
は、接着個数が半導体のダイボンデイング数より
多く、これらの作業はきわめて煩雑な作業であ
る。
For connecting aluminum wires, use precious metal plating or nickel plating (special public
-3461), aluminum evaporation plating (Japanese Patent Application Laid-open No. 1973)
-28662) and adhesion of metal pellets (Special Publication No. 1973)
-37110), and various other proposals. However, in the case of plating, in addition to requiring plating equipment, it is also necessary to control the accuracy of the plating surface and the layer thickness. Furthermore, in the case of bonding metal pellets, the number of bonded pellets is greater than the number of semiconductor die bondings, and these operations are extremely complicated.

また、高分子樹脂絶縁層を有する銅箔回路で
は、絶縁層が低ヤング率であるため、超音波振動
によりワイヤーボンデイングを行うといわゆる超
音波がにげる現象があり十分なボンデイングが不
可能である。また、貴金属メツキやニツケルメツ
キ法では、ボンデイング表面の精度が厳密に要求
されると共にその超音波振動ボンデイング条件も
狭い範囲で操作しなければならなかつた。
Furthermore, in a copper foil circuit having a polymer resin insulating layer, since the insulating layer has a low Young's modulus, when wire bonding is performed using ultrasonic vibration, there is a phenomenon in which so-called ultrasonic waves are lost, making it impossible to perform sufficient bonding. Furthermore, in the noble metal plating and nickel plating methods, precision of the bonding surface is strictly required, and the ultrasonic vibration bonding conditions must also be operated within a narrow range.

本発明は、かかる欠点を解決したものであり、
金属基板に絶縁層、アルミニウム―銅クラツド箔
を順に積層して一体化してなる積層物のアルミニ
ウム―銅クラツド箔をアルミニウムと銅の両者を
エツチングできる塩化鉄等でエツチングして配線
回路を形成させ、しかもアルカリ又は過硫酸アン
モニウムによりエツチングしてアルミニウム回路
や銅回路を露出させて、これに半田を介して銅回
路と半導体や他部材とを積層し、かつ半導体とア
ルミニウム回路とをアルミニウムリード線を用い
超音波によつて固着するようした混成集積回路の
製法を提供しようとするものである。
The present invention solves these drawbacks,
A wiring circuit is formed by etching the aluminum-copper clad foil, which is a laminate made by sequentially laminating an insulating layer and an aluminum-copper clad foil on a metal substrate, with iron chloride, etc., which can etch both aluminum and copper. In addition, the aluminum circuit and copper circuit are exposed by etching with alkali or ammonium persulfate, and then the copper circuit, semiconductor, and other components are laminated via solder, and the semiconductor and aluminum circuit are bonded using aluminum lead wires. It is an object of the present invention to provide a method for manufacturing a hybrid integrated circuit that is fixed by sound waves.

すなわち、本発明は、金属基板に絶縁物層、ア
ルミニウム(10〜100μ)―銅クラツド箔(以下
アルミニウム―銅クラツド箔という)とを順に積
層して一体化してなる積層物の前記アルミニウム
―銅クラツド箔をエツチングして配線回路を形成
させると共にさらにエツチングしてアルミニウム
回路とを形成させ次いで該アルミニウム回路と半
導体とを超音波振動法によりアルミニウムリード
線で固着させることを特徴とする。
That is, the present invention provides the aluminum-copper cladding of a laminate which is formed by sequentially laminating and integrating an insulating layer and an aluminum (10 to 100μ)-copper cladding foil (hereinafter referred to as aluminum-copper cladding foil) on a metal substrate. The method is characterized in that the foil is etched to form a wiring circuit, further etched to form an aluminum circuit, and then the aluminum circuit and semiconductor are fixed by an aluminum lead wire using an ultrasonic vibration method.

以下図面により本発明の実施例を詳しく説明す
るが、第1〜2図は実施例に用いる積層物、第3
〜4図は実施例の断面図、第5図は超音波出力と
引張強度との関係図である。
Examples of the present invention will be explained in detail below with reference to the drawings.
4 are cross-sectional views of examples, and FIG. 5 is a diagram showing the relationship between ultrasonic output and tensile strength.

まず第1図に示すように本発明に用いる積層物
は、金属基板1の上に絶縁物層2を積層し、絶縁
物層2の面にアルミニウム箔3がくるようにアル
ミニウム3と銅4とのアルミニウム―銅クラツド
箔8が積層したものであり、また、第2図は、第
1図のものと逆に構成したもので絶縁物層2の面
に銅箔4がくるようにアルミニウム―銅クラツド
箔8が積層したものである。
First, as shown in FIG. 1, in the laminate used in the present invention, an insulating layer 2 is laminated on a metal substrate 1, and aluminum 3 and copper 4 are stacked so that the aluminum foil 3 is placed on the surface of the insulating layer 2. The aluminum-copper clad foil 8 shown in FIG. The cladding foil 8 is laminated.

次に、このアルミニウム―銅クラツド箔8は両
者に対してエツチング可能な塩化鉄等でエツチン
グして配線回路を形成させる。次いで第2図に示
す積層物を前記の方法でエツチングし、さらに第
3図に示すように金属基板1、絶縁物層2、及び
アルミニウム回路3′の一部をアルカリエツチン
グして銅回路4′を露出させて、該銅回路4′上に
半田7を介して半導体やチツプ低抗体等を載置し
た後、半導体6とアルミニウム回路3′とを超音
波振動法によりアルミニウムリード線5により固
着する。また第1図に示す積層物を前記の方法で
エツチングしさらに第4図に示すように、金属基
板1、絶縁物層2、及び銅回路4の一部を過硫酸
アンモニウム等でエツチングしてワイヤボンデイ
ング部となるアルミニウム回路3′を露出せしめ、
銅回路4′上には、第3図同様に半田7を介して
半導体やチツプ低抗体等を載置し、半導体6とア
ルミニウム回路3′とを超音波振動法によりアル
ミニウムリード線5により接続する。
Next, this aluminum-copper clad foil 8 is etched with etchingable iron chloride or the like to form a wiring circuit. Next, the laminate shown in FIG. 2 is etched by the method described above, and as shown in FIG. 3, a part of the metal substrate 1, insulator layer 2, and aluminum circuit 3' is alkali-etched to form a copper circuit 4'. After exposing the copper circuit 4' and placing a semiconductor, a chip low antibody, etc. on the copper circuit 4' via the solder 7, the semiconductor 6 and the aluminum circuit 3' are fixed by an aluminum lead wire 5 using an ultrasonic vibration method. . Further, the laminate shown in FIG. 1 is etched by the above-described method, and further, as shown in FIG. 4, a part of the metal substrate 1, insulator layer 2, and copper circuit 4 is etched with ammonium persulfate, etc., and then wire bonded. exposing the aluminum circuit 3' that will become the
A semiconductor, a chip low antibody, etc. are placed on the copper circuit 4' via solder 7 as in FIG. 3, and the semiconductor 6 and the aluminum circuit 3' are connected by the aluminum lead wire 5 using the ultrasonic vibration method. .

本発明に用いる金属基板1としては、良熱伝導
性を持つ0.5〜3.0mmのアルミニウム、鉄等が用い
られ、絶縁物層2としては、各種セラミツクス、
無機粉体を含有する高分子樹脂絶縁層、ガラス繊
維を含有する高分子樹脂絶縁層、及び耐熱性高分
子樹脂絶縁層を用い、その肉厚は20μ以上であ
る。前記無機粉体としては、アルミナ、ベリリ
ヤ、ボロンナイトライド、マグネシア、シリカ等
が好ましく、高分子樹脂としては、エポキシ樹
脂、フエノール樹脂、ポリイミド樹脂等が好まし
い。また、絶縁物層2としては、高分子樹脂を含
有する絶縁層が好ましく、さらに、アルミニウム
―銅クラツド箔8のアルミニウムは10〜100μで
あり、アルミニウムが10μ未満では太いアルミニ
ウムリード線の固着ができず、しかも接着力が弱
いため信頼性に劣る。また100μを超えても何ん
ら差支えないが、コスト高となるだけである。銅
は0.1〜100μの厚さが好ましい。さらにアルミニ
ウムに銅をメツキした箔でもよい。又アルミニウ
ムに異種の金属、例えばニツケル、銅を順にメツ
キすることもできる。
The metal substrate 1 used in the present invention is made of aluminum, iron, etc. with a thickness of 0.5 to 3.0 mm and has good thermal conductivity, and the insulating layer 2 is made of various ceramics,
A polymer resin insulation layer containing inorganic powder, a polymer resin insulation layer containing glass fiber, and a heat-resistant polymer resin insulation layer are used, and the thickness thereof is 20 μm or more. The inorganic powder is preferably alumina, beryllia, boron nitride, magnesia, silica, etc., and the polymer resin is preferably epoxy resin, phenolic resin, polyimide resin, etc. Further, as the insulating layer 2, an insulating layer containing a polymeric resin is preferable, and furthermore, the aluminum of the aluminum-copper clad foil 8 has a thickness of 10 to 100μ, and if the aluminum is less than 10μ, thick aluminum lead wires cannot be fixed. Furthermore, the adhesive strength is weak, resulting in poor reliability. Moreover, there is no problem if the thickness exceeds 100μ, but it only increases the cost. Copper preferably has a thickness of 0.1 to 100μ. Furthermore, a foil made of aluminum plated with copper may be used. It is also possible to sequentially plate aluminum with different metals, such as nickel and copper.

次に、2mm厚のアルミニウム板に50μのアルミ
ニウム―銅クラツド箔を、又は金又はニツケルメ
ツキした35μの銅箔をエポキシ系接着剤で接合し
た金属基板を用い、30μのアルミニウム線を超音
波ワイヤーボンデイングした時のボンデイングパ
ツドの種類と引張り強度の関係を第5図に示し
た。すなわち、本発明によるアルミニウム―銅ク
ラツド箔を用い選択的にエツチングを行なつて、
アルミニウム箔15μのボンデイングパツドを形成
させた実験例では引張強度が35μの銅箔上に金メ
ツキやニツケルメツキした時より高く、かつ引張
強度のバラツキが少ないことが分かる。メツキし
た場合にこのように引張強度のバラツキが大きく
なることは、メツキ面の性状がワイヤーボンデイ
ング性に著しい影響を与えるということであり、
メツキによつてボンデイングパツドを形成する場
合には避けられない欠点である。
Next, a 30μ aluminum wire was ultrasonic wire bonded using a metal substrate made by bonding a 2mm thick aluminum plate with a 50μ aluminum-copper clad foil or a 35μ gold or nickel plated copper foil with epoxy adhesive. Figure 5 shows the relationship between the type of bonding pad and the tensile strength. That is, by selectively etching the aluminum-copper clad foil according to the present invention,
It can be seen that in an experimental example in which a bonding pad of 15μ aluminum foil was formed, the tensile strength was higher than when gold plating or nickel plating was applied on a 35μ copper foil, and there was less variation in the tensile strength. This large variation in tensile strength when plated means that the properties of the plated surface have a significant effect on wire bonding properties.
This is an unavoidable drawback when forming a bonding pad by plating.

以上説明した通り本発明は、金属基板に絶縁物
層、アルミニウム―銅クラツド箔を順に積層し、
前記アルミニウム―銅クラツド箔をエツチングし
て配線パターンを形成すると共に、ボンデイング
パツドを形成し、半導体等とアルミニウム回路と
のアルミニウムリード線での固着が超音波振動法
により容易にかつ強固に行われるものである。
As explained above, the present invention sequentially laminates an insulating layer and an aluminum-copper cladding foil on a metal substrate,
The aluminum-copper cladding foil is etched to form a wiring pattern, and a bonding pad is also formed, so that the semiconductor, etc. and the aluminum circuit can be easily and firmly bonded to the aluminum lead wire using an ultrasonic vibration method. It is something.

【図面の簡単な説明】[Brief explanation of drawings]

第1〜4図は本発明の実施例の断面図であり、
第5図は引張強度の実施例と比較例を表わしたも
のである。 符号1…金属基板、2…絶縁物層、3…アルミ
ニウム箔、3′…アルミニウム回路、4…銅箔、
4′…銅回路、5…アルミニウムリード線、6…
半導体、7…半田、8…アルミニウム―銅クラツ
ド箔。
1 to 4 are cross-sectional views of embodiments of the present invention,
FIG. 5 shows examples and comparative examples of tensile strength. Symbol 1...Metal substrate, 2...Insulator layer, 3...Aluminum foil, 3'...Aluminum circuit, 4...Copper foil,
4'...Copper circuit, 5...Aluminum lead wire, 6...
Semiconductor, 7...Solder, 8...Aluminum-copper clad foil.

Claims (1)

【特許請求の範囲】[Claims] 1 金属基板に絶縁物層、アルミニウム(10〜
100μ)―銅クラツド箔を順に積層して一体化し
てなる積層物の前記アルミニウム(10〜100μ)
―銅クラツド箔をエツチングして、配線回路を形
成させ、さらにエツチングしてアルミニウム回路
もしくは銅回路を形成させ、該アルミニウム回路
と半導体とを超音波振動法によりアルミニウムリ
ード線で固着させることを特徴とする混成集積回
路の製法。
1 Metal substrate with insulating layer, aluminum (10~
100μ) - The above-mentioned aluminum (10 to 100μ), which is a laminate made by laminating copper clad foils in sequence and integrating them.
- A copper clad foil is etched to form a wiring circuit, further etched to form an aluminum circuit or a copper circuit, and the aluminum circuit and semiconductor are fixed with an aluminum lead wire using an ultrasonic vibration method. A method for manufacturing hybrid integrated circuits.
JP56146866A 1981-09-17 1981-09-17 Manufacture of hybrid integrated circuit Granted JPS5848432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56146866A JPS5848432A (en) 1981-09-17 1981-09-17 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56146866A JPS5848432A (en) 1981-09-17 1981-09-17 Manufacture of hybrid integrated circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP62079790A Division JPS62271442A (en) 1987-04-02 1987-04-02 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5848432A JPS5848432A (en) 1983-03-22
JPH0115153B2 true JPH0115153B2 (en) 1989-03-15

Family

ID=15417333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56146866A Granted JPS5848432A (en) 1981-09-17 1981-09-17 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5848432A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62140730U (en) * 1986-02-28 1987-09-05
JPS62271442A (en) * 1987-04-02 1987-11-25 Denki Kagaku Kogyo Kk Hybrid integrated circuit
JPS63250164A (en) * 1987-04-07 1988-10-18 Denki Kagaku Kogyo Kk High power hybrid integrated circuit substrate and its integrated circuit
JPH0783163B2 (en) * 1987-05-15 1995-09-06 キヤノン株式会社 Element wiring electrode and manufacturing method thereof
JP2564487B2 (en) * 1987-06-02 1996-12-18 電気化学工業株式会社 Circuit board and hybrid integrated circuit thereof
JP2608980B2 (en) * 1990-09-11 1997-05-14 電気化学工業株式会社 Metal plate based multilayer circuit board
MY139405A (en) 1998-09-28 2009-09-30 Ibiden Co Ltd Printed circuit board and method for its production

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5635038B2 (en) * 1972-12-11 1981-08-14
JPS5716516B2 (en) * 1974-03-29 1982-04-05
JPS5128662A (en) * 1974-09-02 1976-03-11 Sanyo Electric Co Riidosaisen no kochakuhoho
JPS5143571A (en) * 1974-10-09 1976-04-14 Hiroki Katsuki KEESUISOSOCHI
JPS52378A (en) * 1975-06-23 1977-01-05 Oki Electric Ind Co Ltd Method of forming printed wiring
JPS523461A (en) * 1975-06-25 1977-01-11 Kazutami Saito Measuring, detecting and alarming device of land subsidence under a bu ilding
JPS5259855A (en) * 1975-11-13 1977-05-17 Matsushita Electric Works Ltd Method of producing multiilayer printed circuit substrate
JPS5317747A (en) * 1976-08-02 1978-02-18 Sasaki Mooru Kk Natural light inlet tube
JPS5591896A (en) * 1978-12-28 1980-07-11 Fuji Electric Co Ltd Circuit board
JPS5662388A (en) * 1979-10-26 1981-05-28 Tokyo Shibaura Electric Co Hybrid integrated circuit board

Also Published As

Publication number Publication date
JPS5848432A (en) 1983-03-22

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