JPH0115233B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal polarity inversion control circuit, and in particular to a video signal that transmits a composite video signal of television by randomly inverting the polarity of the composite video signal using a pseudo-random code (abbreviated as PN code) in units of horizontal scanning lines. The present invention relates to a video signal polarity inversion control circuit that generates a control signal for a polarity inversion circuit in a signal scramble transmission system.

When transmitting television signals, a scramble transmission method was proposed in the Showa era by the same applicant as the present application, in which the polarity of the composite video signal is inverted using a PN code in units of horizontal scanning lines for the purpose of spectrum averaging and secrecy. This is proposed in the specification of the patent application ``Video Signal Transmission System'' (Japanese Patent Application No. 58-90940) filed on April 28, 1958. In this method, the polarity of the horizontal synchronization signal and the video signal is simultaneously inverted using a PN code, and the white level of the polarity-inverted video signal is approximately the same as the peak value of the synchronization signal whose polarity is not inverted. This is a method that cannot be received using the receiving method. In other words, in a synchronization signal separation circuit used in a normal reception system that separates signals exceeding a certain reference value, the horizontal synchronization signal pulse of the inverted scanning line portion does not appear in the separated composite synchronization signal output; Since the video signal of a high-brightness image is mixed into the video signal and mistakenly recognized as a vertical synchronization signal, in addition to inverting the video signal, both horizontal and vertical synchronization are disrupted, making it impossible to determine the content of the reproduced image. This is a good scrambling method. In this system, on the receiving side, it is necessary to restore the original signal by creating a synchronization signal and an inverted control signal from a composite video signal sent with the polarity inverted at the back porch portion of the horizontal synchronization signal, for example. Various methods can be considered for this purpose by applying conventional techniques, but as described above, a common synchronization signal separation circuit cannot separate only the synchronization signal, so it has the disadvantage of a complicated configuration.

An object of the present invention is to be able to be used in the above-mentioned video signal transmission system, to generate a synchronization signal and a polarity inversion control signal from the output of a normal synchronization signal separation circuit on the reception side, and to have a simple configuration that can be easily applied to the transmission and reception sides. An object of the present invention is to provide a video signal polarity inversion control circuit that can be used in common.

The video signal polarity inversion control circuit of the present invention is used in a video signal transmission method in which a composite video signal is transmitted with its polarity inverted randomly using a PN code in units of horizontal scanning lines, and the video signal generates a control signal for the polarity inversion circuit. In the polarity reversal control circuit, a synchronizing signal separating means separates and shapes a signal exceeding a certain reference value from a composite video signal, a clock pulse generating means generates a clock pulse with a high repetition frequency that is an integral multiple of the horizontal synchronizing frequency, and the clock pulse vertical synchronization signal detection means for counting a predetermined number of vertical synchronization pulses corresponding to a time longer than the notch width of the vertical synchronization pulse and shorter than the horizontal retrace period, and detecting the vertical synchronization signal from the output of the synchronization signal separation means by digital processing; The clock pulse is connected to the outputs of the vertical synchronizing signal detecting means and the synchronizing signal separating means, and starts dividing the clock pulse by a specific horizontal synchronizing signal pulse following the vertical synchronizing signal to generate pulses with a repetition frequency equal to the horizontal synchronizing frequency. horizontal synchronization signal generation means that generates a predetermined number of signals;
By providing a delay means for giving a fixed time delay to the output pulse of the horizontal synchronization signal generation means, and a PN code generation means having a reset function and generating the PN code by using the output pulse of the delay means as a clock input. It is composed of

Next, the present invention will be explained in detail with reference to the drawings.
The embodiment will be described with reference to the Japanese color television standard system with 525 scanning lines, 59.94 Hz field frequency, interlaced scanning, and NTSC system, but it goes without saying that the present invention can be applied to other systems as well.

FIG. 1 is a block diagram of an embodiment of the present invention, which is a conventional synchronization signal separation circuit (SYNC) that separates a signal exceeding a certain reference value from a composite video signal 100.
SEP) 1 and horizontal sync frequency (15.734kHz) 2 ⁹
Clock pulse generation circuit (CLOCK OSC) that generates clock pulses with twice the repetition frequency (8.055808MHz, but hereinafter referred to as 8.056MHz)
2, a vertical synchronization signal detection circuit (V.SYNC DET) 3 that detects a vertical synchronization signal from the output of SYNC SEP1 through digital processing, and horizontal synchronization by dividing the clock pulse 101 based on the output 102 of V.SYNC DET3. A horizontal synchronization signal generation circuit 4 that reproduces the signal 103, a delay circuit (DELAY) 5 that provides a certain time delay to the horizontal synchronization signal output 103, and a clock input of the output 104 to generate the longest time sequence (referred to as m sequence). It consists of a PN code generator (PN GEN) 6 that generates a PN code, and an AND gate 7 that opens and closes the output of the PN GEN 6. In FIG. 1, reference numeral 8 is a key code setter for setting the initial conditions of PN GEN 6, and 9 is a polarity inversion circuit (SW CCT) including a clamp circuit controlled by control output 105.

The operation shown in FIG. 1 will be explained below using the time chart shown in FIG. 2. FIG. 2a shows the above-mentioned composite video signal input 100 whose polarity has been inverted, and during the vertical retrace period, an equalization pulse e, a vertical synchronization pulse v, and a horizontal synchronization signal pulse h are applied to the horizontal synchronization period H, respectively. The last horizontal scanning period H _L of each field and the interval between the last equalization pulse and the first horizontal synchronization pulse H _O are 1/2H or 1/2H depending on the even and odd fields. It becomes H. Figure 2 a shows the composite video signal 100 SYNC
The composite synchronization signal 106 separated and shaped in SEP1 is
When the video signal level of the inverted horizontal scanning period is high, a wide pulse B appears successively, as shown in Fig. 2b, and when the signal level is low, as shown in Fig. 2c, the horizontal synchronizing signal for this period appears. disappears. If this output is detected, for example, through a low-pass filter to detect the vertical synchronization signal, or by the conventional digital synchronization signal detection circuit described in Japanese Patent Publication No. 57-29108, then in the case of Fig. 2b, an inverted video signal is detected. B is mistaken for a vertical synchronization signal. On the other hand, as will be described in detail later, V.SYNC DET3 of this embodiment has a second pulse whose width is increased by the time τ required to count 48 clock pulses 101 with a frequency ²⁹ times higher than that of the horizontal synchronizing signal. The pulse shown in Figure 2D is generated, this pulse is detected by a pulse width detection circuit using digital processing using a clock pulse with twice the horizontal synchronization frequency, and only the vertical synchronization signal detection pulse 102 is generated as shown in Figure 2E. It is configured like this.

The horizontal synchronization signal generation circuit 4 includes a start pulse detection circuit (START COUNT) as shown in FIG.
41, flip-flop (FF) 42, AND gate 43, and frequency division counter (DIVIDE) 44
and end pulse detection circuit (END COUNT) 4
5 and operates as follows.
START COUNT41 is V. shown in Figure 2 e.
It is activated by the SYNC DET output 102 and is configured to count the rising edges of the synchronizing signal pulses of the composite synchronizing signal 106 of FIG. 2b, and to send out the start pulse 107 of FIG. 2f at the rising edge of the ninth pulse. This is a counter circuit, and a start pulse synchronized with the rise of the first horizontal synchronizing signal pulse can be obtained regardless of the length of the H _O interval, which varies between even and odd fields. The FF 42 is set by this start pulse, and its Q output 108 opens the AND gate 43 and sends the clock pulse 101 to the DIVIDE 44. DIVIDE 44 divides the clock pulse by ^1/29 and generates the horizontal synchronization signal output 103 of FIG. 2g which is synchronized with the horizontal synchronization signal. END COUNT45 counts these pulses, and at the same time counts a certain number of pulses, for example, the 252nd pulse (corresponds to the last horizontal sync signal pulse for even fields, and the previous horizontal sync signal pulse from the last for odd fields). The end pulse 108 shown in FIG. 2h is generated.
This end pulse is applied to the reset terminal of FF42, closes the AND gate 43, and resets DIVIDE42.
is reset when the clock input is disconnected.

The output 103 of the horizontal synchronization signal generation circuit 4 is
A digital delay circuit DELAY5 having a clock pulse 101 of 8.056 MHz as a clock input provides a delay of a certain time τ' and is applied to the PN GEN6 as a clock input signal 104 shown in FIG. m-sequence PN codes whose codes are inverted in synchronization with are generated.
This fixed time is set to an arbitrary time from after the back pouch section to the color burst, and in this embodiment is set to about 7 μs. This PN code is applied to SW CCT 9 via AND gate 7 to restore the inverted signal. If the same circuit is used for polarity reversal control on the transmitting side and the key code settings of the PN GEN 6 are the same, the input composite video signal on the transmitting side is restored to the output of the SW CCT 9.
In FIG. 1, an AND gate 7 is provided to inhibit polarity reversal within the vertical synchronization signal period by the Q output 108 of the FF 42 shown in FIG. 2i.

FIG. 3 is a block diagram of one embodiment of the V.SYNC DET 3 of FIG.
A clock pulse counter 31 that counts 48 clock pulses and generates an output pulse 109, a composite synchronizing signal 106, and an output 109 of the clock pulse counter 31 are set and reset to generate an output pulse 110 shown in FIG. 2d. When four consecutive AND outputs of the flip-flop 32, the output 110 of the flip-flop 32, and the clock pulse generator (CLOCK OSC) 36 with twice the horizontal synchronization frequency (31.5kHz) are counted, a pulse is generated to generate the vertical synchronization detection pulse 102. It is composed of a width detection circuit 33. The clock pulse counter 31 includes hexadecimal counters 34, 34' and an AND circuit 35 as shown in FIG.
Since the time τ for counting 48 clock pulses is shorter than the horizontal retrace period T and longer than the notch width l of the vertical synchronizing pulse, a wide pulse A can be obtained only for the vertical synchronizing signal. , for the inverted video period, it becomes an independent pulse shorter than H, such as B'. Note that since the frequency of the CLOCK OSC 36 is selected to be twice the horizontal synchronization frequency, the rise time t of the vertical synchronization signal detection pulse in FIG. START of synchronous signal generation circuit 4
COUNT41 counts the 5th and 6th 2 vertical sync pulses and 6 equalization pulses, detects the 9th pulse, and calculates the first horizontal sync pulse of each field regardless of H _O. A start pulse 109 synchronized with the signal pulse is obtained. Similar detection can be achieved by detecting the sixth pulse using the output 110 of the flip-flop 32 instead of the composite synchronization signal 106; in this case, the CLOCK
There is an advantage that there is no effect even if the frequency of the OSC 36 changes.

V.SYNC DET used in this example
3. CLOCK OSC2, horizontal synchronization signal generation circuit 4
The circuit consisting of
97780) is the configuration proposed in the specification of
Similar circuits described in the above specification are also applicable to the present invention. For a more detailed description of this circuit, please refer to the above specification.

In the above embodiment, PN GEN6 is an m-sequence PN code generator, but it is clear that it is not limited to m-sequence codes and may be any other pseudo-random code sequence.
Although the reset signal is configured to be reset by the output 102 of No. 3, other signals may be used as the reset signal. Also, an AND gate 7 is provided at the output of PN GEN6 to prohibit polarity reversal within the vertical synchronization signal period, but if PN GEN6 is reset before the vertical synchronization signal period (the output of PNGEN6 at the time of reset is “0” (corresponding to non-inverting side control), the AND gate 7
is not necessarily necessary. Furthermore, end pulse 10
8 and the start pulse 107 are not necessarily limited to the first horizontal synchronizing pulse and the last horizontal synchronizing pulse, and even if a specific horizontal synchronizing signal pulse or equalization pulse (only the end pulse) other than the above is selected, If circuits with the same configuration are used on the transmitter and receiver sides, they will operate without any problems and provide approximately the same concealment effect.

As explained in detail above, according to the video signal polarity inversion control circuit of the present invention, when the polarity is randomly inverted in units of horizontal scanning lines and the level of the video signal whose polarity has been inverted reaches the synchronization signal level that is not inverted, However, the polarity inversion control signal synchronized with the horizontal synchronization signal can be output from the output of a normal synchronization signal separation circuit.
There is an effect that can be generated reliably regardless of missing horizontal synchronizing signal pulses or interference with the video signal, and by using this, it is possible to realize a scramble transmission system with a simple configuration and a large concealment effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
1 is a time chart explaining the operation of FIG. 1, and FIG. 3 is a block diagram of an embodiment of the vertical synchronization signal detection circuit of FIG. 1. 1... Synchronous signal separation circuit (SYNC SEP), 2,
36...Clock pulse generation circuit (CLOCK
OSC), 3... Vertical synchronization signal detection circuit (V.SYNC
DET), 4...Horizontal synchronization signal generation circuit, 5...Delay circuit (DELAY), 6...Pseudo random code generator (PNGEN), 7, 35, 43...AND gate, 8...Key code setting device , 9... Polarity inversion circuit (SW CCT), 31... Clock pulse counter, 32, 42... Flip-flop (FF),
33...Pulse width detection circuit, 34, 34'...16
advance counter.

Claims (1)

[Claims] 1. In a video signal polarity inversion control circuit that generates a control signal for a polarity inversion circuit used in a video signal transmission method in which a composite video signal is transmitted with its polarity inverted randomly using a pseudo-random code in units of horizontal scanning lines, a composite video signal a synchronizing signal separating means for separating and shaping a signal exceeding a certain reference value from the horizontal synchronizing frequency, and a clock pulse generating means for generating a clock pulse having a high repetition frequency that is an integral multiple of the horizontal synchronizing frequency.
a vertical synchronization signal that detects a vertical synchronization signal from the output of the synchronization signal separation means by counting a predetermined number of the clock pulses corresponding to a time longer than the notch width of the vertical synchronization pulse and shorter than the horizontal blanking period; and by digital processing; detecting means, which are connected to the outputs of the vertical synchronizing signal detecting means and the synchronizing signal separating means, and begin dividing the clock pulse by a specific horizontal synchronizing signal pulse following the vertical synchronizing signal, at a repetition rate equal to the horizontal synchronizing frequency; A horizontal synchronizing signal generating means for generating a predetermined number of pulses, a delay means for giving a fixed time delay to the output pulse of the horizontal synchronizing signal generating means, and a reset function are provided. 1. A video signal polarity inversion control circuit comprising: pseudo-random code generating means for generating a pseudo-random code.