JPH0115898B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a reproducible information compression circuit, and more particularly to an information compression circuit characterized by a mechanism for automatically detecting and compressing a repetitive pattern portion in a signal.

Background of the Technology Conventionally, one of the methods for troubleshooting printed circuit boards is to apply the same test pattern signal as the non-defective product to the defective product, compare the node signals of the defective product with those of the non-defective product, and determine whether the defective product operates in the same way as the non-defective product. There is a way to determine whether or not there is one. In this method, if a feedback loop exists in the circuit of the printed circuit board, a method is adopted in which the first part of the feedback loop that behaves differently from a non-defective part is determined to be a defective part. In this case,
The signal movements of good and defective products must be constantly compared. For this reason, a method of simultaneously comparing non-defective products and defective products using a card tester is used, but this poses a problem in that it is necessary to always have a supply of non-defective products. In this case, it is possible to store the signal movements of non-defective products in a memory in advance and reproduce them for use, but this has the drawback of requiring a memory with a large storage capacity.

Summary of the Invention In order to solve the problems of the conventional method described above, the present invention compresses and stores information in a memory.
This provides an effective means that allows the original information to be read and used when necessary.

In the present invention, as a configuration for that purpose, the time series t ₀ ,
means for supplying signals of t ₁ , ......t _o-1 , t _o , ......; means for inputting a data string constituted by a plurality of data elements arranged according to the time series; , a first register that sequentially stores data elements at time t _o in the data string, a second register that sequentially stores data elements at time t _o-1 transferred from the first register; a time series memory whose address is the output of the second register and whose write data is the output of the first register; a third register which stores the read data of the time series memory; , a means for operating each of the first to third registers and the time series memory, a comparator for comparing the output of the third register and the output of the first register, and a comparator that outputs a match output. and means for sequentially storing the outputs of the first register and the time series coincidence counter in a memory when the comparator generates a mismatch output. .

EXAMPLES OF THE INVENTION The present invention will be described in detail below using examples.

FIG. 1 is a configuration diagram of an embodiment circuit when the present invention is applied to a card tester. Further, FIGS. 2 to 4 are explanatory diagrams of the operation of the circuit shown in FIG. 1. In FIG. 1, 1 is a rising/falling detection circuit, 2 is a strobe STB counter, 3 is a transition interval counter, 4 is a first register R ₁ , 5 is a second register R ₂ , 6 is a time series memory, and 7 is a The third register R ₃ , 8 is a comparator, 9 to 11 are delay circuits,
12 is a time series coincidence counter, 13 is a memory address counter, 14 is a main memory, and 15 is a comparator.

In addition, 16 is the test DATA signal from the circuit under test (UUT) board, and 17 is the test DATA signal from the card tester.
Strobe STB which is DATA sampling signal
18 is a transition point signal indicating the rise and fall of the DATA signal, 19 is a run length signal indicating the length between transition points, 20 is the output of the first register _R1 ,
21 is the output of the third register _R3 , 22 is the comparator output
R ₁ ≠ R ₃ detection signal, 23 is time coincidence counter 12
24 is the write data to the main memory 14, 25 is the read data from the main memory 14, and 26 is the comparison output of the comparator 15.

In FIG. 1, a rising/falling detection circuit 1 and a transition interval counter 3 constitute a data compression circuit using run-length encoding. Figure 2 shows
It is an explanatory diagram of the operation. (i) is the DATA signal 1 obtained by applying a test pattern to the circuit board under test.
6 is shown. The rising/falling detection circuit 1 performs the following at transition times t ₀ to t ₁₂ of the DATA signal 16 shown in the figure.
A transition point signal shown in (ii) is generated.

The transition interval counter 3 is a counter that counts the STB signal 17 as a clock input CK and uses the transition point signal 18 as a clear input CLR, and counts the STB signal between transition points, which is shown in (iii). It is output as a run length code 19.

In FIG. 1, the circuit from the next first register _R1 to the main memory 14 is a circuit for compressing and storing redundant repeating patterns in the run-length code. FIG. 3 shows the signal relationships inside these circuits.

It is assumed that the run length code input to the first register _R1 is (123123123412). These codes are read from the first register R ₁ at the next transition time signal and written to the second register R ₂ .
If we generalize the values of R ₁ and R ₂ at the transition point, we get
The value of R ₁ becomes the input data of t _o , and the value of R ₂ becomes the input data of t _o-1 .

The read/write operation of the memory 6 is controlled so that, after reading the data at the address indicated by the value of _R2 into the third register _R3 , the value of _R1 is immediately written to the same address. Therefore, data is written to memory 6 at address 1 when t ₂ is reached.
data “2” to address 2 at t ₃ .
3", and so on. On the other hand, the data read from the memory 6 is not from t ₁ to t ₄ , but at t ₅ , the data "2" that was previously written to address 1 at t ₂ is read. is read out.

Comparator 8 compares R ₁ output 20 and R ₃ output 21, and produces a "1" output when they do not match (R ₁ ≠ R ₃ ). The function of this circuit is to check whether the data read out from the address indicated _by the data t _{o -1} in the memory 6 matches the data written in t _o . Thereby, the presence or absence of data redundancy due to the repeated pattern is detected and data compression is performed.

FIG. 4 is a diagram illustrating the repetitive pattern detection operation. The write data (23123123412) to the memory 6 shown in FIG.
The data is written to addresses 1 to 5 in the illustrated time series, superimposed on the previous write data.
At this time, when the read data from the same address immediately before writing matches the write data, that is, when the same data is found on the left side in the figure, two data pairs, that is, data consisting of an address and its data, Indicates that the pairs match. For example, (12) appears for (12), and (23) appears for (23).

As long as such identical data pairs appear one after another in the same order, the data in the memory is not updated. However, a data pair that does not match the previous data pair will be written. As shown (......
......), new data is written to the memory.

In this way, as shown in Figure 4, when a time-series pattern is created in the memory address space, as long as it matches the data on the left, the number of matches is counted, the repeated pattern is encoded, and the data is compressed. becomes possible. As shown in the corresponding line of FIG. 3, the time series coincidence counter 12 in FIG.
The transition time signal 18 is counted from t ₅ to t ₁₀ when the same pattern is repeated and a pattern mismatch occurs (R ₁ ≠ R ₃ ). Cleared at t ₁₀ .

The output 22 of the comparator 8 also serves as a write signal to the main memory 14, and the comparator does not match (R ₁ ≠ R ₃ ).
At times t ₁ to t ₄ and t ₁₀ and t ₁₁ indicating R ₁ output 2
Write data 24 consisting of 0 and the output 23 of the time series coincidence counter 12 is written to the main memory 14.

The memory address counter 13 counts the mismatch signal 22 every time there is a pattern mismatch, and sequentially increments the data write address of the main memory 14.

In this manner, the input DATA signal 16 is subjected to run-length encoding and compression of redundant repeating patterns and is compactly stored in main memory.

Note that the time series memory 6 must be initialized to a certain arbitrary value before starting compression using this circuit.

When testing a board using this example circuit, first collect data from a pass/fail circuit board.
The compressed data is stored in memory, and then the DATA signal is collected for the circuit board under test.
Supplied to the circuit of this embodiment. Data compression processing is performed in the same way as for non-defective circuit boards, and write data 2
Outputs 4. In this case, there is no need to perform memory writing. At this time, the previously written non-defective data is transferred from the main memory to the read data 25.
The comparator 15 compares these write data 24 and read data 25. When a discrepancy is detected, the current
Read the value of STB counter 2, and when necessary, use the compressed data of the good product stored in the main memory.
Raw data according to the specified algorithm
Restore the waveform.

Thereafter, a conventional fault point analysis method is used to calculate the mismatch point indicated by the value of the STB counter 2, that is, the fault detection point or the fault point on the board, or fault analysis is performed on the restored DATA waveform. In addition,
Although the above explanation relates to the case where the present invention is applied to circuit board testing, it goes without saying that the present invention is not limited to this and can be widely used as a general data compression technology. Nor.

Effects of the Invention As described above, according to the present invention, long data including repetitive patterns can be effectively compressed using a relatively simple mechanism. The role it can play in improving the efficiency of data transmission is significant.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of run-length encoding, Fig. 3 is an explanatory diagram of redundant repeating pattern compression circuit operation, and Fig. 4 is an illustration of redundant repeating pattern detection operation. It is an explanatory diagram. In the figure, 1 is a rising/falling detection circuit, 3 is a transition interval counter, 4, 5, 7 are registers, 6 is a time series memory, 8 is a comparator, 12 is a time series coincidence counter, 13 is a memory address counter, 14 indicates main memory.

Claims (1)

[Claims] 1. Means for supplying signals of time series t ₀ , t ₁ , ...... t _o-1 , t _o , ...... Data composed of a plurality of data elements arranged according to the time series means for inputting a sequence; a first register for sequentially storing data elements at time t _o in the data sequence;
a second register that sequentially stores data elements at time t _o-1 transferred from the register; and a time-series memory that uses the output of the second register as an address and the output of the first register as write data. , a third register for storing read data of the time series memory; means for operating each of the first to third registers and the time series memory according to the time series signal; a comparator that compares the output of the register with the output of the first register;
a time-series coincidence counter that counts the number of times the comparator produces a coincidence output; and when the comparator produces a mismatch output, the outputs of the first register and the time-series coincidence counter are sequentially stored in a memory. An information compression circuit characterized by comprising: means.