JPH0117606B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a timing amplifier circuit that constitutes a self-timing digital repeater that extracts timing from a transmitted pulse train, has a small phase deviation, has excellent amplitude limiting characteristics, and can be made into a monolithic IC. It is related to.

In self-timing digital repeaters, the clock frequency component is extracted from the received transmission pulse train using a filter such as a surface acoustic wave filter.
The frequency component is amplified in the timing amplification circuit to a constant amplitude required for identification and reproduction, and then supplied to the identification and reproduction circuit. At this time, since the filter output level fluctuates due to fluctuations in the transmission pulse pattern, etc., the timing amplifier circuit normally maintains (i) a constant timing signal amplitude against fluctuations in the timing input level of 20 to 30 dB, and (ii) ) It is necessary to keep the phase deviation small.

Conventionally, this type of timing amplifier circuit sets the operating point in the active region near the cut-off region in order to avoid the occurrence of phase deviation due to saturation in single-ended amplifiers and to limit the amplitude, and the amplifiers are cascaded by capacitive coupling. are connected to achieve the desired characteristics. In this case, in order to obtain an appropriate operating point and AC load characteristics, a large capacitance of approximately several thousand pF is required as a collector load adjustment capacitor, an emitter bypass capacitor, etc. Therefore, such a circuit configuration is not suitable for monolithic ICs in which it is difficult to realize large capacity. Furthermore, monolithic ICs have the disadvantage that the operating point cannot be set with high precision because the variation in the absolute values of resistances, etc. reaches several tens of percent.

The present invention provides a single-type timing amplifier circuit that (i) is equipped with a current limiting circuit to avoid saturation, (ii) is equipped with a DC bias circuit that provides a stable operating point, and (iii) has a small coupling capacitance. (iv) high input impedance with sufficient gain;
Its main feature is that it can provide an output that is in phase with the input signal, and its purpose is to obtain a timing signal with small phase deviation and stable amplitude for timing circuit input signals of different levels.

FIG. 1 shows an embodiment of the timing amplifier circuit of the present invention, in which 1 is an input transistor, 2 is a base,
3 is a collector, 4 is an emitter, 5 is an output transistor, 6 is a base, 7 is a collector, 8 is an emitter, 9 is a positive power supply terminal, 10 is a feedback impedance, 11 is a constant voltage circuit, 12 is a negative power supply terminal, 13
14 is a current limiting circuit, and 14 is a DC feedback circuit.

The operation of the timing amplifier circuit shown in FIG. 1 will be explained. The input terminal of this timing amplifier circuit is the base 2 of the input transistor 1. When the output of a surface acoustic wave filter or the like is applied to the base 2, a signal with the opposite phase to the input signal is generated at the collector 3, and this output signal causes the collector 7 of the output transistor 5, that is, the output terminal, to have the same phase as the input signal. A signal is generated. At this time, there is a low impedance between the emitter 4 of the input transistor 1 and the negative power supply terminal 12 until a certain amount of current I _L is reached, and the voltage drop between the terminals is constant, and when the current reaches I _L , there is a high impedance. A current limiting circuit 13 is connected, and when the emitter current of the input transistor 1 increases due to an input signal and reaches _IL , the emitter current is limited to _IL . Further, the base bias current of the input transistor 1 is supplied by a DC bias circuit consisting of a constant voltage circuit 11 and a DC feedback circuit 14. Since the input impedance seen from the base 2 of this DC bias circuit is sufficiently high compared to the input impedance of the input transistor 1, the voltage gain of this timing amplifier circuit is approximately equal to the input impedance of the input transistor 1.
It is given by the product g _n1 ·Z _F of the mutual conductance g _n1 of , and the feedback impedance 10, Z _F . The terminal voltage of the constant voltage circuit 11 has the same current dependence and temperature dependence as the base-emitter voltage of the input transistor 1.

With the above configuration, the functions and effects described below can be obtained. (1) Since the maximum value of the emitter current of the input transistor 1 is limited by the current limiting circuit 13, the maximum emitter current of the input transistor 1 can be set appropriately.
can be prevented from becoming saturated. Therefore, it is possible to suppress the occurrence of phase deviation caused by deterioration of response speed due to saturation of the transistor. (2) Current limiting circuit 13 connected to emitter 4 of input transistor 1
Since the impedance of is low until it reaches the above-mentioned limit current I _L , the broadband performance of the timing amplifier circuit can be ensured. (3) Since the voltage between the terminals of the constant voltage circuit 11 has the same current and temperature dependence as the voltage between the base and emitter of the input transistor 1, for example, when the DC feedback circuit 14 is composed of a series resistor, the input transistor The emitter current value of the output transistor 5 is stably set to a value smaller than the emitter current of the output transistor 5. That is, the input transistor 1 is set in the active region near the cutoff region. In addition, input transistor 1 to output transistor 5 to constant voltage circuit 11
- The DC feedback loop consisting of the DC feedback circuit 14 provides a stable bias condition (operating point) even with temperature fluctuations. (4) Since it has a high input impedance, for timing signals of several 10 to several 100 MHz, the input signal can be converted into an IC with a microcapacitor.
Even if it is applied to the input terminal 2 through several pF, the decrease in voltage gain is small. Therefore, it is also possible to form a high-gain timing amplifier circuit into an IC by cascading the timing circuits shown in FIG. 1 using capacitors.

FIG. 2 shows an embodiment of the current limiting circuit 13,
15 is a current limiting transistor, 16 is an emitter,
17 is a base, 18 is a collector, 19 is a maximum current setting diode, and 20 is a maximum current control resistor. This current control circuit 13 is an ordinary current mirror circuit, and the current flowing through the maximum current control resistor 20 is the collector current of the current limiting transistor 15, that is, the maximum value of the emitter current of the input transistor 1 (the limiting current I _L ). In the configuration in which the collector 18 and the emitter 4 of the input transistor 1 are connected as shown in _FIG . The emitter current of No. 15 is shared by the base current of the same transistor and becomes saturated, and the emitter-collector voltage is about 0.02 to 0.05 V.
Exhibits low impedance. On the other hand, due to the input signal, the emitter current of the input transistor 1 increases with respect to the base current I _B of the current limiting transistor 15,
When the voltage becomes approximately h _FE · I _B (h _FE ; current amplification factor), the emitter-collector voltage of the transistor rises rapidly and exhibits high impedance. The above characteristics satisfy the characteristics of the current limiting circuit 13 described in the explanation of FIG.

This is an embodiment of the constant voltage circuit 11 and the DC feedback circuit 14 shown in FIGS. 3 and 1, in which 21 is a voltage regulating diode and 14 is a DC feedback circuit using a series resistor. The series resistor 14 is several kΩ, and the diode 2
Input transistor 1
By adopting the same structure as , it is possible to increase the input impedance of the DC bias circuit and set the operating point near the cutoff region of the input transistor 1 as described in the explanation of FIG.

In the timing amplifier circuit shown in FIG. 1, by applying an impedance having frequency dependence to the L-C-R parallel resonant circuit as the feedback impedance 10 and Z _F , a gain characteristic having frequency selectivity can be obtained, and the target By setting the resonant frequency to the timing signal frequency, a timing amplification circuit with high S/N and high gain can be constructed.

As explained above, (1) it limits the emitter current of input transistor 1 and is equipped with a low-impedance current limiting circuit, so saturation of the input transistor can be avoided in response to excessive input signals, and wide-band Gain characteristics can be obtained. Therefore, there is an advantage that output signal phase deviation due to response speed deterioration can be suppressed for timing input signals having different levels.

(2) Since it is equipped with a DC bias circuit that stably sets the operating point of the input transistor to the active region near the cutoff region, good amplitude limiting characteristics can be obtained in conjunction with the effect of the current limiting circuit in item (1) above. .

(3) Since it is equipped with a DC bias circuit with high input impedance, the amount of decrease in voltage gain is small even in a multi-stage configuration with minute capacitive coupling of several pF.
As a result, a multi-stage timing amplifier circuit can be constructed in which the stages are coupled with a capacitance of several pF, and can be implemented as an IC. Since it is capacitively coupled, it has the advantage that extremely stable characteristics can be obtained against temperature fluctuations even if a high gain multi-stage amplifier circuit is configured.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the timing amplifier circuit of the present invention, FIG. 2 shows an embodiment of the current limiting circuit, and FIG. 3 shows an embodiment of the DC bias circuit. 1... Input transistor, 2, 6, 17... Base, 3, 7, 18... Collector, 4, 8, 16
... Emitter, 5 ... Output transistor, 9 ...
Positive power supply terminal, 10... Feedback impedance, 11
... Constant voltage circuit, 12 ... Negative power supply terminal, 13 ...
Current limiting circuit, 14... DC feedback circuit, 15...
Current limiting transistor, 19... Maximum current setting diode, 20... Maximum current control resistor, 21...
...Voltage regulating diode.

Claims (1)

[Claims] 1. The base terminal of the first bipolar transistor is used as an input terminal, and the collector of the first transistor is connected to the base of the second transistor and to the collector via a feedback impedance to form a collector load resistance. A common emitter-grounded amplifier circuit is configured in which the first and second transistors are common, a current limiting circuit is connected between the emitter terminal of the first transistor and the negative power supply terminal or the ground terminal, and the emitter terminal of the second transistor is connected between the emitter terminal and the negative power supply terminal or the ground terminal. and a negative power supply terminal or a ground terminal are connected by a nonlinear element having the same current-temperature dependence as the voltage between the base and emitter terminals of the first transistor for constant voltage, and the emitter terminal and the base of the first transistor are connected. 1. A timing amplification circuit for a self-timing digital repeater, comprising a high input impedance DC bias circuit that sets the operating point of the first transistor near a cutoff region by connecting through a high resistance. 2. Claim 1, characterized in that an LCR parallel resonant circuit whose resonant frequency is set to the target timing signal frequency is used as the feedback impedance that connects the collector of the first transistor and the collector of the second transistor. The timing amplification circuit of the self-timing digital repeater described in .