JPH0117632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a charge transfer image sensor, particularly an interline transfer type image sensor.

A solid-state image sensor using an interline transfer method, which has been improved as solid-state image sensors become smaller in size or more highly integrated, has a plurality of photoelectric conversion sections 11 separated and arranged two-dimensionally as shown in FIG. For example, in the case of two-phase drive, a vertical charge transfer register (hereinafter simply referred to as a vertical register) in which a first vertical transfer electrode group 12 and a second vertical transfer electrode group 13 are arranged alternately. a column 14 and a vertical transfer electrode group 12 corresponding to the photoelectric conversion section 12;
Alternatively, an image sensor without a gate electrode on a gate region for reading accumulated charges from a photoelectric conversion section having a structure consisting of a gate region 15 covered with the vertical transfer electrode between 13 and 15 times has been proposed.

As shown in Fig. 2, during vertical transfer operation, such an image sensor is driven within a range with the potential relationships shown in Fig. 22 and 23, while the accumulated charge in the photoelectric conversion section is read out to the vertical register. Sometimes, a voltage even higher than that during vertical transfer is applied to each vertical transfer electrode group to achieve the potential state shown in FIG. Drive. In order to perform well-known interlaced scanning on such an image sensor, it is necessary to drive it with a three-level vertical register drive waveform as shown in FIG.

By the way, each transfer electrode of a charge transfer image sensor is a complete capacitive load, and the interphase coupling capacitance of each electrode driven by two-phase or four-phase pulses may be equal to or greater than the capacitance generated between the substrate and the substrate. Therefore, it is essential that the drive circuit for driving such transfer electrodes has low impedance, and even in conventional two-level drive, it is inevitable that power consumption tends to increase and the number of circuit components increases. In order to convert such a drive circuit into a three-level drive circuit most reliably, as shown in _FIG . This is a method of adding a power supply voltage switching circuit 42 that switches between _H and H, but in such a three-level vertical transfer electrode drive circuit, the third
The drive waveform shown in the figure inevitably has the disadvantage of extremely high power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a drive circuit for a charge transfer image sensor that consumes low power and has a small number of components.

According to the present invention, a plurality of vertical charge transfer register arrays are formed of a plurality of photoelectric conversion units arranged two-dimensionally on the same semiconductor substrate and a group of vertical transfer electrodes provided corresponding to the photoelectric conversion units. and at least a gate region covered by the vertical transfer electrode group between the photoelectric conversion section and the corresponding vertical transfer electrode group, and a horizontal transfer register for sequentially reading parallel charges of the electrostatic charge transfer register array. In the drive circuit of the charge transfer image sensor equipped with the first switching circuit that generates the pulse amplitude necessary for vertical transfer, and the vertical transfer pulse amplitude necessary for reading out the accumulated charge in the photoelectric conversion region, a second switching circuit for generating a pulse amplitude, a diode having the power input part of the first switching circuit as a cathode and the power supply side as an anode; There is obtained a drive circuit for a charge transfer image sensor, characterized in that the drive circuit comprises at least a capacitor connected between the cathodes, and the output end of the first switching circuit is the connection end to the vertical charge transfer register electrode.

According to the present invention, a three-level drive circuit for an interline charge transfer image pickup device with low power consumption and a small number of components is realized.

Next, an embodiment of the present invention will be explained in detail using the drawings.

FIG. 5 is a diagram showing a drive circuit according to the present invention, and here, to simplify the explanation, a drive circuit for an image sensor that operates with two-phase pulses is shown. 51 is the first
This switching circuit generates pulses necessary for vertical transfer, and a voltage corresponding to the amplitude necessary for vertical transfer is applied to the power input section 52 through a diode 54 with the power supply section 53 as an anode. has been done. This first switching circuit is exactly the same switching circuit as the conventional binary level drive circuit, and the input signal is exactly the same timing pulse. This first switching circuit constitutes a complementary switching circuit including a P channel enhancement MOS transistor 55 and an N channel enhancement MOS transistor 56 in order to efficiently drive the capacitive load with low impedance.
In a switching circuit with this configuration, when a capacitive load is applied, only the charging current flows to the load, so the power consumption is very low. Reference numeral 61 denotes a first switching circuit, and in this switching circuit, a voltage corresponding to a pulse amplitude that is further added to the vertical transfer pulse amplitude required when reading out the accumulated charge in the photoelectric conversion region is applied to the power input section 62. There is. In this embodiment, since the voltage is approximately equal to the pulse amplitude required for vertical transfer, it is connected to the first switching power supply section 53. This second switching circuit
Similar to the switching circuit shown in FIG.

The output terminal 67 of this second switching circuit 61
is connected to the other end of a capacitor 64 whose one end is connected to the power input section 52 of the first switching circuit 51 . Note that the capacitance of this capacitor 64 is normally selected to be sufficiently larger than the drive electrode capacitance. This second switching circuit is supplied with an input signal that generates one pulse every vertical blanking period of television scanning.
Further, the two-phase vertical transfer electrodes φV ₁ 71 and φV ₂ 72 are connected to the output end 5 of the first switching circuit 51, respectively.
Connected to 7. In the operation of this drive circuit, during the vertical transfer period, the transistor 66 of the second switching circuit is on, so the capacitor 64 is charged with the voltage supplied to the first switching circuit. And the second vertical blanking period
When the transistor 65 of the switching circuit turns on, one end of the capacitor 64, which has been at GND potential, rises to the second supply voltage, so the potential of the other end of the capacitor 64, 52, becomes higher than the vertical transfer pulse amplitude. The supply voltage to the second switching circuit increases. In other words, a read pulse is added. At this time, if the transistor 55 of the first switching circuit 51 is ON, the potential of the first output terminal 57 has the vertical transfer pulse amplitude plus the pulse amplitude necessary for reading out the photoelectric conversion section. Therefore, if the first switching circuit 51 that generates the vertical transfer pulses φV ₁ and φV ₂ alternately inputs the vertical transfer timing pulse to turn on the high level during the vertical blanking period, that is, turn on the transistor 55, the photoelectric conversion section can be alternately turned on. The pulses shown in FIG. 3 necessary for reading are applied, and an interlace operation is realized. In the above embodiment, the readout pulse of the photoelectric conversion unit as shown in FIG _.
In other words, the transistor 55 of the first switching circuit is turned on in advance, and then the transistor 6 of the switching circuit is turned on.
Although we have shown an example of the operation in which transistor 5 is turned on, the opposite case is shown when transistor 6 of the second switching circuit is turned on.
5 is turned on, even if the transistor 56 of the first switching circuit is turned off and then the transistor 55 of the first switching circuit is turned on,
The transistor 65 of the second switching circuit
When turned on, the voltage at the power input terminal 52 of the first switching circuit is equal to the readout voltage (3
At this point, the transistor 56 of _the first switching circuit is turned on.
Since it is ON, the output terminal 57 has an output GND potential, but when the transistor 55 turns ON, a photoelectric conversion unit readout voltage is generated at that point, and is added to the vertical transfer pulse amplitude as in the previous embodiment. Drive can be performed in the same manner even at pulse timings that are similar to the above. In the above description, regarding the switching operations of the first and second switching circuits,
Although we have explained only the ON or OFF of one transistor of a complementary transistor, we can tell you that in switching of such complementary transistors, when one transistor is ON, the other transistor is definitely OFF.

As can be seen from the circuit operation described above, the drive circuit of the present invention requires only a power supply voltage approximately half the maximum voltage of the three-level level, and the second switching circuit is used to control the photoelectric conversion section during the vertical blanking period. Since the switching operation is performed only when reading data, the power consumption is very low, and the power consumption is almost the same as that of conventional two-level drive, and the number of components can be minimized.

Note that although the present invention has been described for the case of two-phase drive, the present invention can be similarly implemented in a four-phase drive imaging device.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of an image sensor using an interline transfer method without a gate electrode for reading accumulated charges from a photoelectric conversion section, Fig. 2 is a potential schematic diagram showing the operation of the image sensor shown in Fig. 1, and Fig. 3 is a driving waveform applied to the vertical charge transfer register of the image sensor shown in FIG. 1, FIG. 4 is a block diagram of a conventional three-level drive circuit, and FIG. 5 is a three-level vertical charge transfer register according to the present invention. This is the drive circuit. In the figure, 11 is a photoelectric conversion unit, 12 and 13 are a group of vertical transfer electrodes, 14 is a vertical charge transfer register,
15 is a gate region, 22 and 23 are potentials during vertical transfer, 24 is a potential when reading out the photoelectric conversion section, 41 is a switching drive circuit, 42 is a power supply voltage switching circuit, 51 is a first switching circuit, 52 is a power input section, 53 is a power supply section, 54
is a diode, 55 and 65 are P channel enhancement MOS transistors, and 56 and 66 are N
channel enhancement MOS transistor,
57 is the output terminal of the first switching circuit, 61 is the second switching circuit, 62 is the power input section, 6
4 is a capacitor, and 67 is a second switching circuit.

Claims (1)

[Claims] 1. A plurality of vertical charge transfer register arrays each consisting of a plurality of photoelectric conversion sections arranged two-dimensionally on the same semiconductor substrate, vertical transfer electrode groups provided corresponding to the photoelectric conversion sections, and the photoelectric conversion sections. Charge transfer imaging comprising at least a gate region covered by the vertical transfer electrode group between a conversion unit and a corresponding vertical transfer electrode group, and a horizontal transfer register that sequentially reads parallel charges of the vertical charge transfer register array. The device drive circuit includes a first switching circuit that generates the pulse amplitude necessary for vertical transfer, and a pulse amplitude that is added to the vertical transfer pulse amplitude necessary for reading out the accumulated charge in the photoelectric conversion region. a second switching circuit for generating a signal, a diode whose cathode is the power input part of the first switching circuit and an anode which is the power supply side, and a diode connected between the output part of the second switching circuit and the cathode of the diode. 1. A drive circuit for a charge transfer image sensor, characterized in that the drive circuit comprises at least a capacitor, and an output end of the first switching circuit is a connection end to the vertical charge transfer register electrode.