JPH0118392B2 - - Google Patents

Description

[Detailed Description of the Invention] a. Technical Field of the Invention The present invention relates to a device for identifying the direction of arrival of ultrasonic signals arriving from various directions underwater. The present invention relates to a device that forms a received beam having directivity in one direction and changes the directivity direction of the received beam at high speed.

The applicant has filed a patent application for this type of device in 1982.
No. 121439 (Japanese Unexamined Patent Publication No. 126271/1983). The present invention improves this and realizes a more practical device.

b. Conventional Device Japanese Patent Application No. 57-121439 (Japanese Unexamined Patent Publication No. 59-126271) previously provided by the applicant will be explained.

In FIG. 1, Z ₁ to Z ₈ indicate ultrasonic transducers, which are arranged at regular intervals in a straight line, for example, 1/1/2 of the ultrasonic signal.
They are arranged at two wavelength intervals.

The received signals of each of the vibrators Z ₁ to Z ₈ are amplified by the respective preamplifiers PA ₁ to PA ₈ , and then guided to mixing circuits MX ₁ to MX ₈ provided correspondingly.

Each of the mixing circuits MX ₁ to MX ₈ separately performs mixing with the rectangular wave train read out from the memory circuit 1.
Note that the rectangular wave train is described in Japanese Patent Application No. 57-121439
59-126271), counter 2
A clock pulse source 4 is sent out from a frequency dividing circuit 3.
When counting pulse trains, the data is generated by reading the data at the memory address corresponding to the counted value. The memory circuit 1 has first to eighth output terminals, and each output terminal sends out stored data at a memory address corresponding to the count value of the counter in a binary value. The binary value data change is then used as a rectangular wave train. Further, this rectangular wave train data is latched into each of the latch circuits 601 to 608 by a latch pulse sent from the latch pulse generator 5.

The mixed outputs of the mixing circuits MX ₁ to MX ₈ are added in an adding circuit 7, and then a specific frequency signal is extracted by a filter 8. Therefore, the special application was filed in 1982.
As explained in No. 121439 (Japanese Unexamined Patent Publication No. 59-126271), ultrasonic transducer Z ₁ Of the received signals in each direction arriving at Z 8 to Z ₈ , a received signal in a specific direction can be sent out from the filter 8 . Furthermore, the phase of the rectangular wave train sent out from the memory circuit 1 is changed to a specific state. That is, by changing the frequency of the rectangular wave train, the direction of the received signal sent from the filter 8 can be changed.

The output signal of the filter 8 is amplified by an amplifier 9 and then led to a display 10 for display. The display 10 is, for example, a cathode ray tube display, and a scanner 11 scans the display screen. The scanner 11 performs a scanning operation at the same time as the transmitter 12 sends out a transmission pulse. This pixel scanning is performed in response to changes in the direction of the received signal sent from the filter 8. Therefore, on the display screen of the display 10, received signals arriving from each direction are displayed on pixels in the corresponding direction.

c. Disadvantages of the conventional device In FIG. 1, latch circuits 601 to 608
The phase precision of the rectangular wave train sent out from each of the rectangular wave trains is determined by the change in the count value of the counter 2 in one cycle of the rectangular wave train, and therefore by the number of memory addresses in the memory circuit 1 allocated to one cycle of the rectangular wave train. be done. That is, as the number of allocated addresses increases, the accuracy of the phase change of the rectangular wave train can be improved.

The accuracy of the phase change of the rectangular wave train is determined in consideration of the azimuth resolution of the received signal sent from the filter 8. Furthermore, the access time of the memory circuit 1 is limited by the period, that is, the frequency, of the rectangular wave train and the number of divisions of one period of the rectangular wave train.

For example, if the frequency of the rectangular wave train is set to 1 MHz and one period of the rectangular wave train is divided into 1/64 and stored, the time per section is 1 μsec for one period of the rectangular wave train.
Since it is 1/64 of , it becomes 1 μsec x 1/64 = 15.625 nsec.

Therefore, in this case, the memory circuit 1 cannot generate a 1 MHz rectangular wave train unless the access time is at least 15.625 nsec or more.

However, even the bipolar type memory circuits currently on the market, which are said to be the fastest, have an access time of 50 to 60 nsec. Therefore, it is impossible to generate a 1 MHz rectangular wave train as described above simply by reading data from the memory circuit.

d. Purpose of the invention This invention solves the above-mentioned drawbacks, and aims to make it possible to generate a rectangular wave train of 1 MHz as described above using a memory circuit with an access time of 50 to 60 nsec as described above. .

e Embodiment of the Invention In FIG. 2, parts with the same numbers as in FIG. 1 perform the same operations.

The pulse train sent out from the clock pulse source 4 is guided to the counter 2 via frequency divider circuits 13 and 14. The frequency dividing circuits 13 and 14 each have a frequency dividing ratio of 1/2.
For example, 1M in mixed circuit MX ₁ to MX ₈
When a Hz rectangular wave train is derived, and when the phase of the rectangular wave train is generated with an accuracy of 1/64 of one period as described above, the half period of the output pulse of the frequency dividing circuit 13 is
The clock frequency of the clock pulse source 4 is set to 15.625 nsec.

The output pulse of the frequency dividing circuit 13 (FIG. 3A) is further divided into 1/2 in the frequency dividing circuit 14 (the third
Diagram B) Guided to counter 2. The counter 2 is composed of, for example, 12 binary digits, and the count value changes at the fall of the output pulse B of the frequency dividing circuit 14. Therefore,
The counter 2 receives the output pulse B of the frequency dividing circuit 14.
Every time 4096 pieces are counted, the count value is incremented, and the count value is led to each of the memory circuits 161, 162, 163, and 164. The storage circuits 161 to 164 use read-only memories (ROM) and have 4096 storage addresses, and the stored data at the storage addresses corresponding to the count value of the counter 2 is read out at the same time.

Each of the storage circuits 161 to 164 stores phase data of mixed frequency signals guided to the mixing circuits MX ₁ to MX ₈ , similarly to the storage circuit 1 of FIG. The storage circuits 161 to 164 store storage data at the same storage address at different phase positions in order of half cycles of the output pulse A of the frequency dividing circuit 13. So, for example, 1MHz
When generating a mixed frequency signal of
1 to 164 send out stored data whose phase positions differ by 1/64 period of one period of the 1 MHz signal.
Further, the count value of the counter 2 changes every two cycles of the pulse wave A, that is, every 1/64×4=1/16 cycle of the 1MHz signal, and each of the memory circuits 161 to 164 changes the count value every two cycles of the pulse wave A, and therefore every 1/64×4=1/16 cycle of the 1MHz signal. Each memory address sequentially stores phase data for every /16 cycle.

Like the memory circuit 1 in FIG. 1, the memory circuits 161 to 164 send out eight types of memory data corresponding to each of the rectangular wave trains, that is, mixed frequency signals guided to the mixing circuits MX ₁ to MX ₈ . Output end 0 ₁
to ₀₈ . The storage outputs 0 ₁ to 0 ₈ of the storage circuits 161 to 164 are led to and latched by the respective latch circuits 171 to 174. Each of the latch circuits 171 to 174
Similar to the latch circuits 601 to 608 shown in the figure, they are configured to individually latch the storage outputs 0 ₁ to 0 ₈ of the storage circuits 161 to 164, respectively.

The latch circuits 171 to 174 are connected to the frequency divider circuit 14.
The inverted waveform of the output pulse B (FIG. 3) is led through the inverting circuit 18, and a latch operation is performed at the rising edge of the inverted waveform.

The stored data latched in latch circuits 171 to 174 are led to data selectors 151 to 158 by data bus 19. Each of the data selectors 151 to 158 has four input terminals,
Data at either input end is sent to the output end.

FIG. 4 shows a specific example of the data selectors 151 to 158, in which the AND circuits 191 to 194 transfer the data of the data input terminals Pr ₁ to Pr ₄ to the OR circuit 2.
0 to the output P ₀ . A control signal is led to the terminals S ₁ and S ₂ , and this control signal is sent to the inverting circuit 21.
AND circuit 1 via 1, 212, 221, 222
91 to 194 to make one of the AND circuits conductive. The output pulse A of the frequency dividing circuit 13 is applied to the terminal _S1 , and the output pulse A of the frequency dividing circuit 14 is applied to the terminal _S2 .
An output pulse B is derived. Therefore, when both inputs are at a low level, each output of the inverting circuits 211 and 221 is at a high level, thereby causing the AND circuit 1
91 is made conductive. Then, when the terminal S ₁ becomes high level and the terminal S ₂ becomes low level, the inverting circuit 21
The respective outputs of 2 and 221 become high level, and the AND circuit 192 becomes conductive. Similarly, when terminal S ₁ is at low level and terminal S ₂ is at high level, AND
When the circuit 193 is conductive and both terminals S ₁ and S ₂ are at high level, the AND circuit 194 is conductive.
Thereafter, in the same way, the AND circuits 191 to 194 are repeatedly turned on every half period of the output pulse A of the frequency dividing circuit 13, so that the data at the input terminals Pi ₁ to Pi ₄ are sequentially transferred to the output terminal P ₀ in time series. Sent from

Each input terminal Pi of data selectors 151 to 158
Of the memory outputs of the memory circuits 161 to 164 sent by the latch circuits 171 to 174 to Pi ₄ ,
Outputs sent out from output terminals with the same number are guided. That is, the input terminal of the data selector 151
The latch outputs of the first output terminals ₀₁ of the respective outputs of the memory circuits 161 to 164 are led to Pi ₁ to Pi ₄ .
Then, as described above, the first outputs 0 ₁ of the memory circuits 161 to 164 are sent out repeatedly in time series.

Similarly, the data selector 152 sends out the latch outputs of the second outputs 0 ₂ of the storage circuits 161 to 164 in time series. Furthermore, data selector 1
53 to 158 transmit the third to eightyth ₃ to ₀₈ of the memory circuits 161 to 164 in time series, respectively.

In the above, the data selector 151 converts the first output 0 ₁ of the memory circuits 161 to 164 into the frequency dividing circuit 1
The output pulse A is sent out in time series every half period of 1/64 μsec of the output pulse A of No. 3. Then, the memory circuits 161 to 16
When the first outputs 0 _{and 1} of 4 are sent out in sequence, the count value of the counter 2 changes at the falling edge of the output pulse B of the frequency dividing circuit 14, and the count value of the counter 2 changes and the memory circuits 161 to 164
The next memory address is specified. Since the count value of the counter 2 changes every two periods of the output pulse A of the frequency dividing circuit 13, 1/64 x 4 = 1/16 (μsec) = 62.5 (μsec), each of the memory circuits 161 to 164 has a period of 62.5 nsec. The memory address is specified in order for each. Therefore, the memory circuits 161 to 164 can read the stored data at each memory address with sufficient stability if the access time is 50 nsec or less. And 1MHz from data selector 151
When transmitting the received signal, the memory addresses of the memory circuits 161 to 164 are designated every 62.5 μsec, so it is sufficient to store the phase data of the 1 MHz rectangular wave train every 62.5 nsec. Furthermore, since the data stored in the memory circuits 161 to 164 is sent out in time series at an interval of 1/64 μsec = 15.625 nsec, the data stored in the memory circuits 161 to 164 is stored every 62.5 nsec.
By storing the phase data of the Hz rectangular wave train while varying it by 16.625 nsec, the rectangular wave train sent from the data selector 151 can be sent out with a phase accuracy of 16.625 nsec.

The data selectors 152 to 158 are also similar to the above, and the memory circuit 161 is read every 62.5 nsec.
By transmitting the 164 stored data in time series every 16.625nsec, a 1MHz rectangular wave train can be generated.
Sends with a phase accuracy of 16.625nsec.

From each of the data selectors 151 to 158,
Each of the rectangular wave trains sent out as described above is guided to mixing circuits MX ₁ to MX ₈ and then sent to an ultrasonic transducer Z _1.
It is mixed with the received signals of Z to Z. Thereafter, a directional receiving beam is formed in the same manner as in FIG.

f. Effects of the Invention As explained above, the phase data of the rectangular wave train to be generated is stored in a plurality of storage circuits at intervals longer than the access time of the storage circuits, and the data stored in each storage circuit is transmitted in time series. By doing so, it is possible to generate a rectangular wave train with a phase accuracy equal to or less than the access time of the memory circuit.

[Brief explanation of drawings]

FIG. 1 shows a conventional example, FIG. 2 shows an embodiment of the present invention, FIG. 3 is a waveform diagram for explaining its operation, and FIG. 4 shows a specific example of the data selector. 2...Counter, 4...Clock pulse source,
7... Addition circuit, 8... Filter, 9... Amplifier, 10... Display, 11... Scanner, 12...
Transmitter, 13, 14... Frequency dividing circuit, 151 to 1
58...Data selector, 161 to 164...
Memory circuit, 171 to 174...Latch circuit, 1
8... Inverting circuit, 191 to 194... AND circuit, 20... OR circuit, 211, 212... Inverting circuit, Z ₁ to Z ₈ ... Ultrasonic receiver, PA ₁ , PA ₈ ...
...Preamplifier, MX ₁ to MX ₈ ...Mixed circuit.

Claims (1)

[Scope of Claims] 1. A first ultrasonic transducer in which at least first and second ultrasonic transducers are arranged, and each received signal and phase of the first and second ultrasonic transducers are controlled over time; A device that forms a directional reception beam whose pointing direction sequentially changes by separately mixing the second frequency signals and extracting a specific frequency signal from the summed signal of the mixed frequency signals. First and second frequency signal generators that generate the first and second frequency signals; and a first frequency signal generator generated by the first frequency signal generator.
a first mixing circuit that mixes the frequency signal of the frequency signal and the received signal of the first ultrasonic transducer; and a second frequency signal generated by the second frequency signal generator and the second a second mixing circuit that mixes the received signal of the ultrasonic transducer; an addition circuit that adds together the mixed outputs of the first and second mixing circuits; and a specific frequency from among the outputs of the addition circuit. and a filter circuit for extracting a signal, each of the first and second frequency signal generators being configured with first to Kth (K=2, 3, 4...) storage circuits, Each of the first to Kth memory circuits has a storage capacity of n addresses, and the data stored in the same address of each memory circuit is simultaneously read out and latched in the first to Kth latch circuits. After the latched data is sent out in chronological order, the stored data at the next storage address of each of the storage circuits is simultaneously read out and latched. Device.