JPH0118594B2 - - Google Patents
Info
- Publication number
- JPH0118594B2 JPH0118594B2 JP58118697A JP11869783A JPH0118594B2 JP H0118594 B2 JPH0118594 B2 JP H0118594B2 JP 58118697 A JP58118697 A JP 58118697A JP 11869783 A JP11869783 A JP 11869783A JP H0118594 B2 JPH0118594 B2 JP H0118594B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- dry film
- film layer
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は多層配線基板の改良、特に微細化加工
に適した多層配線基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in multilayer wiring boards, and particularly to a method for manufacturing multilayer wiring boards suitable for miniaturization.
(ロ) 従来技術
従来の多層配線基板の製造方法では第1図に示
す多層配線を実現するには第2図の如く、セラミ
ツク等の絶縁基板1上に銅箔等の第1の導電パタ
ーン2を形成し、その上に絶縁材料を2度スクリ
ーン印刷して十分に厚くした絶縁物層3を設け、
更にその上に第2の導電パターン4を形成して構
成していた。(b) Prior Art In the conventional manufacturing method of a multilayer wiring board, in order to realize the multilayer wiring shown in FIG. 1, as shown in FIG. is formed, and an insulating material layer 3 made sufficiently thick by screen-printing an insulating material twice is provided thereon,
Further, a second conductive pattern 4 was formed thereon.
斯上の構造では第1の導電パターン2と第2の
導電パターン4の接続部は絶縁材料のスクリーン
印刷時に選択的に窓5を形成して両者を接触でき
る様にしている。しかしながら絶縁材料は有機溶
剤でペースト状としてスクリーン印刷するので、
窓5のエツヂが鮮明に印刷できず第2図の如く内
側ににじみが発生して窓5がつぶされる危惧があ
つた。このため窓5をにじみを考慮して十分に大
きく、例えば直径300μに形成していた。この結
果第1の導電パターン2および第2の導電パター
ン4はこの大きさの窓5を形成できるだけ十分に
離間させる必要があり、微細化パターン加工の障
害となつていた。 In the above structure, a window 5 is selectively formed at the connection portion between the first conductive pattern 2 and the second conductive pattern 4 during screen printing of the insulating material so that the two can come into contact with each other. However, since the insulating material is screen printed as a paste using an organic solvent,
The edges of the window 5 could not be printed clearly, and as shown in Figure 2, there was a risk that the window 5 would be crushed due to bleeding inside. For this reason, the window 5 is formed to be sufficiently large, for example, 300 μm in diameter, in consideration of bleeding. As a result, the first conductive pattern 2 and the second conductive pattern 4 must be spaced apart from each other sufficiently to form a window 5 of this size, which has been an obstacle to fine pattern processing.
(ハ) 発明の目的
本発明は斯点に鑑みてなされ、従来の欠点を完
全に除去した極めて微細化加工に適した多層配線
基板の製造方法を提供するものである。(c) Object of the Invention The present invention has been made in view of the above, and provides a method for manufacturing a multilayer wiring board that completely eliminates the conventional drawbacks and is suitable for extremely fine processing.
(ニ) 発明の構成 本発明は以下の各工程より構成される。(d) Structure of the invention The present invention is comprised of the following steps.
(1) 絶縁基板上に第1の導電パターンを形成する
工程。(1) A step of forming a first conductive pattern on an insulating substrate.
(2) 第1の導電パターン上にドライフイルム層を
選択的に付着する工程。(2) selectively depositing a dry film layer on the first conductive pattern;
(3) 第1の導電パターンを被覆する絶縁物層を基
板上に形成する工程。(3) A step of forming an insulating layer covering the first conductive pattern on the substrate.
(4) ドライフイルム層を除去しスルーホールを形
成する工程。(4) Step of removing the dry film layer and forming through holes.
(5) 絶縁物層上に第2の導電パターンを形成し且
つスルーホールで第1の導電パターンと接続す
る工程。(5) A step of forming a second conductive pattern on the insulating layer and connecting it to the first conductive pattern through a through hole.
(ホ) 実施例
本発明の第1の工程は第3図Aに示す如く、絶
縁基板11上に第1の導電パターン12を形成す
ることにある。絶縁基板11としてはセラミツク
スあるいは表面を酸化膜で被覆したアルミニウム
等を用い、第1の導電パターン12は基板11に
全面に銅箔を貼着した後所望のパターンにエツチ
ングして形成される。(E) Embodiment The first step of the present invention is to form a first conductive pattern 12 on an insulating substrate 11, as shown in FIG. 3A. The insulating substrate 11 is made of ceramics or aluminum whose surface is coated with an oxide film, and the first conductive pattern 12 is formed by attaching copper foil to the entire surface of the substrate 11 and then etching it into a desired pattern.
本発明の第2の工程は第3図Bに示す如く、第
1の導電パターン12上にドライフイルム層13
を選択的に付着することにある。ドライフイルム
層13としてはホトレジストをフイルム状に加工
したものを用い、基板11上に約80〜100℃で熱
圧着した後、周知の写真蝕刻法により第1の導電
パターン12上のスルーホールを形成する予定部
分上に残存される。本工程では写真蝕刻法を用い
るのでスルーホールの直径は約80μ程度まで微細
加工できる。 In the second step of the present invention, as shown in FIG. 3B, a dry film layer 13 is formed on the first conductive pattern 12.
The purpose is to selectively attach. As the dry film layer 13, a photoresist processed into a film shape is used, and after thermocompression bonding on the substrate 11 at about 80 to 100°C, through holes are formed on the first conductive pattern 12 by a well-known photolithography method. will be left on the intended part. Since this process uses photolithography, the diameter of the through hole can be finely processed to about 80μ.
本発明の第3の工程は第3図Cに示す如く、第
1の導電パターン12を被覆する絶縁物層14を
基板11上に形成することにある。絶縁物層14
としてポリイミドを用い、スルーホールを形成す
るドライフイルム層13よりやや大きい領域を残
して基板11全面にポリイミドを2回刷りしてピ
ンホールの防止と十分な膜厚を確保している。具
体的には乾燥後30〜40μ厚ぐらいになる様にスク
リーン印刷し、またにじみによりドライフイルム
層13端部まで絶縁物層14は形成できる。 The third step of the present invention is to form an insulating layer 14 on the substrate 11, covering the first conductive pattern 12, as shown in FIG. 3C. Insulator layer 14
Polyimide is used as the substrate, and polyimide is printed twice over the entire surface of the substrate 11, leaving an area slightly larger than the dry film layer 13 where through holes are formed, to prevent pinholes and ensure a sufficient film thickness. Specifically, the insulator layer 14 can be formed up to the ends of the dry film layer 13 by screen printing so as to have a thickness of about 30 to 40 μm after drying, and by bleeding.
本発明の第4の工程は第3図Dに示す如く、ド
ライフイルム層13を除去しスルーホール15を
形成することにある。本工程では有機溶剤を用い
てドライフイルム層13のみを選択的に除去す
る。なおポリイミドは有機溶剤に不溶であるの
で、ドライフイルム層13と同一形成の微細なス
ルーホール15を形成できる。 The fourth step of the present invention is to remove the dry film layer 13 and form through holes 15, as shown in FIG. 3D. In this step, only the dry film layer 13 is selectively removed using an organic solvent. Note that since polyimide is insoluble in organic solvents, fine through holes 15 having the same structure as the dry film layer 13 can be formed.
本発明の最終工程は第3図に示す如く、絶縁物
層14上に第2の導電パターン16を形成し且つ
スルーホール15で第1の導電パターン12と接
続することにある。本工程ではスルーホール15
を含む絶縁物層14全面に銅あるいはニツケルの
無電界ニツケルメツキにより銅あるいはニツケル
メツキ層を形成後、所望の形状にエツチングして
第2の導電パターン16を形成する。従つて第2
の導電パターン16はスルーホール15にも同時
に形成されるメツキ層によつて第1の導電パター
ンと接続されている。 The final step of the present invention is to form a second conductive pattern 16 on the insulating layer 14 and connect it to the first conductive pattern 12 through a through hole 15, as shown in FIG. In this process, the through hole 15
A copper or nickel plating layer is formed on the entire surface of the insulating layer 14 by electroless plating of copper or nickel, and then etched into a desired shape to form the second conductive pattern 16. Therefore, the second
The conductive pattern 16 is connected to the first conductive pattern by a plating layer which is also formed at the same time in the through hole 15.
(ヘ) 発明の効果
本発明に依ればドライフイルム層13を用いる
ことによつて写真蝕刻法による微細加工精度によ
りスルーホール15が形成できるので、第1の導
電パターン12の巾を従来の300μから100μ程度
に狭めることができる。これにより多層配線基板
の実装密度を大巾に向上でき、電子部品の高密度
化が実現できる。(F) Effects of the Invention According to the present invention, by using the dry film layer 13, the through-holes 15 can be formed with fine processing precision by photolithography, so that the width of the first conductive pattern 12 can be reduced to 300 μm compared to the conventional width. The width can be narrowed from 100μ to about 100μ. As a result, the mounting density of the multilayer wiring board can be greatly improved, and the density of electronic components can be increased.
第1図は一般的な多層配線基板を説明する上面
図、第2図は従来構造の多層配線基板を説明する
第1図A−A線断面図、第3図A乃至第3図Eは
本発明による多層配線基板の製造方法を説明する
断面図である。
11は絶縁基板、12は第1の導電パターン、
13はドライフイルム層、14は絶縁物層、15
はスルーホール、16は第2の導電パターンであ
る。
Fig. 1 is a top view illustrating a general multilayer wiring board, Fig. 2 is a sectional view taken along line A-A in Fig. 1 illustrating a multilayer wiring board with a conventional structure, and Figs. 3A to 3E are main views. FIG. 2 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the invention. 11 is an insulating substrate, 12 is a first conductive pattern,
13 is a dry film layer, 14 is an insulating layer, 15
16 is a through hole, and 16 is a second conductive pattern.
Claims (1)
工程、該第1の導電パターン上にドライフイルム
層を選択的に付着する工程、前記第1の導電パタ
ーンを被覆する絶縁物層をスクリーン印刷で前記
基板上に形成する工程、前記ドライフイルム層を
完全に除去しスルーホールを形成する工程、前記
絶縁物層上に第2の導電パターンを形成し且つ前
記スルーホールで前記第1の導電パターンと接続
する工程とを具備することを特徴とする多層配線
基板の製造方法。1 forming a first conductive pattern on an insulating substrate, selectively attaching a dry film layer on the first conductive pattern, and forming an insulating layer covering the first conductive pattern by screen printing. a step of forming a second conductive pattern on the substrate, a step of completely removing the dry film layer to form a through hole, and forming a second conductive pattern on the insulating layer and connecting the first conductive pattern with the through hole. 1. A method for manufacturing a multilayer wiring board, comprising the step of connecting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11869783A JPS6010697A (en) | 1983-06-29 | 1983-06-29 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11869783A JPS6010697A (en) | 1983-06-29 | 1983-06-29 | Method of producing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010697A JPS6010697A (en) | 1985-01-19 |
| JPH0118594B2 true JPH0118594B2 (en) | 1989-04-06 |
Family
ID=14742913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11869783A Granted JPS6010697A (en) | 1983-06-29 | 1983-06-29 | Method of producing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010697A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3863502B2 (en) | 2003-05-19 | 2006-12-27 | 株式会社コナミデジタルエンタテインメント | Deformed toy |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56118395A (en) * | 1980-02-23 | 1981-09-17 | Tokyo Shibaura Electric Co | Method of forming multilayer wire |
| JPS5817696A (en) * | 1981-07-23 | 1983-02-01 | 日立化成工業株式会社 | Method of producing multilayer printed circuit board |
| JPS59115589A (en) * | 1982-12-22 | 1984-07-04 | 富士通株式会社 | Method of forming stereoscopic wiring |
-
1983
- 1983-06-29 JP JP11869783A patent/JPS6010697A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6010697A (en) | 1985-01-19 |
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