JPH0118624B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile receiving apparatus comprising a sampling pulse adjustment circuit.

In recent years, a thermal recording method has been widely used as a facsimile recording method because the equipment is easy to maintain and paper costs are low. In thermal recording, two-tone recording, that is, white or black binary image recording is usually performed.

On the other hand, the AM-PM-VSB adopted in the G standard recommended by the CCITT (International Telegraph and Telephone Consultative Committee)
(Amplitude Modulation−Phase Modulation−
In the case of analog transmission methods, such as Vestigial Side Band (abbreviation for Vestigial Side Band), the image signal detected and reproduced on the receiving side is an analog signal. Therefore, in order to record a binary image on the receiving side, it is necessary to sample the analog signal and convert it into a binary image signal.

The manner in which jitter appears in the received image due to the above operation will be explained using FIG.

FIG. 1a shows the waveform of the image signal sending clock 1 on the transmitter side, and FIG. 1b shows the waveform of the image signal 2 to be sent out. A high level "1" indicates a self-portrait, and a low level "0" indicates a black image. The image signal 2 is formed in synchronization with the rise of the sending clock 1, and is then sequentially modulated and sent out as a facsimile signal to the telephone line. FIG. 1c shows an analog image signal 3 obtained by detecting and demodulating an input facsimile signal in a receiver. 4 indicates a threshold voltage for converting the analog image signal 3 into a white or black binary image signal. The analog image signal 3 fluctuates as shown by waveforms 3a to 3b due to band limitations of the line, filters, noise, and the like. Therefore, the binary signal sliced by the threshold voltage 4 is represented by the binary signal 5 shown in FIG. 1d. Then, it is varied as shown by waveforms 5a, 5b, 5c, and 5d. The binary signal 5 corresponds to the rising edges 6a and 6b of the sampling pulse 6 of the receiver shown in FIG. 1e.
When sampled at , the binary image signal 7 shown in FIG. 1f is obtained. However, if the binary image signal 5 has jitter of waveforms 5b and 5d, the image signal 7 after sampling becomes waveforms 7b and 7d, and an image 8 containing jitter as shown in FIG. 1g is recorded. be done. The image 8 is originally formed by the binary image signal 7,
The line image 8a should appear to be continuous vertically, but images 8b, 8c, etc. are formed due to jitter such as waveforms 7b and 7d, so the left and right boundaries of the image as a whole are not aligned. .

In conventional facsimile receivers, the timing of the sampling pulse is fixed, so the
When the analog image signal 3 fluctuates as shown in FIG. 1, the jitter shown in FIG. 1g inevitably occurs. Furthermore, the transmitter's output clock 1 and the receiver's sampling pulse 6 are set to approximately the same frequency, but have independent phase relationships. Therefore, due to a slight frequency error between the sending pulse and the sampling pulse, the phase changes over time between 0 and 2π. For this reason, the jitters mentioned above were unavoidable. The facsimile receiving device of the present invention binarizes the received analog image signal and adjusts the timing of the received sampling pulse using the change points included in the binarized signal, thereby obtaining an image with less jitter. This is how it was done.

An embodiment of the present invention will be described below with reference to the drawings. Figures 2a to 2c show the principle for removing the jitter. FIG. 2 shows a signal 9 obtained by binarizing the received analog image signal, and the first
This corresponds to the binary signal 5 in Figure d. In the binary signal 9, the time position at which the white level changes to the black level varies as shown by waveforms 9a to 9c due to the influence of the line and filter. At this time, the probability of occurrence of a change point in the binarized signal 9 is considered to be distributed as shown in FIG. 2b with respect to time t. Therefore, if sampling is performed at the rising edges 10a and 10c (adjacent sampling times) of the waveform of the sampling pulse 10 shown in FIG. It is only necessary to adjust the phase of the sampling pulse 10 so that the falling part 10b of the waveform of the sampling pulse 10 is located.

FIG. 3 shows an embodiment of the present invention using the above-mentioned G standard, and is a block diagram showing the electrical circuit of the receiver.

The operation of each part will be explained below along the flow of received facsimile signals. In FIG. 3, a received facsimile signal input from a telephone line 11 is filtered through a bandpass filter 12 to cut out unnecessary frequency components.
Pass through. In addition, the input level of the facsimile signal from line 11 is 0 to -40 dBm depending on the line condition.
Since the degree changes, the automatic gain control circuit 13 (hereinafter
AGC circuit), even if the input level fluctuates,
The gain is controlled so that the maximum amplitude (white level in this case) of the analog image signal detected and reproduced inside the receiver is always constant. The output of the AGC circuit 13 is connected to the carrier regeneration circuit 14 and the multiplier 1.
5, and the output of the carrier regeneration circuit 14 is sent to the multiplier 15, so the multiplier 15 multiplies the regenerated carrier and the received signal to perform synchronous detection. The output of the multiplier 15 is input to a low-pass filter 16 to remove unnecessary high frequency components generated by the synchronous detection. Since the output of the low-pass filter 16 is a ternary analog image signal whose polarity is inverted every time a white signal appears, it is rectified by the full-wave rectifier circuit 17. Here, FIG. 4a is G
This is a signal for one line in the mode. Fourth
FIG. 4B corresponds to FIG. 4A, and shows the waveform of the full-wave rectified analog image signal 26 (the signal output from the signal line 17a). In the G mode, one line of signals consisting of the synchronization signal 25a and the image signal 25b is transmitted in 1/6 seconds, and the synchronization signal 25a at the beginning of each line has a length of 6.5 to 10 msec. The waveform of the synchronization signal 25a is a white level signal 26a, that is, a carrier with maximum amplitude, and its phase is inverted at its terminal end 26b, forming a signal change point. The analog image signal 26 shown in FIG. 4b is input to the slicer 18 and AGC circuit 13 shown in FIG. Signal binarized by the slicer 18 (the terminal end 26b and the low level "black" of the image signal may be sliced at different levels)
is input to the line memory 20 from the signal line 19a via the signal line 18a and the sampling circuit 19, and is stored therein, and then sequentially sent to the printer unit 21 to be recorded as a binary image. A binary signal is input from the slicer 18 or further from the signal line 18a to the sampling pulse adjustment circuit 22 (the main block of the present invention). The sampling pulse adjustment circuit 22 is a circuit that generates a sampling pulse to be supplied to the sampling circuit 19 from the signal line 22a. The clock generator 23 is a sampling pulse adjustment circuit 22.
A clock signal used in the synchronization timing generation circuit 24 is generated and output from signal lines 23a and 23b, respectively. The synchronous timing generation circuit 24 is G
Create mode synchronization timing. According to the CCITT standard, in G-mode communication, the phases of the synchronization timing generation circuits of the transmitter and receiver are matched before starting image transmission and reception. Therefore, the synchronization timing generating circuit 24 of the receiver generates a sampling pulse, that is, the signal 40 shown in FIG. Signal line 24a
Output to. In the configuration shown in FIG. 3, the signal outputted from the sampling pulse adjustment circuit 22 via the signal line 22a corresponds to the signal 10 shown in FIG.
The signal input to signal 9 corresponds to signal 9 shown in FIG. 2a. As explained in FIGS. 2a to 2c, the structure is such that jitter is minimized.

FIG. 5 shows one specific embodiment of the sampling pulse adjustment circuit 22, and FIGS.
It shows the waveforms of signals passing through each signal line shown in the figure and their mutual timing.

The operation will be explained below using FIG. 5 and FIGS. 6 a to 6. The high level of the waveforms in FIGS. 6a to 6j is set to "1", and the low level is set to "0". Signal line 2 from clock generator 23 (Figure 3)
The clock signal input via 3a is shown in Figure 6a.
This can be shown by the signal 38. and signal line 38
Let the frequency of be φ. In FIG.
8 is input to a 4-bit binary counter 27 and a flip-flop 34. The input parts P ₁ to _{P 4} of the 4-bit binary counter 27 receive P ₁ in the normal interval.
=P ₂ =P ₃ =0, P ₄ =1, that is, "8" is applied in decimal notation. Also, the carrier signal 46 shown in Figure 6i is sent from the carrier terminal CR to the load terminal.
It is input to LD. The carrier signal 46 is the sixth
The waveform rises at "15" shown in the count signal 39 in Figure b, and the binary counter 27
As shown in the normal section 39a, an 8 frequency divider circuit is formed that counts from "8" to "15". As a result, the frequency of the signal output from the output section QC of the binary counter 27 becomes φ/8. The waveform of the signal outputted from the output section QC to the signal line 27a is as shown in the signal 44 in FIG. 6g. On the other hand, a signal 40 having a waveform shown in FIG. 6c from the synchronous timing generation circuit 24 (FIG. 3) via the signal line 24a operates the monomulti 31. The monomulti 31 detects the rising edge 40a of the waveform of the signal 40 and outputs the signal 41 shown in FIG. 6d from the signal line 31a. That is, the signal 41 detects the rising portion 40a of the signal 40 to form the falling portion 41a of the signal 41, and the rising portion 41a is formed approximately 2 msec after the falling portion 41a.
b. The setting of approximately 2 msec is intended to prevent malfunctions due to timing differences in synchronization signals during transmission and reception. The flip-flop 32 receives the signal 41, detects the rising edge 41b of the waveform of the signal 41, and detects the rising edge 41b of the waveform of the signal 41.
A signal 42 is outputted from the signal 32a. In other words,
The signal 42 forms a falling part 42a by detecting a rising part 41a of the signal 41, and forms a rising part 42b by detecting a rising part 47a of the waveform of a signal 47, which will be described later. When the signal outputted from the output section of the flip-flop 32, ie, the signal 42 in FIG. 6e, becomes a low level "0", the flip-flops 28 and 29 to which the signal 42 is input via the signal line 32a are enabled. Signal line 1
The signal that passes through the signal line 35a with its phase reversed by the inverter 35 via the signal line 35a is the signal 4 shown in FIG. 6f.
It is 3. The signal 43 is connected to the slicer 18 shown in FIG. 3 by the terminal 26b of the synchronization signal shown in FIG.
The signal is binarized by the inverter 35 and reversed in phase by the inverter 35 as described above, and the period of the sampling pulse is adjusted only once per line. flipflop 2
8 and 29 input the signal 43 from the signal line 35a and the signal 44 from the signal line 27a (or 22a), so the level of the signal 44 is "1".
Either flip-flop 28 or 29 is set depending on whether the flag is "0" or "0". Flip-flops 28 and 29 form a phase comparison circuit for comparing phases. At the rising edge 43a of the waveform of the signal 43 in FIG. 6f, the signal 43 is "1",
The signal 44 becomes "0". The signal 43 "1" is transferred from the signal line 35a to the flip-flop 28.
and 29, and the "0" of the signal 44 is the signal 27a.
is input to the input section D of the flip-flop 29. Furthermore, since the "0" signal 44 is input to the inverter 36 from the signal line 27a, the "1" signal output from the inverter 36 is sent to the input section of the sampling circuit (FIG. 3) and the flip-flop 28 via the signal line 22a. Enter in D. Therefore, from the output Q of the flip-flop 28, the signal 4 shown in FIG.
5, the rising edge 45a of the waveform, that is, the signal "1" is output to the signal line 28a, and the flip-flop 2
A signal of "0" is sent from the output part Q of 9 to the signal line 29a.
Then, a signal of "1" is sent from the output section to the signal line 29b.
Output each. The OR circuit 30 inputs a signal of "1" from the signal line 28a and a signal of "0" from the signal line 29a, and outputs a signal of "1" to the signal line 30a. On the other hand, 4-bit shift register 2
7 input parts P ₁ , P ₂ , P ₃ , P ₄ are each connected to signal line 3
0a, 29a, 29a, and 29b, so the input parts P ₁ to _{P 4} have P ₁ = P ₄ = 1, P ₂ = P ₃
=0, that is, "9" is applied in decimal notation. Therefore, in the count signal 39 shown in FIG. 6b,
While the normal section 39a started from "8", the adjustment section 39b started from "9",
Switches to a divide-by-7 circuit that counts from "9" to "15". Therefore, this adjustment section 39b becomes a 7 frequency division counter, and the output line 27a is connected from the output part QC of the binary counter 27 (that is, it becomes a variable frequency division circuit).
or flip-flop 28,2 via 22a
The signal 44 shown in FIG. Therefore, the rising portion 4 of the signal 44 in the next section (the adjustment section 39b)
4a acts to approach the rising edge 43a of the signal 43 by 1/φ. This is a binary counter 27
becomes 1 depending on the value of the signal input to input parts P ₁ to _{P 4}
This is because the sampling pulse is switched only once per line in the range of 8±1 frequency division, and the period of the sampling pulse is adjusted by ±1/φ. Next, binary counter 2
From the carrier terminal CR of No. 7, the carrier signal 46 shown in FIG. The signal 47 in FIG. 6j becomes "1" at the rising edge 47a.
When the signal becomes , the AND circuit 33 opens,
The flip-flop 32 is reset via the signal line 33a. As a result, the signal 42 shown in FIG.
Reset 9. And this state is signal line 2
4a until the next synchronization timing pulse 40a is input. The signal outputted from the signal line 22a changes the phase of the signal 44 to the inverter 3.
6, it corresponds to Fig. 2 a to c, and the falling edge of the sampling pulse waveform is aligned at time Tmax when the change point of the binary signal shown in Fig. 2 b is most likely to occur. It can be adjusted as follows.

In the above embodiments, the timing of the sampling pulse is adjusted once per line, but it is not necessary to adjust the timing of the sampling pulse once per line. However, compared to the black signal at the terminal end 26b of the synchronizing signal shown in FIG. 4b, the generation timing of the black signal in the image signal varies more greatly depending on the preceding and succeeding image signals, so it is not suitable for use in adjusting the sampling pulse. It is thought that this is not the case.

Further, although the present embodiment has been described assuming _G2 mode communication, the present invention can also be used in other modes, such as a transmission method using white block skips. In this case as well, it is sufficient to use a stable black signal of the image signal, for example, a synchronization signal whose structure includes the black signal as a part thereof.
In this case, the signal after the black signal can also be made constant, which further improves the effect. Further, one aspect of the present invention is based on the principle shown in FIGS. 2a to 2c, that is, the sampling pulse is adjusted so that approximately the middle of adjacent sampling times coincides with the temporal position where the probability of occurrence of a change point of the image signal is highest. The purpose is to adjust the phase. Of course, it can be realized using a circuit configuration other than that described in the embodiment or a microcomputer or the like in which the principle of FIG. 2 is implemented as software.

[Brief explanation of drawings]

FIG. 1a is a waveform diagram of the image signal sending clock on the transmitter side, FIG. 1b is a waveform diagram of the image signal sent from the transmitter side, and FIG. 1c is a waveform diagram of the analog image signal on the receiver side. Figure 1 d is a waveform diagram of the binarized analog image signal, Figure 1 e is a waveform diagram of the sampling pulse on the receiver side, and Figure 1 f is the binarized signal of Figure 1 d. Figure 1g is a plan view of the image formed by the signal in Figure 1f, Figure 2a is a waveform diagram of the binarized signal, Figure 2a is a waveform diagram of the signal obtained by sampling with the sampling pulse of Figure 2b is a graph showing the distribution of the probability of occurrence of the change point of the binary signal shown in Figure 2a, Figure 2c is a waveform diagram showing sampling pulses, and Figure 3 is a facsimile diagram of this embodiment. Fig. 4a is a block diagram showing the electrical circuit of the receiving device; Fig. 4a is a block diagram showing a signal for one line; Fig. 4b is a waveform diagram of a full-wave rectified analog image signal; Fig. 5 6 is a circuit configuration diagram showing an embodiment of the sampling adjustment circuit used in the facsimile receiver of the present invention, and FIGS. 6 a to 6 j show the waveforms and mutual timings of signals passing through each signal line of the circuit shown in FIG. In the waveform diagram shown, 12... band filter, 13
...AGC circuit, 14 ...Carrier regeneration circuit, 1
5... Multiplier, 16... Low-pass filter, 17... Full wave rectifier circuit, 18... Slicer, 19... Sampling circuit, 20... Line memory, 21... Printer section, 22... Sampling pulse adjustment circuit , 23... Clock generator, 24... Synchronous timing generation circuit, 27... 4-bit binary counter, 28, 29, 32, 34... Flip-flop, 31... Monomulti, 30... OR circuit,
33...AND circuit, 35, 36...inverter.

Claims (1)

[Claims] 1. A demodulation circuit that detects and demodulates a received signal; 2. That binarizes the signal demodulated by the demodulation circuit.
A facsimile receiving device comprising: a digitization circuit; a generation circuit that generates a sampling pulse for sampling the output binary signal of the binarization circuit; and a phase adjustment circuit that adjusts the phase of the sampling pulse; , a detection unit that detects the timing at which a change point of the output binary signal occurs during one cycle of the sampling pulse;
adjusting the phase of the sampling pulse so that the value signal is sampled at appropriate timing;
It consists of an adjusting section that adjusts the phase of the sampling pulse back and forth for a sufficiently short period of time with respect to the period of the sampling pulse for each adjustment according to the timing detected by the detecting section, and the first half of one period of the sampling pulse. If the changing point is detected at a timing of A facsimile receiving device characterized by shifting the phase of .