JPH0119168B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift register control device for a sequence controller having a shift register instruction for shifting a fixed length shift register by one bit.

When executing a shift register instruction by connecting unit-length shift registers in series, conventional sequence controllers require that each register's input conditions (reset, clock, shift input data) be programmed individually and then indirectly connected in series. Was.

FIG. 1A shows a ladder diagram of a conventional shift register control device, and FIG. 1B shows a program for controlling the same. This sequence controller that performs a scanning operation first executes a load instruction (LOD) to take in the reset signal, clock, and final bit data of shift register 0 (8 bits), and then issues a shift register instruction (LOD) for shift register 1. Execute SFT1). Next, the load instruction is executed again to take in the reset, signal, clock, and input data, and the shift register instruction (SFT0) for shift register No. 0 is executed. By the above operation, 0
Shift register No. 1 is connected to shift register No. 1 and performs shift control of the 16-bit shift register.

However, the above-mentioned shift register control device requires a program of eight steps in total, and has the disadvantage that the program becomes extremely complicated when a large number of such multiple connected registers are required to be controlled.

An object of the present invention is to provide a shift register control device that only requires setting input conditions to the first shift register when connecting a plurality of unit length registers.

In summary, the present invention provides a logic operation register that stores logic operation results or input data, which is generally used in a control section of a sequence controller.
An overflow bit is set when a shift register instruction is executed, so that the next shift register instruction is executed using the set overflow bit as direct shift input data without setting an input condition again. Furthermore, the contents of a stack register in which input conditions such as a clock and a reset signal are already stacked can be used as they are as input conditions for the next shift register command.

The shift register control method according to the present invention will be explained below with reference to the drawings.

FIG. 2 is a block diagram of a sequence controller control section implementing the present invention.

In the figure, a user's RAM 3 stores a user program, and a work RAM 4 has an input state buffer 40 and a unit length (8-bit) shift register 41 (plurality). The output port 5 and input port 6 are connected to an output module and an input module (not shown) via an IO bus. The output port 7 supplies a logical operation result or input data to a 1-bit logical operation register 8, and also supplies a shift clock to an 8-bit stack register 9. The input port 10 is connected to the logic operation register 8.
or each stage output of the stack register 9. The stack register 9 is an 8-level register in which the contents of the logical operation register 8 are stacked when a load instruction is executed.

Next, the contents of the shift register instruction execution operation when unit length shift registers are connected in series will be explained.

FIG. 3A shows a ladder diagram, and FIG. 3B shows a program.

Execution of the instruction starts from address 0 of the program and ends
A scan operation is performed up to the N address where the instruction is written. When operation starts, the state of the input module is first read from the input port 6 via the IO bus. The read input state is set in the input state buffer 40 of the work RAM 4. Execution of the instruction at address 0 starts from this state.

In the load instruction (LOD) at address 0, the data at input number 0 is set in the logical operation register 8.
If this data is "on", the 0th shift register is reset by the 0th shift register instruction, which will be described later. In the next load instruction, the data of the first input is set in the logical operation register 8. Also, at this time, when the instruction at address 0 is executed, the logic operation register 8
The 0th input data that was set in is pushed into the stack register 9. The first input data is
When changing from "off" to "on", it becomes the shift register clock. Similarly, the load instruction at address 2 sets the data at the input at number 2 in the logical operation register 8 and executes stacking.
As a result, the 2nd input data is set in the logic operation register 8, the 1st input data is set in the 0th stage (level 0) of the stack register 9, and the 0th input data is set in the 1st stage (level 1). The data will be set.

4A, B, and C show the contents of the logical operation register 8 and stack register 9 after execution of the load instructions at addresses 0, 1, and 2, respectively. Note that in the figure, the symbol * indicates unspecified content remaining from the previous instruction.

When the above load instruction is executed, the shift register 0 (SFT0) instruction at address 3 is executed next. Similar to the conventional shift register instruction, this instruction uses the contents of the logical operation register 8 as data,
Further, shift control is performed using the 0 stage output (No. 1 input data) of the stack register 9 as a clock and the 1 stage output (No. 0 input data) as a reset signal.

FIG. 5 is a flowchart showing the shift control operation.

As described above, since this sequence controller executes each instruction by scanning operation, shifting is performed only at the rising edge of the clock. Also, for reset, the reset signal is
Reset control is performed continuously while ON. Steps n1 to n3 are procedures for resetting the shift register depending on the state of the reset signal. Similarly, the rising edge of the clock is detected at steps n4 and n5, and at the rising edge, the contents of the shift register are shifted to the right by 1 bit by proceeding from step n5 to step n6. reset signal,
At times other than when the clock rises, the program exits without executing anything and moves on to the next command. Note that the previous reset signal and previous clock are stored in the work RAM.
4 is temporarily stored in an appropriate area.

At step n6, the contents of the shift register are shifted to the right, and then at step n7, overflow data is set in the logical operation register 8. As a result of this processing, when the shift register command is executed again for the second shift register, the overflow bit becomes input data and shift control is performed. That is, by performing the above shift control on the 0th shift register (first shift register), and then performing the same shift control on the 1st shift register (second shift register), the 0th shift register It is possible to shift to a 16-bit shift register in which the 1st shift register and the 1st shift register are connected in series. Then, when executing the shift register instruction for the second time, the stack contents (reset, clock) used for the first shift register instruction can be used as is, so the program executes the shift register instruction at address 3, as shown in Figure 3B. All you have to do is write this after address 4.

Since the above shift control is performed,
The total number of program steps required to shift a double-length shift register by 1 bit may be 5 steps in total. Furthermore, even if it becomes necessary to configure a quadruple length shift register, the number of instructions may be 7 steps. That is, one instruction (shift register instruction)
By simply adding , it is possible to form a state in which unit-length shift registers are connected in series on the hardware.

As described above, according to the present invention, overflow data when executing a shift register instruction is also set in the logical operation register, which conventionally was only a storage register for logical operation results and input data. The conditions that have already been input into the shift register for the first shift register can be used as-is for the shift register instruction for the second shift register, so unit-length shift registers can be directly connected extremely easily, and the program The number of steps can be minimized.

[Brief explanation of drawings]

FIGS. 1A and 1B show a ladder diagram and program of a conventional shift register control system. Second
The figure is a block diagram of a sequence controller control unit that implements the shift register control method according to the present invention, Figures 3A and B are ladder diagrams and programs of the same control system, and Figures 4A, B, and C are after execution of a load instruction. FIG. 5 shows the contents of the logic operation register and the stack register, and FIG. 5 shows a flowchart of the shift control operation.

Claims (1)

[Claims] 1. A logic operation register that stores input data and logic operation results, a stack register in which the contents of the logic operation register are stacked when executing a load instruction that sets input data to the logic operation register, and multiple shift registers for work. and a shift register instruction for shifting the shift register by 1 bit using the contents of the logical operation register as shift input data, wherein the shift register overflows when the shift register instruction for the first shift register is executed. It is characterized by comprising means for setting data in the logic operation register, and means for setting the contents of the logic operation register and the stack register as input conditions when executing a shift register instruction for the second shift register. , Sequence controller shift register control device.