JPH0119677B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an imaging device using a solid-state imaging device.

[Background technology]

In recent years, the development of so-called portable video, which is a miniaturized video camera and VTR, has been active, but in the future, an even more advanced form of 8mm video, which is a combination of a video camera and a VTR, is likely to be developed.

The miniaturization of such electronic devices is particularly dependent on semiconductor technology. Due to such advances in semiconductor technology, the photoelectric conversion section of the aforementioned video camera is also about to be replaced from an image pickup tube to a solid-state image pickup device.
Currently, solid-state image sensors have many features compared to image pickup tubes.

That is, because it is a solid-state device, it has features such as small size, low power consumption, mass productivity, and no burn-in.

With the establishment of technology for solid-state image sensors with these many features and the development of ultra-compact magnetic recording devices, the conventional silver halide photography technology, which uses silver halide film as a recording medium, has been replaced by magnetic photography, which does not require development processing. is being threatened by electronic photography technology.

The main use of VTRs today is to record moving images on a VTR and display them on a TV, which is called a movie video.Still images are recorded on a recording device and the recorded signal is sent to a TV. If we call a video whose main purpose is to display it or print it with a printer as still video, there is a big difference between both movie video and still video because the signal format is converted into the TV signal format. There isn't.

However, while movie video generally captures images of the subject continuously, still video captures images of the subject instantaneously, just like a regular camera, so the iris, shutter, AGC,
The responsiveness of white balance etc. will need to operate quite differently, and in addition, the driving method of the solid-state image sensor will also be slightly different, which means that the current optical system
There is a problem in that a signal processing system alone cannot be used for both.

For this reason, it is preferable to separate the movie camera section and the still camera section, but it will only be worth it in terms of cost once such cameras have become sufficiently popular. Currently, it is advantageous to use both.

When the camera section is used for both movies and still images, problems arise in the charge accumulation method of the solid-state image sensor and its readout method. Solid-state image sensors include MOS type and interline type CCD (IL-
CCD), frame transfer type CCD (FT-
CCD), but the basic structure of the device is not really relevant here, so we will explain using FT-CCD as an example.

The FT-CCD consists of an imaging section consisting of multiple photoelectric conversion cells that convert the light of the subject image into charges, a memory section that temporarily stores signal charges from the imaging section, and a TV synchronization signal that converts the signal charges from the memory section. A horizontal shift register section that reads out timings that match the
It also includes an on-chip amplifier section that amplifies the signal charge from the horizontal shift register section and outputs it as a signal voltage.

When using such an FT-CCD as a movie camera, the imaging section performs photoelectric conversion as described above for one field period, and this photoelectrically converted signal charge is transmitted as a vertical transfer pulse of several MHz during the vertical blanking period. is moved to the memory section. Then, the signal charge in the memory section is transferred to the horizontal shift register section during the horizontal blanking period for every horizontal scan in the next field period, and is transferred from the on-chip amplifier in the next stage to the CCD.
Read out as a signal. During this time, the imaging section is in a photoelectric conversion state. In other words, photoelectric conversion and vertical transfer are repeated for each field, resulting in a continuous video signal.

Next, when the FT-CCD just described is used as a still camera, image blurring is likely to occur, because a TV signal is made up of one frame of video signal, and one frame consists of two Freilds ( Since a single image is assembled using interlacing (odd and even fields), one frame signal due to photoelectric conversion at different times may cause image blurring, especially for fast-moving subjects, resulting in a decrease in image quality. cause

There are two methods to eliminate these drawbacks:

The first method is to use signals from only odd fields (or only from even fields). That is, this method uses the signal of the odd numbered field also for the next even numbered field. However, when such a method is used, the vertical resolution deteriorates, making it unsuitable for still images.

The second method is to double the number of vertical elements in the imaging section, and to provide a second horizontal shift register section between the imaging section and the memory section, so that odd and even fields can be simultaneously processed on the surface of the imaging device. The idea is to use a solid-state imaging device that can capture and sequentially read out images, and that can handle both movie video and still video. The present applicant proposed such a solid-state imaging device in Japanese Patent Application No. 146587/1983.

This imaging device is shown in FIG. 1, and its operation will be briefly explained.

In FIG. 1, 1 is an imaging section in which a plurality of photoelectric conversion cells are arranged in a matrix, 2 is a memory section that transfers and stores signal charges obtained in the imaging section, and 3 is a reading section for reading signal charges obtained in the imaging section. 4 is a second horizontal shift register for reading signal charges stored in the memory section; 5 and 6 are on-chip amplifiers for amplifying read signals from the first and second horizontal shift registers. This imaging device as a whole forms a frame transfer type CCD. And the number of cells in the vertical direction of the imaging unit 1 is
490, and the number of cells in the vertical direction of the memory section 2 is 245.

In the case of a movie video, the signal charges of two vertically adjacent pixels of the imaging section 1 are sequentially added in the first shift register 3 and transferred to the memory section 2, and then transferred from the second shift register 4 via the on-chip amplifier 6. and read it out as a signal IC. (This mode is called the first mode or field mode.) In the case of still video, the signal charges of the odd-numbered cells in the vertical direction of the imaging section 1 are read out from the first horizontal shift register 3, and the signal charges of the even-numbered cells are read out from the first horizontal shift register 3. The signal charges are read out by the second horizontal shift register 4. (This mode is called the second mode or frame mode).

With this configuration, if frame mode is used, a completely interlaced signal can be obtained without loss of vertical resolution even in the case of still video. Therefore, the device shown in FIG. 1 can be applied to both movies and stills.

In the case of still video, reading in field mode is also possible at the expense of vertical resolution.

[Problem that the invention seeks to solve]

By the way, when we compare field mode and frame mode, we find that compared to field mode, which adds the signal charges of two cells, frame mode, which reads out the signal charge of each cell as is, has almost no signal charge. It becomes 1/2. In other words, the sensitivity of the camera will be reduced by one aperture stop.

Furthermore, the on-chip amplifier section is composed of MOS elements, and this MOS has poor low-frequency noise characteristics.
Furthermore, considering that the human eye easily senses noise in the low frequency range, the S/N deterioration by one stop of aperture becomes a problem that cannot be ignored.

In addition, the number of horizontal elements in solid-state image sensors is currently 390.
Alternatively, even 570 elements may be insufficient, and the number of horizontal elements may be increased in the future.The other possibility is that the current 2/3 inch optical system will be gradually reduced to a 1/2 inch optical system and then an 8 mm optical system in the next step. It is expected that this will happen, and when that happens, camera sensitivity will become a very important issue.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention aims to provide an imaging device that compensates for fluctuations in the level of a readout signal due to differences in reading methods from a solid-state imaging device.

[Means for solving problems]

In order to achieve the above object, the present invention provides an imaging means having a solid-state imaging device in which a plurality of photoelectric conversion cells capable of forming a video signal for one frame are arranged in a matrix, and an imaging means for recording still images. Trigger means for forming a trigger signal; exposure means for causing the plurality of photoelectric conversion cells to perform photoelectric conversion only for the same period in response to the trigger means; and recording means for recording the read signal read from the image sensor. Then, in response to the trigger means, the plurality of photoelectric conversion cells are caused to perform photoelectric conversion for the same period by the exposure means, and then the signals of odd rows and even rows in the photoelectric conversion cells are added together to form one field. a first mode of forming a video signal for the same period of time, and after causing the plurality of photoelectric conversion cells to perform photoelectric conversion for the same period by the exposure means in response to the trigger means; selection means for selectively selecting a second mode in which a video signal for one interlaced frame is formed by sequentially reading out row signals in separate field periods; and control means for controlling the level of the readout signal read out from the image sensor so that a level difference does not occur in the signal input to the recording means between the two modes.

[Effect]

As described above, in the present invention, by providing the level control means, switching between the first mode in which the signal charges in the photoelectric conversion cells are added and read out, and the second mode in which the signal charges in each of the photoelectric conversion cells are read out is performed. Even in such a case, no level difference occurs in the read signal, and the dynamic range of the subsequent signal processing circuit can be suppressed and the configuration can be simplified.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

In Figure 2, 11 is the structure shown in Figure 1.
FT-CCD, the imaging section has approximately 570 elements horizontally and approximately 570 elements vertically.
Consists of 490 elements. 12 is a driver for the CCD 11; 13 is a synchronizing signal generating circuit that generates pulses for driving the CCD 11; 12 and 13 constitute a reading means. 14 is CCD
11 is an iris and shutter control circuit for controlling the amount of light incident on it; 15 is a first mode switching circuit for switching between movie mode and stay mode; 16 is a control circuit for controlling the iris aperture value and shutter operating speed from the output signal of CCD 11; The AE control unit 17 is an auto gain control unit (hereinafter referred to as AGC) that variably controls the signal level when the signal level is low even if the AE control unit 16 opens the iris. 18 is a signal processing circuit composed of a process circuit encoder circuit and a modulation circuit for converting the output signal of the AGC 17 into a recording signal; 19
20 is a recording head, 20 is a recording mechanism including a motor, 21 is a rotation control unit that controls the speed and phase of the motor of the recording mechanism 20 by control pulses from the synchronization signal generator 13, 22 is a NAND gate, 23 is an AND gate, 24 is a switch circuit, and 25 is a second circuit for selecting whether to manually or automatically select the frame mode and field in the stay mode.
A mode switching circuit 26 is a third mode switching circuit for selecting frame mode or field mode when the manual mode is selected in circuit 25, and 30 is a switch circuit including an amplifier circuit as a level control means.

When the movie mode is selected by the first mode switching circuit 15, the output of the switching circuit 15 becomes a low level (hereinafter referred to as "L"), and this signal causes the synchronization signal generator 13 to generate a control pulse for the movie mode. That is, when a trigger switch (not shown) is pressed, power is applied to each circuit to start recording. Movie mode is continuous recording, so iris and
The AE control unit 16 that controls the AGC 17 performs feedback control with an appropriate time constant. Also,
The reading method of the CCD 11 is set to the field mode described above, and data is read out from the second horizontal shift register 4 in FIG. 1 via the on-chip lamp 6.

Next, when the first mode switching circuit 15 selects the stay mode, the output of the mode switching circuit 15 becomes a high level (hereinafter referred to as "H"), and outputs a stay mode control pulse to the synchronization signal generator 13. Instruct them to do so. The AE control section 16 determines the shutter speed and iris aperture value and transmits them to the iris shutter control circuit 14. The stay mode includes both the field mode recording and frame mode recording described above. When the field mode recording and frame mode recording are set to the automatic selection mode, the switch circuit 24 is connected to contact a. In the automatic selection mode, when the AE control unit 16 detects that the subject is under low illumination, the output line 27 becomes "H". Then Nand Gate 22
The output of AND gate 23 is “L”, and the output of AND gate 23 is “L”
Therefore, the synchronizing signal generator 13 is set to stay mode and field mode. Furthermore, when the subject is not under low illumination, the output line 27 becomes "L", the output of the NAND gate 22 becomes "H", the output of the AND gate 23 becomes "H", and the synchronization signal generator 13 changes from the still mode to the frame mode. Set.

When the second mode switching circuit is set to manual selection mode, the switch circuit 24 is connected to the b side,
According to the setting of the third mode switching circuit 26. The third mode switching circuit 26 can arbitrarily select field mode or frame mode during the stay mode.

When the field mode is selected in the stay mode, an image with a good S/N ratio can be obtained even if the subject is under low illumination. Furthermore, even when the subject is under high illumination, images with soft focus, or a so-called blurring effect, can be obtained.

Furthermore, when the frame mode is selected, a sharp image with high resolution can be obtained.

By the way, as mentioned above, in the field mode, the output of the second horizontal shift register shown in FIG. 1 is used, and in the frame mode, the output of the first,
Since the second horizontal shift register is used, switching of the shift register in each mode is performed by the switch circuit 30. The operation of the switch circuit 30 will be explained in detail below.

FIG. 3 shows a first embodiment of the switch circuit 30. In the figure, 40 is an adder, 41 is an amplifier, 4
2 is a switch. In the frame mode, the read signals 1A and 1B are combined into one system through an adder 40, and then compensated in an amplifier 41 so that the level becomes equal to the level of the read signal 1C in the field mode. In the field mode, the signal is sent directly to the switch circuit 42 without going through the amplifier 41. The switch circuit 42 is connected to the a side in the frame mode, and connected to the b side in the field mode. This configuration compensates for the difference in read signal level between frame and field modes. Furthermore, since the level is adjusted before being used in the AE control section 16, it is possible to prevent the subsequent circuit from becoming complicated.

4 and 5 show other circuit examples of the switch circuit 30 as 30' and 30''.

The example shown in FIG. 4 shows the gain adjustment of the CCD on-chip amplifiers 5 and 6 in the frame mode, the imaging section 1, the memory section 2, the shift register section 3,
4. In order to keep the total gain of the on-chip amplifiers 5 and 6 constant, the signals 1A and 1B are amplified at different ratios through separate amplifiers 43 and 44, respectively, and then added by an adder 45 to form one series. This is an example. The operation of switch 46 is the same as switch 42 in FIG. As described above, according to this embodiment, since the levels are adjusted in the odd and even fields in the frame mode, it is possible to prevent flickering when played back on a TV receiver.

The example shown in FIG. 5 is an example in which, in the field mode, the level of the read signal 1C is lowered by the attenuator 48 to compensate for the level matching with the read signal in the frame mode. Note that 47 is an adder and 49 is a switch. Although an example in which level control is performed using an amplifier or an attenuator as the level control means has been shown above, the present invention also includes level compensation using other configurations. Also, the above is FT
- Although the explanation has been made using a CCD, the present invention is not limited to the type of image sensor.

The IL-CCD and MOS types will be briefly explained below.

Figure 6 shows interline transfer method (IL-CCD)
FIG. As shown in the figure, the IL-CCD has a light-receiving element 51 which is a photoelectric conversion section, and the information charge accumulated in the light-receiving element 51 is transferred to a vertical register 5.
Transfer gate TG that controls transfer to 3
and the vertical register 53 that temporarily stores information charges from the light receiving element 51 by means of the TG.
It is composed of a horizontal register 54, an on-chip amplifier 55, etc. for reading out information charges from the vertical register 53 as a CCD output signal every horizontal scanning period (1H).

Considering the stay mode, after the shooting is finished, that is, after the shutter is closed, the information charges of the light receiving elements (indicated by n1, n2, ...) corresponding to odd fields are transferred to the vertical register 53, and then transferred to the horizontal register 53. 54 every 1H, and outputted from the on-chip amplifier 55 as an odd field CCD output signal. When all the signals of the odd fields are read out in this way, the CCD output signals of the even fields (indicated by m1, m2, . . . ) are read out in the next even field period. This kind of operation is called a frame mode, and the photoelectrically converted information charge in the frame mode is C ₁
shall be.

Next, in the field mode in the stay mode, the information charges of a pair of adjacent odd and even fields are added in the vertical register 53 and output to the horizontal register 54, and then output from the on-chip amplifier 55. If the amount of information charge at this time is C ₂ , then C ₁ =1/2C ₂ .

As mentioned above, since the amount of accumulated charge is different between the frame mode of the stay mode and the field mode, a switch circuit 56 and an amplifier 57 are provided to adjust the level of the CCD output signal.
The switch circuit 56 is connected to the b side in the frame mode, and the read signal is made to the same level as in the field mode by the amplifier 57 and sent to the AGC or the like.

FIG. 7 is a schematic diagram of a MOS type solid-state image sensor.

As shown in the figure, the MOS type is composed of a light receiving element 61, a vertical scanning circuit 63, a horizontal scanning circuit 62, and the like. The operation of the MOS type is well known, so I will not explain it here, but since it is basically an X-Y scanning method, it uses the frame mode that divides into two fields as mentioned earlier, and adds the signal charges of two adjacent elements. You can easily configure the field mode you want.

Since the signal level read out at that time is naturally different between both modes, it is necessary to adjust the signal level in each mode.

Therefore, it becomes possible to adjust the read signal level in both modes by using the switch circuit 65 whether or not the signal is passed through the amplifier 66.

[Effects of the Invention] As described above, the present invention provides a first mode in which signal charges in adjacent photoelectric conversion cells of a solid-state image sensor are added and read by providing a level control means;
Even if a second mode is provided in which each signal charge of each cell is read out, there is no difference in level between the read signals of both modes, and signals can be taken out at the same level for each mode. Therefore, the dynamic range of subsequent circuits such as AE control of the imaging device can be suppressed, and the configuration is greatly simplified.

Furthermore, it is possible to prevent the image from becoming smaller due to differences in readout signal levels.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a frame transfer type CCD, FIG. 2 is a control circuit diagram of this embodiment, and FIGS. 3, 4, and 5 are circuits showing the internal configuration of the switch circuit 30 in FIG. 2. Figure 6 is an interline type
A schematic diagram of a CCD, and FIG. 7 is a schematic diagram of a MOS type solid-state image sensor. In the figure, 1 is an imaging unit, 2 is a memory unit, and 3
is a first horizontal shift register, 4 is a second horizontal shift register, 11 is a CCD, 13 is a synchronization signal generator,
15 is a first mode switching circuit, 16 is an AE control section,
17 is an AGC, and 30 is a switch circuit.

Claims (1)

[Scope of Claims] 1. Imaging means having a solid-state imaging device in which a plurality of photoelectric conversion cells capable of forming a video signal for one frame are arranged in a matrix, and a trigger forming a trigger signal for recording a still image. means; exposure means for causing the plurality of photoelectric conversion cells to perform photoelectric conversion only for the same period in response to the trigger means; recording means for recording a readout signal read out from the image sensor; In response, the plurality of photoelectric conversion cells are caused to perform photoelectric conversion for the same period by the exposure means, and then the signals of odd rows and even rows in the photoelectric conversion cells are added together to form a video signal for one field. A first mode in which the plurality of photoelectric conversion cells are caused to perform photoelectric conversion for the same period by the exposure means in response to the trigger means, and then signals of odd and even rows of the photoelectric conversion cells are separated into separate modes. selection means for selectively selecting a second mode in which a video signal for one interlaced frame is formed by sequentially reading data during a field period; An imaging apparatus comprising: control means for controlling the level of a readout signal read out from the imaging element so that a level difference does not occur in the signal input to the recording means.