JPH0119782B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization control system between devices connected via a digital transmission path.

When transmitting and receiving control information between devices connected via a digital transmission path, it is necessary to perform synchronization control prior to transmitting and receiving the information in order to identify the beginning of the control command. To this end, various methods have been implemented in the past, but in this type of conventional method, a master-slave relationship is established between devices connected by a digital transmission path, and control is initiated from one device. There is. Furthermore, when transmitting and receiving control information between devices having equivalent functions, a method is adopted in which master and slave are determined based on some conditions and synchronous control is performed. However, these methods have the drawback that control cannot be performed between devices placed under exactly the same conditions.

In order to eliminate these drawbacks, the present invention performs synchronous control by having both devices perform the same operation, and will be described in detail below with reference to the drawings.

FIG. 1 is a flowchart showing the synchronization procedure of the synchronization control method according to the present invention.

FIG. 2 shows a time chart and a pattern used in the synchronous control method according to the present invention, where A is an example of a time sequence of a synchronization procedure when starting a new synchronous control, and B is an example of a time sequence of a synchronization procedure after the synchronization procedure is finished. This is an example of a time chart of the synchronization procedure when synchronization is lost for some reason, a and b each indicate devices connected by a digital transmission line, C is an example of a pattern used for this control, and is an example of a synchronization procedure when synchronization is lost for some reason. pattern,
is a synchronization pattern, is a synchronization establishment pattern, and is a control information exchange pattern.

Two devices a and b connected by a digital transmission path independently execute the flow shown in FIG. When attempting to perform synchronous control of both devices a and b, since they are connected by a digital transmission path, they are synchronized bit by bit, and it is difficult to detect whether all bits are 0 or 1. is easy. In the synchronization establishment pattern shown in Figure 2C, all bits are 1.
Therefore, even if synchronization between the two devices is not established, it is possible to receive the synchronization establishment pattern sent from the other device and know as many times as possible that the other device is ready for reception. Therefore, it is possible for both devices to independently execute the procedure shown in FIG. 1 and perform the synchronization procedure. Further, even if a synchronization establishment pattern is received, the bit at the position indicated by F in FIG.

On the other hand, when synchronization is established, it is possible to detect a specific pattern. Therefore, if synchronization is lost for some reason after the synchronization procedure is completed and synchronization is established between both devices, the device that has lost synchronization will detect the out-of-synchronization pattern and request transmission to the other device. is possible, and the synchronization procedure shown in FIG. 1 can be restarted.

Next, referring to FIG. 2A, a case will be described in which two devices connected by a digital transmission path newly execute a synchronization procedure.

The fact that the digital transmission path has been set up in the two devices a and b is transmitted independently at times t _a and t _b . Two devices a and b are at time t _a and t _b respectively
From then on, following the flow shown in FIG. 1, a synchronization pattern is sent out after sending out an out-of-synchronization pattern for a certain period of time. Even if the notification of the completion of the transmission line setup performed at times t _a and t _b is sent to both devices a and b completely independently, both devices are connected to the other device when the subsequent device starts sending out the synchronization pattern. A state is reached in which synchronization patterns from the devices are exchanged with each other.

When both devices receive the synchronization pattern from the other device, they detect the bit set to 1 in the synchronization pattern and establish synchronization. When the synchronization establishment is completed, they lock the synchronization circuit and register their own device synchronization establishment display register. After setting, a synchronization establishment pattern is sent to the partner device for a certain period of time. When both devices receive the synchronization establishment pattern from the partner device, they set their own device's partner device synchronization establishment display register. In the example shown in the figure, synchronization is established for device a at time t _c1 and device b at time t _c2 . Each device continues to send synchronization patterns until both its own device synchronization establishment display register and the partner device synchronization establishment display register are set, and when both registers are set, control information is sent.
Disclose the transmission/reception (pattern) of B ₀ to _{B 7} . In the illustrated example, this time is indicated by t _d . In this control, it goes without saying that each device maintains its previous state while receiving the synchronization establishment pattern to prevent synchronization from being erroneously established due to the synchronization establishment pattern.

Next, after completing the synchronization procedure according to Figure 2B,
The synchronization procedure when synchronization is lost for some reason during the transmission/reception state (pattern) of control information B ₀ to _{B 7} will be explained. This example shows a case where device a becomes out of synchronization at time t _a '.

At the time t _a ' when the device a becomes out of synchronization, it resets the synchronization establishment display register of the other device and the synchronization establishment display register of its own device, sends out the out-of-synchronization pattern, and restarts the sequence shown in FIG. 1. The partner device b, which is in the synchronization established state, can detect the out-of-synchronization pattern, and when it detects this pattern, it resets the partner device's synchronization establishment display register, sends the synchronization establishment pattern, and maintains the synchronization established state of its own device. Then resume the sequence shown in Figure 1. the time at this time
Denote by t _c2 ′.

If both devices become out of synchronization, the sent out out of synchronization patterns cannot be detected by each other, but
In this case, both devices restart the sequence shown in FIG. 1 from sending out the out-of-synchronization pattern, and the process is similar to the case shown in FIG. 2A. In either case, both devices will be in one of the states in the sequence shown in Figure 1,
It is possible to run sequences independently.
The aforementioned out-of-synchronization can be easily detected by constantly monitoring that the position of the synchronization bit F, which is sent at regular intervals, is 1, and when this bit becomes 0, it is considered to be out of synchronization. can be executed. Further, on the device side that is not in a synchronization established state, it is impossible to detect the out-of-synchronization pattern and it is ignored, but in this case, the sequence is being executed and ignoring it will not cause any problem.

In the above explanation, the synchronization establishment pattern is assumed to be 1, but if all bit errors are likely to occur, it can be stabilized by setting it to negative logic. Further, the out-of-synchronization pattern may be any pattern in which the patterns B ₀ to B ₇ are determined, and of course may be a pattern other than the pattern shown in FIG. 2C.

Further, in the above description, a case has been described in which the control information has an 8-bit configuration, but it goes without saying that the control information may have any configuration other than 8-bit as long as the synchronization bits at the position of F are at regular intervals. Furthermore, the information to be sent and received may be any information other than control information, as long as the same pattern as the out-of-synchronization pattern does not occur. In addition, when performing error control using one unit of information {B ₀ to B ₇ in Figure 2 C} in the transmission and reception of information, the pattern when there is no information is made the same as the synchronization pattern by performing an even parity check. In addition to stabilizing the system, it is also possible to eliminate unusable codes by making the out-of-synchronization pattern a pattern that causes an error in parity check.

FIG. 3 is a block diagram showing the configuration of an embodiment of a synchronous control circuit according to the present invention, in which 1a and 1b are synchronous control circuits according to the present invention connected by a digital transmission line, and 2a and 2b are transmission line interfaces. Device,
3 is transmitted digital information, 4 is received digital information,
5 is a clock signal, 6 is a signal indicating completion of transmission line setting, 7 is a transmission control information input terminal, 8 is a reception control information output terminal, 9 and 9' are digital transmission lines, 10
11 is a transmission register, 12 is a transmission synchronization control circuit, 13 is a reception register, 14 is a reception digital information switching circuit, and 15 is a reception synchronization control circuit. Here, synchronous control circuit 1
A and 1b have exactly the same configuration, and transmission line interface devices 2a and 2b also have exactly the same configuration.

Next, its operation will be explained.

The transmission line interface devices 2a and 2b transfer received digital information 4 and transmit digital information 3 to their respective synchronization control circuits 1a and 1b.
will be received. The transmission and reception digital information 3 and 4 are transferred to NRZ (Non-Return-to-
Zero) code. The clock signal 5 is an RZ code clock signal synchronized with the transmitted and received digital information, and controls the timing of delivery and reception of the transmitted and received digital information of the synchronization control circuits 1a and 1b. A signal 6 indicating completion of setting of the transmission line indicates to the synchronous control circuits 1a and 1b that the setting of the digital transmission lines 9, 9' between the transmission line interface devices 2a and 2b has been completed and it is now possible to send and receive digital information. and synchronous control circuits 1a and 1
b is activated by this signal and starts the synchronous control shown in FIG.

Transmission control information B ₀ to transmission control information input terminal 7
.about.B ₇ are added, and the reception control information output terminal 8 outputs reception control information B ₀ to _{B 7} . In the transmission _/ reception state of control information shown in _FIG . In states other than the transmission/reception state, the control pattern from the transmission synchronization control circuit 12 is sent to the transmission register 11. Also, the second
The synchronization bit F in Figure C is the constant transmission synchronization control circuit 12.
The side information is sent to the transmission register 11. The communication enable display signal 10 from the reception synchronization control circuit 15 is used to identify the transmission/reception state of this control information and other states.
1. Transmission register 11 is 9 bits
The transmission digital information switching circuit 10 is a parallel-to-serial conversion shift register with a latch signal 102 supplied from the transmission synchronization control circuit 12.
It takes in the information from the transmission line interface device 2a or 2b and converts it into a digital signal synchronized with the transmission bit rate of the digital transmission line 9 or 9' using the clock signal 5 supplied from the transmission line interface device 2a or 2b. It is delivered to device 2a or 2b.

The transmission synchronization control circuit 12 receives a clock signal 5 supplied from the transmission line interface device 2a or 2b.
is frequency-divided by 1/9 and supplied to the transmission register 11 as a latch signal 102. In addition, the transmission synchronization control circuit 1
2 is activated by an out-of-synchronization pattern transmission instruction signal 103 and a synchronization establishment pattern transmission instruction signal 104 from the reception synchronization control circuit 15.

When activated by the out-of-synchronization pattern sending instruction signal 103, the out-of-synchronization pattern is supplied to the transmission digital information switching circuit 10 for a certain period of time, and then the synchronization pattern is supplied to the switching circuit 10.

When activated by the synchronization establishment pattern sending instruction signal 104, the synchronization establishment pattern is supplied to the transmission digital information switching circuit 10 for a certain period of time, and then the synchronization pattern is supplied to the switching circuit 10 again.

The reception register 13 is a 9-bit serial/parallel conversion register, and converts the reception digital signal synchronized with the transmission bit rate of the digital transmission line 9 or 9' by the clock signal 5 supplied from the transmission line interface device 2a or 2b to the reception digital information. 4, the received information is converted into parallel information by the latch signal 105 supplied from the reception synchronization control circuit 15, and the received digital information switching circuit 1 converts the received information into parallel information.
Supply to 4.

The reception digital information switching circuit 14 is shown in FIGS. 2A and 2B.
During the control information transmission/reception state shown in FIG. 1, the reception information B ₀ to _{B 7} supplied from the reception register 13 is outputted to the reception control information output terminal 8, and is also supplied to the reception synchronization control circuit 15 together with the synchronization bit F.
Furthermore, output to the reception control information output terminal 8 is stopped during periods other than the control information transmission/reception state. The communication enable display signal 10 from the reception synchronization control circuit 15 is used to identify the transmission/reception state of this control information and other states.
1.

The reception synchronization control circuit 15 monitors the synchronization control procedure shown in FIG. 1 or FIG. 2 and controls the establishment of synchronization. First, as soon as the signal 6 indicating the completion of setting of the digital transmission paths 9, 9' is detected, an out-of-synchronization pattern sending instruction signal 103 is generated, and the transmission synchronization control circuit 1
2 to send out the out-of-synchronization pattern. Subsequently, the reception synchronization control circuit 15 receives the synchronization pattern sent from the partner device, and when the synchronization pull-in is completed, it locks the synchronization circuit, sets its own device synchronization establishment display register, and sends the synchronization establishment pattern sending instruction signal 104. and instructs the transmission synchronization control circuit 12 to send out a synchronization establishment pattern.

FIG. 4 shows a detailed diagram of a portion 15' related to the synchronization pull-in operation of the reception synchronization control circuit 15 in FIG.
1 and 158 are gate circuits, 152 is a differential circuit,
153 is a 1/9 frequency dividing circuit, 154 is a synchronization monitoring circuit,
155 is a partner device synchronization establishment display register, 156
157 is a synchronization establishment pattern detection circuit, and 159 is a transmission synchronization control activation circuit.

The self-device synchronization establishment display register 150 is set while the synchronization of the received digital information 4 is established. The gate circuit 151 blocks the received digital information 4 when the self-device synchronization establishment display register 150 is set, and allows it to pass when it is reset. The differentiating circuit 152 extracts the change point from 0 to 1 of the digital information that has passed through the gate circuit 151, and
A preset signal 106 for the frequency dividing circuit 153 is generated.
When the presettable 1/9 frequency divider circuit 153 completes synchronization pull-in, the self-device synchronization establishment register 150 is set, and the gate circuit 151 is in the blocking state, the preset signal 106 is not input, so that the interface device 1a or 1b is not input. A latch signal 105 is supplied to the receiving register 13 by dividing the frequency of the clock signal supplied from the register 105 to 1/9. When the self-device synchronization establishment register 150 is in the reset state, the preset signal 106 is supplied to this 1/9 frequency divider circuit to preset it. When the latch signal 105 is supplied at the ninth clock after the preset of the 1/9 frequency divider circuit, the contents of the reception register 13 are latched in the arrangement shown in the figure and taken in as data. In this case, the synchronization bit will not appear at the correct position unless synchronization pull-in is completed.

The synchronization monitoring circuit 154 constantly monitors the synchronization bit F of the received digital information, uses the latch signal 107 to detect that the synchronization bit becomes 1 continuously for a certain period of time, and sets the self-device synchronization establishment display register 150. If synchronization bit 0 is detected, the own device synchronization establishment display register 150 and the partner device synchronization establishment display register 155 are reset. The partner device synchronization establishment display register 155 is set when a synchronization pattern from the partner device is detected, and the synchronization monitoring circuit 154 is set after the own device enters the synchronization established state.
It is reset when the output changes from 1 to 0 and out-of-synchronization is detected, or when an out-of-synchronization pattern from the partner device is detected. The synchronization establishment pattern detection circuit 156 detects the synchronization establishment pattern from the partner device and sets the partner device synchronization establishment display register 155. This synchronization establishment pattern can be detected by confirming that a series of 1's continues for a certain period of time in the received digital signal.

The out-of-synchronization pattern detection circuit 157 receives the received information B ₀
It is detected by confirming that the pattern ~ _B7 is an out-of-synchronization pattern. Gate circuit 158
When the own device synchronization confirmation display register 150 is set (when the own device has synchronization established),
The detection information of the out-of-synchronization pattern detected by the out-of-synchronization pattern detection circuit 157 is passed, and the synchronization establishment display register 155 of the partner device is reset. Also, when the own device synchronization establishment display register 150 is in the reset state (when the own device synchronization has not been established)
prevents detection information of the out-of-synchronization pattern and erroneously detecting the out-of-synchronization pattern of the partner device. The transmission synchronization control starting circuit 159 is for starting the transmission synchronization control circuit 12 shown in FIG.
When the completion of the setting is known by the signal 6 indicating the completion of setting of the digital transmission path, and when the self-device synchronization establishment display register 150 changes from the set state to the reset state, an out-of-synchronization pattern sending instruction signal 103 is generated, and the self-device synchronization is performed. When the establishment display register 150 changes from the reset state to the set state, when the own device synchronization establishment display register 150 is in the set state, and when the partner device synchronization establishment display register 155 changes from the set state to the reset state, a synchronization establishment pattern is sent. An instruction signal 104 is generated to instruct the start of control of the transmission synchronization control circuit 12 explained in FIG.

Although omitted in the explanation, it is necessary to stop the operation of the synchronization monitoring circuit 154 while the synchronization establishment pattern detection circuit 156 is receiving the synchronization establishment pattern.
This can be easily achieved by providing a gate circuit that blocks the latch signal 107 input to the synchronization monitoring circuit 154 when a synchronization establishment pattern is being received and the synchronization establishment display register of the device itself has not been set. .

As explained above, the setting of the own device synchronization establishment display register and the other device synchronization establishment display register of the reception synchronization control circuit 15 is performed completely independently. During the period when both display registers are set, the reception synchronization control circuit 15 outputs the communicable display signal 1.
01 indicates that communication is possible. Therefore, the transmitting and receiving digital information switching circuits 10 and 14
is in a state where the information from the transmission control information input terminal 7 is sent out, and the reception information is output from the reception control information output terminal 8.

In addition, in the above explanation, it was explained that the synchronization pattern and synchronization establishment pattern are not sent from each device until it starts synchronization control, but this situation may occur depending on the status of each device. If there is a possibility that this may occur, send a reset signal (for example, all 0s) with the synchronization bits set to 0 for a certain period of time and reset the other device only when synchronization control is started with signal 6 indicating completion of transmission path setting. This makes it possible to prevent malfunctions due to the above-mentioned conditions.

As explained above, according to the present invention, two devices connected by a digital transmission line can perform synchronization control independently, and synchronization control between devices placed in a completely equal state can be performed. It is possible, for example, when both terminal devices receive an incoming call, are set to the same operating conditions, and cannot establish a master-slave relationship by any means, such as when setting up a line by reservation. This has the advantage of being able to perform synchronous control for transmitting and receiving control information between both terminal devices.

[Brief explanation of drawings]

Fig. 1 is a flowchart showing the synchronization procedure of the synchronous control method according to the present invention, Fig. 2 is a diagram showing the time chart of the synchronous control method according to the invention and the pattern used, and Fig. 3 is a flowchart showing the synchronization procedure according to the synchronous control method according to the present invention. FIG. 4 is a block diagram showing the configuration of one embodiment of the control circuit. FIG. 4 is a detailed diagram of a portion related to the synchronization pull-in operation of the reception synchronization control circuit of FIG. 3. 1a, 1b... synchronous control circuit, 2a, 2b...
Transmission line interface device, 3... Transmission digital information, 4... Reception digital information, 5... Clock signal, 6... Signal indicating completion of transmission line setting, 7...
...Transmission control information input terminal, 8...Reception control information output terminal, 9, 9'...Digital transmission line, 10...
Transmission digital information switching circuit, 11... Transmission register, 12... Transmission synchronization control circuit, 13... Receiving register, 14... Receiving digital information switching circuit, 1
5... Reception synchronization control circuit, 101... Communication possible display signal, 102, 105, 107... Latch signal,
103...Out-of-synchronization pattern sending instruction signal, 104
... Synchronization establishment pattern sending instruction signal, 106 ... Preset signal, 150 ... Own device synchronization establishment display register, 151, 158 ... Gate circuit, 152
... Differentiation circuit, 153 ... 1/9 frequency division circuit, 154
... Synchronization monitoring circuit, 155 ... Other device synchronization establishment display register, 156 ... Synchronization establishment pattern detection circuit, 157 ... Out-of-synchronization pattern detection circuit, 159
...Transmission synchronous control starting circuit.

Claims (1)

[Claims] 1. In a synchronization control method for information transmission between two devices connected via a digital transmission path, a first device that loses synchronization during information transmission will control a second device that has established normal synchronization. The second device, which has received the out-of-synchronization pattern, sends out a synchronization pattern to the first device following the synchronization establishment pattern while maintaining the synchronization establishment of its own device. The first device receives the synchronization pattern and establishes synchronization, and then sends out the synchronization establishment pattern, and the two devices transmit the synchronization pattern after establishing synchronization of their own device, and transmit the synchronization establishment pattern from the other device. A synchronous control method characterized by restarting information transmission upon reception of a synchronous control method.