JPH0122628B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal matrix display device, and particularly to an improvement of a circuit that generates a driving voltage waveform thereof.

[Conventional technology]

Conventionally, it has been known to drive a liquid crystal matrix panel with alternating current using a line sequential scanning method and a voltage averaging method. proposed a liquid crystal matrix panel display device as shown in (Japanese Patent Application No. 112994/1982).

In FIG. 1, reference numeral 10 denotes a liquid crystal matrix panel, which has a plurality of scanning electrodes X1 to X4 and signal electrodes Y1 to Y4 arranged to intersect each other so as to define a large number of matrix intersection points to become pixels. When the voltage applied to the liquid crystal interposed between the opposing electrodes at each matrix intersection exceeds a certain value (referred to as the threshold voltage V _th ), the orientation state of the liquid crystal molecules changes, and the light transmittance increases. changes. When performing pixel display on this type of panel, the scanning electrodes X1 to
It is designed to supply image signals to the Y4 side,
As a driving method in this case, an alternating current driving method called a voltage averaging method is preferably used in order to prevent unevenness in the excited state of the liquid crystal.

In the drive device shown in FIG. 1 which employs such a line sequential scanning method and voltage averaging method, 12 is a scanning circuit that generates a line sequential scanning signal, and 16 and 18 are selection voltages V _S1 as shown in FIG. , non-selection voltage V _NS1
20 is a first voltage generating circuit that combines the voltages V _S1 and V _NS1 in accordance with the line sequential scanning signal to synthesize a driving voltage waveform to be supplied to each scanning electrode.
electronic switch circuit, 22 is image signal input terminal 2
2a is a serial-to-parallel conversion circuit, 24 is a line memory that stores image signals for one row, 28, 30
is a voltage generating circuit 32 that generates a selection voltage V _S2 and a non-selection voltage V _NS2 as shown in FIG.
is a second electronic switch circuit which combines the voltages V _S2 and V _NS2 according to each bit state of the image signal from the line memory 24 to synthesize a drive voltage waveform to be supplied to each signal electrode. Electronic switch circuit 20
has a pair of electronic switches 20a and 20b connected to each scanning electrode, and a positive-phase scanning signal is applied to the control terminal of each one of the electronic switches 20a, and the control terminal of each other electronic switch 20b is applied to the control terminal of the other electronic switch 20b. A scanning signal having an opposite phase is applied to the inverter 14 through the inverter 14. The electronic switch pair alternately opens and closes so that when one switch is on, the other switch is off, and the common output side has a selection voltage V _S1 and a non-selection voltage V _NS1 as shown in Figure 2. A scanning electrode driving voltage waveform _VX consisting of the combination is generated. Voltage switch circuit 3
2 is also configured in the same manner as the circuit 20 described above,
Each has a pair of electronic switches 32a and 32b connected to each signal electrode, and a positive-phase image signal is applied to the control terminal of each electronic switch 32a, and a positive-phase image signal is applied to the control terminal of each other electronic switch 20b. An image signal of opposite phase is applied via the inverter 26. Electronic switch 32a, 3
The pair 2b is the aforementioned electronic switch 20a, 20b.
It opens and closes in the same manner as shown in FIG. 2, and as shown in FIG. 2, a voltage waveform V _Y for driving the signal electrode is generated, which is a combination of a selection voltage V _S2 and a non-selection voltage V _NS2 . Driving voltage to the liquid crystal matrix panel 10
When V _X and V _Y are applied, the voltage actually applied to the liquid crystal becomes an _AC waveform of _V It becomes selected state.

In order to obtain the drive voltage waveform shown in Fig. 2, a signal with two potential levels, V 0 and 0, is used as the selection voltage V _S1 , and a signal with two potential levels of V ₀ and 0 is used as the non-selection voltage V _NS1 .
A signal with two levels aV ₀ and (1-1/a)V ₀ is used as the selection voltage V _S2 , and a signal with two levels O and V ₀ is used as the non-selection voltage V _NS2 .
Signals with two levels, aV ₀ and (1-2/a)V ₀ , are required, respectively, and the voltage generation circuits 16, 1
8, 28, and 30 are composed of pulse oscillators that generate respective signals. Note that a is a constant determined according to the driving conditions of the liquid crystal. For example, as shown in Japanese Patent Laid-Open No. 50-68419, if the duty ratio is 1/N, then a is set in the vicinity of a=√+1. Ru.

In the circuit shown in Fig. ₁ , depending on the case, driving _{voltage waveforms V} can be added. In this case, V _S1 is 2 of +(1-1/a)V ₀ and -(1-1/a)V ₀ .
level signal, V _NS1 as O level signal, V _S2
and V _NS2 , AC signals of ±1/aV ₀ with opposite phases are generated, respectively.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional devices have two drawbacks: (1) The internal configuration of the voltage generating circuits 16, 18, 28, and 30 is complicated, so that changes in device specifications cannot be accommodated, and (2) those voltage generating circuits are (3) It is difficult to standardize the circuit.

Furthermore, as such a display device, Japanese Patent Application Laid-open No. 52
It is known to use a resistive voltage divider circuit as described in Japanese Patent No. -55832. In this known technology, the number of resistors is 4, and each resistance value is 1:1:1:1 from one potential terminal side to the other potential terminal side, or the division ratio can be arbitrarily set. Therefore, the resistors are arranged so as to satisfy the ratio relationship of (√-1):1:1:(√-1) (n: duty ratio).

However, in this resistive voltage divider circuit, (1) only five potential levels can be generated; therefore, six potential levels suitable for the optimal voltage averaging method as shown in FIG. 2 cannot be generated;

(2) When considering the partial pressure ratio, (√−1) and (√
-1) It is necessary to adjust the values of two resistances in total.

There are other problems.

SUMMARY OF THE INVENTION An object of the present invention is to solve this kind of problem and to provide a liquid crystal matrix display device with a simple configuration in which liquid crystal driving conditions can be easily set and circuits can be standardized.

[Means for solving problems]

To summarize the features of the present invention,
The circuit that generates the drive voltage waveform to be supplied to the scanning electrodes and the drive voltage waveform to be supplied to the signal electrodes is configured as a single circuit by combining a resistive voltage divider circuit and a group of electronic switch circuits. .

A resistive voltage divider circuit has a plurality of resistors connected in series between a pair of potential terminals, and extracts all the potential levels necessary to configure the drive voltage waveform from these potential terminals or the connection point between the resistors. configured.

Further describing a preferred embodiment of the present invention, one of the electronic switch circuits includes a plurality of electronic switch circuits for opening and closing pairs of potential levels in opposite phases in response to synchronizing signals. It has a pair of switches and is configured to generate selection and non-selection voltages by these pairs of electronic switches.

[Effect]

These features not only simplify the circuit configuration and enable circuit standardization, but also make it extremely easy to deal with changes in device specifications, and in particular, make it easy to set or change optimal drive conditions. There are advantages.

〔Example〕

The present invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

Referring to FIG. 4, a circuit configuration of a liquid crystal matrix display device according to an embodiment of the present invention is shown. In the circuit shown in FIG. 1, the same parts as those in FIG. For the sake of simplicity, in this example, a case where a 3×3 liquid crystal matrix panel 10 is driven will be taken up, and the configuration and operation of the voltage generating circuit 40, which is a feature of the present invention, will be described in detail. In Figure 4, e ₁₁ , e ₁₂ ......
e ₃₃ indicates a liquid crystal body or pixel located at a matrix intersection point, V _X1 to V _X3 are voltages for driving scanning electrodes X1 to X3, and V _Y1 to V _Y3 are voltages for driving signal electrodes Y1 to X3. show. Furthermore, S1 to S3 represent sequential scanning signals, and L1 to L3 represent each bit of an image signal for one row.

The voltage generating circuit 40 that generates the selection voltage V _S1 and non-selection voltage V _NS1 on the scanning side and the selection voltage V _S2 and non-selection voltage V _NS2 on the signal side has a configuration as shown in FIG. It includes a voltage dividing circuit 43 and an electronic switch circuit 50. Resistor voltage divider circuit 4
3 are resistors 43A, 43B, 43C, 43D connected in series between a pair of potential points 44A and 44F,
43E, and a power terminal 4 is provided at potential point 44A.
A power supply voltage V _DD is applied from 1 through the variable resistor 42, and the potential point 44F is connected to the O potential or the ground potential. Resistance 43A, 43B, 43C, 43
The values of D and 43E are chosen as R, R, and (a-4)R, R, R, respectively, to obtain the potential levels constituting the selection and non-selection voltages previously explained with reference to FIG.
The resistance ratio is 1:1:(a-4):1:1. By giving weight to each of the resistors 43A to 43E in this way, the connecting points 44B and 4 between the resistors are
4C, 44D, and 44E have (1-1/a) V ₀ , (1-2/a ₎ V ₀ , and 2/
A potential of aV ₀ and 1/aV ₀ can be obtained.

On the other hand, the electronic switch circuit 50 includes electronic switches 51a and 51b, 52a and 52b, 53a and 53b, 54a and 54b constituting four electronic switch pairs 51, 52, 53, and 54, respectively.
It is equipped with The output ends of the electronic switches 51a and 51b are connected to the output terminal 55, and the output ends of the electronic switches 52a and 51b are connected to the output terminal 55.
The output ends of the electronic switches 52b are connected to the output terminal 56, the output ends of the electronic switches 53a and 53b are connected to the output terminal 57, and the output ends of the electronic switches 54a and 54b are connected to the output terminal 58.
are commonly connected to each other. 48 is a terminal for applying the clock signal CP for the same period, and this terminal 48 is connected to the electronic switches 51a, 51
It is connected to each control input terminal of electronic switches 51b, 52a, 53a, and 54a via an inverter 49. As a result, the electronic switches of each electronic switch pair open and close in opposite phases, such that when one closes, the other opens. One electronic switch 51a of the electronic switch pair 51 is supplied with the voltage V ₀ at the potential point 44A, and the other electronic switch 51b is supplied with the voltage O at the potential point 44F, and the output terminal 55 is supplied with the voltage V 0 at the potential point 44F. clock signal as shown in
A selection voltage V _S1 on the scanning electrode side is generated according to CP. One electronic switch 52a constituting the electronic switch pair 52 has a voltage of 1-1/1 at the connection point 44B.
a) V ₀ is supplied, the other electronic switch 52b is supplied with the voltage 1/aV ₀ of the connection point 44E, and the output terminal 56 is supplied with a clock signal as shown in FIG.
A non-selection voltage V _NS1 on the scan electrode side is generated according to CP. One electronic switch 53a of the electronic switch pair 53 is supplied with a voltage V ₀ from a potential point 44A, and the other switch 53b is supplied with a voltage O from a potential point 44F, so that the output terminal as shown in FIG. At 57, a selection voltage V _S2 on the signal electrode side is generated in response to the clock signal CP. Furthermore, one electronic switch 54a of the electronic switch pair 54 has a voltage (1-2/a) at the connection point 44C.
V ₀ is supplied and the other electronic switch 5
4b is supplied with the voltage 2/aV ₀ of the connection point 44D, and the output terminal 58 outputs the non-selection voltage on the signal electrode side according to the clock signal CP as shown in FIG.
V _NS2 is obtained.

Incidentally, as each of the electronic switches shown in FIGS. 4 and 5, an electronic switch made of a complementary metal oxide semiconductor (CMOS) integrated circuit as shown in FIG. 6 can be used. In Figure 6, IN is the input terminal,
OUT is the output terminal, V _C is the control terminal, and V _S3 is the source power supply.

Here, with reference to FIG. 8, the overall operation of the liquid crystal matrix display device of FIG. 4 will be briefly described. 8th
As shown in the figure, scanning signals S1, S2, and S3 are generated from a scanning circuit 12 in response to a clock signal CP. Now, assuming that pixels e ₁₃ , e ₂₂ , and e ₃₁ are to be lit, the image signal is transferred from the line memory 24 to the eighth pixel.
The signals are generated as shown in FIGS. L1, L2, and L3. S
1 and L3 are at H level, the driving voltage V _X1 ,
Since V _Y3 is formed by selection voltages V _S1 and V _S2 , respectively, pixel _e13 is displayed, and similarly S2 and L2
When is at H level, pixel _e22 is displayed, and S3 and L
1 is at H level, pixel e ₃₁ is displayed.O Scan electrodes and signal electrodes related to pixels that are not lit or not displayed include, for example, the respective applied voltages to electrodes X1 and Y1 shown as an example in FIG.
Voltages similar to V _X1 and V _Y1 are applied, and the pixel is in a half-selected state or a non-selected state.

As described above in detail, this embodiment is advantageous because the selection/non-selection voltage generation circuit has a simple configuration and the electronic switch circuit section 50 and the like can be easily standardized.

Furthermore, since the resistance voltage divider circuit 43 is used, one of the reference potentials V ₀ can be easily changed by directly changing the magnitude of the power supply voltage V _DD or by changing the value of the resistor 42 .

By changing the reference voltage _V0 , the brightness and contrast of the liquid crystal can be adjusted. Particularly in this case, it is advantageous to use the variable resistor 42 because it can easily accommodate changes in device specifications regarding V ₀ .

Furthermore, setting or changing the optimum driving conditions is as follows:
This can be easily implemented by simply adjusting the main resistor 43C, and in this respect as well, it is highly flexible for various device specifications.

The present invention is not limited to the embodiments described above, and can be implemented in various modified forms. For example, instead of or together with the variable resistor 42 in the circuit of FIG.
4A, and in that case, use a temperature-sensitive resistor whose resistance-temperature characteristics correspond to the temperature change in the threshold voltage _Vth of the liquid crystal as shown in Figure 9. This is extremely advantageous since temperature changes in the threshold voltage can be automatically compensated for.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a liquid crystal matrix display device with a simple configuration in which the driving conditions of the liquid crystal can be easily set and the circuit can be standardized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a liquid crystal matrix display device according to the prior art, and FIGS. 2 and 3 are waveforms showing drive voltage waveforms when the device of FIG. 1 is driven with alternating current according to the voltage averaging method. 4 is a circuit diagram of a liquid crystal matrix display device according to an embodiment of the present invention, FIG. 5 is a wiring diagram showing the detailed configuration of the selection/non-selection voltage generation circuit in the device of FIG. 4, and FIG.
5 is a circuit diagram showing an example of an electronic switch that can be used in the circuit of FIG. 5. FIGS. 7 and 8 are time charts for explaining the operation of the circuit of FIGS. 4 and 5. FIG. 9 is a graph showing an example of the temperature characteristics of the liquid crystal used in the circuit of FIG. 10...Liquid crystal matrix panel, 12...Scanning circuit, 14, 26, 49...Inverter, 16,
18, 28, 30, 40... Selection/non-selection voltage generation circuit, 20, 32, 50... Electronic switch circuit, 22... Series-parallel conversion circuit, 24... Line memory, 42... For determining applied voltage variable resistance, 4
3...Resistance voltage divider circuit, 51-54...Electronic pair.

Claims (1)

[Scope of Claims] 1. A liquid crystal matrix panel having a plurality of scanning electrodes and signal electrodes arranged to intersect with each other so as to define a large number of matrix intersection points to be pixels, and a scanning circuit that generates a scanning signal. , a serial-to-parallel conversion circuit that converts the input image signal into parallel signals for one row, a line memory that stores the image signal for one row, and a line from one potential terminal side to the other potential terminal side. It has five resistors connected so as to substantially satisfy the following ratio relationship 1:1:(a-4):1:1 (where a is an arbitrary constant), When the potential of one potential terminal is V ₀ and the potential of the other potential terminal is 0, V ₀ , (1-1/a)V ₀ , (1-
2/a) A resistive voltage divider circuit adapted to take out the potential levels of V ₀ , 2/aV ₀ , 1/aV ₀ , 0, an electronic switch to which the potential level V ₀ of the resistor voltage divider circuit is supplied, and the above and a first electronic switch pair to which the potential level 0 of the resistive voltage divider circuit is supplied, and which open and close in opposite phases to each other in response to a synchronization signal to generate the selection voltage V _S1 on the scanning electrode side; Potential level of the above resistor voltage divider circuit (1-1/a)
It consists of an electronic switch to which V ₀ is supplied and an electronic switch to which the potential level 1/aV ₀ of the resistor voltage divider circuit is supplied, and they open and close in opposite phases to each other in accordance with the synchronization signal, and are connected to the scanning electrode side. It consists of a second electronic switch pair that generates the selection voltage V _NS1 , an electronic switch that is supplied with the potential level V ₀ of the resistive voltage divider circuit, and an electronic switch that is supplied with the potential level 0 of the resistive voltage divider circuit, a third electronic switch pair that opens and closes in opposite phases to each other in response to a synchronization signal to generate the selection voltage V _S2 on the signal electrode side; and a potential level (1-2/a) of the resistor voltage divider circuit.
It consists of an electronic switch to which V ₀ is supplied and an electronic switch to which potential level 2/aV ₀ of the resistor voltage divider circuit is supplied, and they open and close in opposite phases to each other according to the synchronizing signal, and a fourth electronic switch pair that generates the selection voltage V _NS2 ; a plurality of electronic switches connected to each of the scan electrodes and supplied with the selection voltage V _S1 on the scan electrode side; It consists of a plurality of electronic switches to which the non-selection voltage V _NS1 on the scanning electrode side is supplied, and opens and closes in opposite phases to each other according to the scanning signal to generate drive voltage waveforms to be supplied to each of the scanning electrodes. a first electronic switch circuit; a plurality of electronic switches each connected to each of the signal electrodes and supplied with the selection voltage V _S2 on the signal electrode side; and a plurality of electronic switches each connected to each of the signal electrodes and non-selected on the signal electrode side. It consists of a plurality of electronic switches to which voltage V _NS2 is supplied, and opens and closes in opposite phases to each other according to the image signal stored in the line memory to generate drive voltage waveforms to be supplied to each of the signal electrodes. A liquid crystal matrix display device comprising: a second electronic switch circuit; 2. A liquid crystal matrix display device according to claim 1, wherein a is a constant determined depending on driving conditions.