JPH0122938B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel control method in a data processing system.

The operation of a general channel device (hereinafter referred to as a channel) will be described below.

The channel receives or reads control information in a format given by a program from the central processing unit and main memory, and activates the input/output device. When an input/output operation between the channel input/output devices is started, the central processing unit is released from the input/output operation and can perform other processing. A channel transfers data to and from an input/output device through an input/output interface with the input/output device. The channel has registers that hold the address in the main memory where the data to be transferred is stored (or is stored) and the byte count representing the amount of data transferred, and transfer control is performed while updating these registers. Do the following.

I/O operations are initiated by I/O commands and channel command words (hereinafter referred to as CCWs). CCW is decoded and executed by channels and input/output devices. A CCW or a series of CCWs arranged to execute sequentially
A group forms a channel program.

Both I/O instructions and CCWs are read from main memory, but their format is common to various I/O devices. The input/output start command (SiO, SiOF) specifies a channel and an input/output device, and instructs the channel to execute a channel program prepared in the main memory. The start address of the channel program prepared in the main memory is stored at a fixed address location in the main memory. The channel specified by the I/O start command is a channel address indicating the start address of the channel program stored at a fixed address location in main memory.
Read the address word (CAW), then
The CCW specified by this CAW is sequentially read from the main memory to control a series of input/output operations with the input/output device. When the channel program finishes executing, the channel requests a termination interrupt from the central processing unit, and when this request is accepted, status information including the channel program termination result is stored at a fixed address location in main memory. The following will be explained with reference to figures. FIG. 1 shows the format of a CCW, in which 1 is a command section, 2 is a data address section, 3 is a flag section, and 4 is a byte count section. The command section 1 is further classified into the following seven types. Invalid code, sense command, channel jump command, reverse read command, write command, read command,
This is a control command. Among these, invalid codes and intra-channel jump commands are processed (executed) by the channel and are not notified to the input/output device.
The other five types of command codes are notified from the channel to the input/output device and decoded at the start of CCW execution. When an input/output device receives a command code, it initiates the input/output operation defined by the command code. Data address part 2
specifies the start address of the address location in the main memory of data transferred between the input/output device and the channel. The flag section 3 has the format shown in FIG. 2, and specifies how the CCW and channel program should be executed for the channel. The byte count section 4 specifies the number of bytes of data to be transferred between the channel and the input/output device by its CCW. When a channel reads the CCW onto its internal register in response to an input/output start command, the command part 1 is decoded by the channel and notified to the input/output device. The input/output device notifies the channel whether the command can be executed. If it is executable, data transfer will be started. When the channel receives notification that it can be executed, it reports completion of the input/output start command to the central processing unit.

When an input/output device requests a channel to transfer data, the channel transfers data for the number of bytes specified in the byte count section to the address location in main memory specified in the data address section. Perform the transfer. Data transfer requests are made from the input/output device in units of bytes, and the channel manages the number of transferred bytes by subtracting 1 from the byte count section each time. If the count section becomes zero during data transfer, the channel will
Determine whether bit 32 of the flag part is “ON” or not, and if it is “ON”, the currently executed CCW
A new file prepared in main memory following
Read the CCW, replace the registers in the channel except for the command part with the new CCW, and continue data transfer. This is a data chain, and in the case of a read command, a series of consecutive data transferred from an input/output device can be stored at different address locations in main memory.
Furthermore, at the time of a write command, data at different address locations in the main memory can be transferred to the input/output device as a series of continuous data. Since the data chaining is done by channels, it is not concerned with the input/output devices. If no data chain is specified when the count section reaches zero, the
To end CCW execution, the channel instructs the input/output device to end data transfer. The input/output device that has been instructed to terminate stops requesting data transfer and reports the completion of command execution to the channel.
If the count part of the CCW indicates a value larger than the number of bytes transferred by the I/O device, the I/O device must have reported completion of command execution before the count part reaches zero. become.

When the end of command execution is reported, the channel determines how to execute the channel program as follows, depending on the value of the count field and the contents of the flag field.

If the count part is zero and bit 33 of the flag part is "ON", a new CCW is read out from the main memory and the contents of the channel register including the command part are replaced with the contents of the new CCW and input. Notify the output device of the new command and execute the new CCW. This is called a command chain. If the count part is not zero, check bit 34 of the flag part, and if it is "ON", command chaining is performed in the same way as when the count part was zero.

If a chain of commands other than those described above is not performed, status information at the time when execution is completed is created and an input/output end interrupt is requested to the central processing unit.

When an input/output end interrupt request is accepted, the channel transfers the next address location of the executed CCW to a fixed address location in main memory, and
The updated byte count contents and status information are stored and the channel operation ends. The above is the general channel operation in the prior art.

Now, in a data processing system, there are cases where a plurality of data blocks of undefined length are continuously received. Possible methods for realizing this receiving operation using conventional technology include: first, issuing a read command for each block; second, using data chaining; and third, using command chaining. . In the first method, the central processing unit has to issue an input/output start command for each block, which increases the number of exchanges with the channels, which takes time and causes a decrease in system performance. . In the second method, since the received data block has an undefined length, there is no guarantee that it will match the prepared byte count, and data chaining will be inhibited at the point of mismatch. The third method has the disadvantage that there is no means to know the amount of data in each block. In other words, in a chain of commands, the updated byte/byte of the last executed CCW is
Only the contents of the count are notified, and the byte count of the CCW executed midway cannot be known.

An object of the present invention is to, in the case of continuously receiving a plurality of data blocks of undefined length as described above,
The object of the present invention is to improve the receiving operation, which caused a decrease in performance in the prior art, and to provide a channel device that can notify the number of bytes of each CCW by chaining, which was not possible with the prior art. Therefore, when the present invention receives an input/output instruction from the central processing unit, it reads a channel command word consisting of a command section, a data address section, a flag section, and a count section from the main memory, and inputs/outputs the contents of the command section. In a data processing system having a channel device that controls data transfer between a main storage device and an input/output device by notifying the device and updating the contents of the data address field and the count field when data is transferred, The channel command word storage area on the main storage device is configured so that a predetermined space is provided between each channel command word, and the flag section is configured to store the channel command word in the space section under certain conditions. It has a control bit that instructs to store state information and data transfer amount information within the device, and when the above specific condition occurs in the channel device, the above state information and data transfer amount information are stored in the channel command being processed.・Storing the channel command word in the space section at the next address position of the word, and reading out the channel command word at the next address position of the space section which has been stored, and based on the read channel command word. The feature is that the data transfer is continued.

The present invention will be explained below using examples. Figure 3 shows the CCW stored in the main memory and the registers in the channel, and in the figure, 10 is
CAW holding register, 20 is data address
Registers, 30 is a flag register, 40 is a byte count register, 50 is a status information register, 60 to 6N are CCW areas of main memory, 32
37 are the contents of the flag portion shown in FIG. 2, and 38 is a status storage instruction bit for instructing storage of status information. The CAW register 10 is a register that holds the address of the CCW to be executed next by the channel. When receiving an input/output start command, the CAW register 10 is a register that holds the address of the CCW to be executed next by the channel.
Stores a word to give the start address of the channel program. When the channel reads the CCW, it updates the contents of the CAW register 10 to indicate the address of the CCW to be executed next. The data address register 20, flag register 30, and byte count register 40 are registers that store the CCW that has been read out, and the channel stores the data address register as the CCW execution progresses. 20 and the contents of byte count register 40 are updated.
When a series of data transfers with the input/output device are completed and the input/output device reports completion of command execution, the byte count register 40 and
Depending on the contents of the flag register 30, an input/output end interrupt is requested or command chain processing is performed.・Bit 38 of register 30 (Status storage instruction.ST)
can be investigated. FIG. 4 is a block diagram of main parts of a control signal generation circuit in a channel according to an embodiment of the present invention. In the figure, the same numbers as in FIG. 3 indicate the same components, 60 is a zero detection circuit, 61 ~65
is an AND circuit, 66 to 69 are inverting circuits, 70 is an OR circuit, 71 is a byte count zero signal line, 72
73 is a data chain signal line, 74 is an input/output end interrupt signal line, 75 is a status information storage signal line, and 76 is a command chain signal line.

When the end of command execution is reported from the input/output device via signal line 72, flag register 3
When bit 38 (ST) of 0 is "OFF", the output of the AND circuit 65 is "ON", and command chaining is performed as in the prior art.
(ST) is “ON”, the output of the AND circuit 64 is “ON”, and the contents of the byte count register 40 of the channel register and the status information register 50 are the CCW of the main memory device indicated by the CAW register 10. Control is performed so that the data is stored in the area. Furthermore, after the storage, the CAW register 10 is updated to indicate the CCW to be executed next. Thereafter, similarly to the command chain, the CCW to be executed indicated in the CAW register 10 is read out and stored in each register of the channel, and the input/output operation is continued. That is, according to the present invention, when bits 33 (CC) and 38 (ST) of the flag register 30 are specified, the CCW area next to the CCW area currently being executed is used as a storage area, and the next execution is executed. The CCW will be the CCW in the area next to this storage area. Figure 5 shows the main memory in the embodiment.
The CCW area is shown, and side A in the figure shows an example of the contents before the input/output command is issued, and side B in the figure shows an example of the contents after the input/output command is completed. In the figure,
Assuming that the block length received with READ1 is 100 bytes, the CCW next to the CCW that specified READ1
The remaining byte count value 50 is stored in the area along with status information. Furthermore, assuming that the block length received in READ2 is 150 bytes, the remaining byte counter value is stored together with status information in the CCW area next to the CCW specified in READ2, which is 0 in this example. The following data are stored in the same manner, but the last CCW does not need to be specified by bits 33 (CC) and 38 of the flag register 30. The status information and remaining byte count value of the last CCW are stored at a fixed address (CSW) in main memory as an input/output instruction end interrupt.

As described above, according to the present invention, even when a plurality of data blocks of undefined length are continuously received in a data processing system, the reception processing can be easily realized without imposing a load on the central processing unit.

[Brief explanation of drawings]

Figure 1 shows the channel command word (CCW)
FIG. 2 is a diagram showing the format of the flag section. FIG. 3 is a diagram showing the relationship between the channel command word (CCW) stored in the main memory and registers in the channel. FIG. 4 is a block diagram of the main part of a control signal generation circuit in a channel according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating how the channel command word (CCW) area of the main memory device is used in the embodiment. . In the figure, 30 is a flag register, 40 is a byte count register, and 75 is a status information storage signal.

Claims (1)

[Claims] 1 When an input/output command is received from the central processing unit, the command section, data address section,
The channel command word consisting of a flag section and a count section is read out, the contents of the command section are notified to the input/output device, and the contents of the data address section and count section are updated during data transfer. In a data processing system having a channel device that controls data transfer between a storage device and an input/output device, a predetermined space is provided between each channel command word in the channel command word storage area on the main storage device. The flag section includes a control bit that instructs the space section to store state information and data transfer amount information in the channel device under the occurrence of a specific condition,
When the specific condition occurs in the channel device, the status information and data transfer amount information are stored in the space section located at the address next to the channel command word being processed, and the storage processing is further performed. A channel control method characterized in that a channel command word located at the next address position of a space portion that has been read is read out, and data transfer is continued based on the read channel command word.