JPH0123005B2 - - Google Patents
Info
- Publication number
- JPH0123005B2 JPH0123005B2 JP55072361A JP7236180A JPH0123005B2 JP H0123005 B2 JPH0123005 B2 JP H0123005B2 JP 55072361 A JP55072361 A JP 55072361A JP 7236180 A JP7236180 A JP 7236180A JP H0123005 B2 JPH0123005 B2 JP H0123005B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse width
- voltage
- output
- terminal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
- Pulse Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、パルス幅として加わる入力信号を時
間領域で操作して出力する波形変換回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform conversion circuit that operates an input signal applied as a pulse width in the time domain and outputs the resultant signal.
従来、第1図aに示す構成によるパルス幅変換
回路があり、bは各部の波形を示す。この回路は
周知の如く、パルスストレツチヤと称され時間軸
上の波形操作を行なうものである。この構成にお
いて、入力信号イが接地に対して正電位の期間ト
ランジスタTr1は導通状態となり、コンデンサC1
の端子電圧e1はほぼ接地電位となる。入力信号が
接地電位になるとトランジスタT1は非導通状態
となり、コンデンサC1は抵抗R1を通して電圧E1
で充電され、端子電圧e1はロの如く指数関数で上
昇する。さらに電圧比較器11の反転入力にはコ
ンデンサC1の端子電圧e1が加わり、非反転入力に
は基準電圧e2が加わる。電圧e1が基準電圧e2を越
えると電圧比較器11の出力電位は反転する。従
つて該電圧比較器11の出力波形はハのようにな
る。即ち入力信号のパルス幅をτx、出力信号のパ
ルス幅をτyとし、電圧e1が基準電圧e2を超える迄
の時間τbとすると入出力のパルス幅の関係はτy=
τx+τbとなる。ここで、τbはE1,R1,C1およびe2
によつて定まる一定のパルス幅である。従つてこ
のパルス幅変換回路によれば、入力信号のパルス
幅τxとE1,R1,C1に対応したパルス幅の出力信
号を得ることができるが、入力信号のパルス幅以
下の微小パルス幅を得ることはできない欠点があ
つた。 Conventionally, there is a pulse width conversion circuit having the configuration shown in FIG. 1a, where b indicates the waveform of each part. As is well known, this circuit is called a pulse stretcher and performs waveform manipulation on the time axis. In this configuration, the transistor T r1 is conductive while the input signal A is at a positive potential with respect to ground, and the capacitor C 1
The terminal voltage e 1 of is almost the ground potential. When the input signal goes to ground potential, the transistor T 1 becomes non-conducting, and the capacitor C 1 passes the voltage E 1 through the resistor R 1 .
The terminal voltage e 1 increases exponentially as shown in (b). Furthermore, the terminal voltage e 1 of the capacitor C 1 is applied to the inverting input of the voltage comparator 11, and the reference voltage e 2 is applied to the non-inverting input. When voltage e 1 exceeds reference voltage e 2 , the output potential of voltage comparator 11 is inverted. Therefore, the output waveform of the voltage comparator 11 is as shown in (c). That is, if the pulse width of the input signal is τ x , the pulse width of the output signal is τ y , and the time until the voltage e 1 exceeds the reference voltage e 2 is τ b , the relationship between the input and output pulse widths is τ y =
τ x + τ b . Here, τ b is E 1 , R 1 , C 1 and e 2
is a constant pulse width determined by . Therefore , according to this pulse width conversion circuit, it is possible to obtain an output signal with a pulse width corresponding to the input signal pulse width τ The drawback was that it was not possible to obtain the pulse width.
また他の従来例としてτxなるパルス幅の入力信
号を標本化によりA/D変換した後、デイジタル
符号に応じたτyなるパルス幅を出力する波形操作
により、入出力パルス幅の関係がτy=a・τxとな
るような方法があつた。この方法によれば、サン
プリング周期によつて定まる定数aを1以下にで
きるので、入力信号のパルス幅以下の出力を得る
ことができるが、回路が複雑になる点、A/D変
換を行うことにより出力パルス幅が入力パルス幅
の変化に対して不連続になる点、入力パルス幅が
狭い場合はサンプリング周波数を高くせねばなら
ず、技術的な困難性を伴なう等の欠点があつた。 As another conventional example, after A/D conversion is performed by sampling an input signal with a pulse width of τ There was a method that made y = a・τ x . According to this method, the constant a determined by the sampling period can be made less than 1, so it is possible to obtain an output that is less than the pulse width of the input signal, but the circuit becomes complicated and A/D conversion is not required. This has disadvantages such as the output pulse width becoming discontinuous with respect to changes in the input pulse width, and when the input pulse width is narrow, the sampling frequency must be increased, which is accompanied by technical difficulties. .
本発明は、上記したような欠点を解決するため
に、入力パルス幅を電圧に変換してパルス幅変調
器の制御入力に加えることを特徴とし、入力パル
ス幅に比例し、入力パルス幅より狭いパルス成分
を含む出力パルスを得る回路を提供するものであ
る。 In order to solve the above-mentioned drawbacks, the present invention is characterized in that the input pulse width is converted into a voltage and applied to the control input of the pulse width modulator, and the input pulse width is proportional to the input pulse width and narrower than the input pulse width. A circuit for obtaining an output pulse containing a pulse component is provided.
第2図は本発明による実施例を示す図で、aは
構成を示し、bは各部の波形を示す。主要構成は
抵抗R2,R3,R4トランジスタTr2から成る定電流
源12と、積分コンデンサC2と、放電用電子ス
イツチ13aと、パルス幅変調器16aから成
る。さらにパルス幅変調器16aはコンデンサ
C3、抵抗R1,R6,R7,R8,R9、トランジスタ
Tr3、電圧比較器11aおよび11b、フリツプ
フロツプ15で構成される。まず、放電パルスイ
が入力されると、放電用電子スイツチ13aで、
積分コンデンサC2の電荷は急速に放電する。ま
たインバータ13bも電子スイツチとして使用さ
れ、入力信号ロが加わると論理レベル“1”の期
間定電流源12を駆動する。このため積分コンデ
ンサC2の端子電圧ハは、瞬時の電圧をv、定電
流をi、時間をtとすればv=1/C2∫idtとなるの
で時間と共に直線的に増加し、その最終値は入力
信号のパルス幅に比例する。そしてC2の端子電
圧は放電パルスが加わるまで保持される。一方、
トリガパルスニがインバータ14に加わると電圧
比較器11aの入力は論理レベル“0”となりフ
リツプフロツプ15をセツトし、Q出力ホは立ち
上がる。このときトランジスタTr3のベースは、
抵抗R9を通してフリツプフロツプ15の出力
に接続されているので非導通であるから、コンデ
ンサC3は抵抗R1を通して+5Vで充電され、C3の
端子電圧トは指数関数曲線で上昇する。さらにコ
ンデンサC3の端子電圧が電圧比較器11bの反
転入力に印加されている電圧を越えるとフリツプ
フロツプ15はリセツトされ、トランジスタTr3
は導通状態となり、C3の電荷は急速に放電する。
ところで、R5a,R6,R7,R8の合成抵抗値が十分
大きければコンデンサC2の端子電圧ハは入力信
号のパルス幅に比例する。コンデンサC2の端子
電圧が接地電位の時、パルス幅変調器16aがト
リガパルスニにより起動されたとき、パルス幅変
調器16aの出力パルス幅はホに示した最小値τb
なるパルス幅になる。ところが、幅τxなる入力パ
ルスが定電流源12を駆動すると入力パルス幅に
応じたコンデンサC2の端子電圧が抵抗R5aを通し
て電圧比較器11bの反転入力に加算され比較電
圧が増加するので、出力パルス幅は増加する。入
力パルス幅がτxのときの出力はホに示すようにパ
ルス幅τyとなる。従つて入出力パルス幅の関係は
τy=a・τx+τbなる一次関数となり、出力パルス
幅τyは入力パルス幅τxに関連づけられる。ここ
で、パルス幅変調器16aの制御感度aは、定電
流12の出力電流と、コンデンサC2、および抵
抗R5a,R6,R7そしてR8で設定される定数であ
る。またτbはパルス幅変調器16aの抵抗R1と
積分コンデンサC3の値で定まる一定値である。
本発明は、a≦1に選ぶことにより、τxの変化分
Δτxに対するτyの変化分ΔτyをΔτxに比例し、Δτ
x
より十分小さな値にすることができる。 FIG. 2 is a diagram showing an embodiment according to the present invention, in which a shows the configuration and b shows waveforms of each part. The main components include a constant current source 12 consisting of resistors R 2 , R 3 , and R 4 transistors T r2 , an integrating capacitor C 2 , an electronic discharge switch 13 a, and a pulse width modulator 16 a. Furthermore, the pulse width modulator 16a is a capacitor.
C 3 , resistor R 1 , R 6 , R 7 , R 8 , R 9 , transistor
It consists of T r3 , voltage comparators 11a and 11b, and flip-flop 15. First, when a discharge pulse is input, the electronic discharge switch 13a
The charge on the integrating capacitor C 2 is rapidly discharged. Inverter 13b is also used as an electronic switch, and when input signal RO is applied, it drives constant current source 12 during the logic level "1" period. Therefore, if the instantaneous voltage is v, the constant current is i, and the time is t, then the terminal voltage C of the integrating capacitor C2 increases linearly with time , and the final The value is proportional to the pulse width of the input signal. The terminal voltage of C2 is then held until a discharge pulse is applied. on the other hand,
When the trigger pulse N is applied to the inverter 14, the input of the voltage comparator 11a becomes a logic level "0", setting the flip-flop 15, and the Q output H rises. At this time, the base of transistor T r3 is
Since it is connected to the output of flip-flop 15 through resistor R9 and is therefore non-conducting, capacitor C3 is charged with +5V through resistor R1 , and the voltage at the terminals of C3 rises in an exponential curve. Furthermore, when the terminal voltage of capacitor C3 exceeds the voltage applied to the inverting input of voltage comparator 11b, flip-flop 15 is reset and transistor T r3
becomes conductive and the charge on C3 rapidly discharges.
By the way, if the combined resistance value of R 5a , R 6 , R 7 , and R 8 is sufficiently large, the terminal voltage of capacitor C 2 will be proportional to the pulse width of the input signal. When the terminal voltage of the capacitor C2 is at ground potential and the pulse width modulator 16a is activated by the trigger pulse 2, the output pulse width of the pulse width modulator 16a is the minimum value τ b shown in E.
The pulse width will be as follows. However, when an input pulse with a width τ x drives the constant current source 12, the terminal voltage of the capacitor C2 corresponding to the input pulse width is added to the inverting input of the voltage comparator 11b through the resistor R5a , and the comparison voltage increases. The output pulse width increases. When the input pulse width is τ x , the output becomes the pulse width τ y as shown in E. Therefore, the relationship between the input and output pulse widths is a linear function of τ y =a·τ x +τ b , and the output pulse width τ y is related to the input pulse width τ x . Here, the control sensitivity a of the pulse width modulator 16a is a constant set by the output current of the constant current 12, the capacitor C2 , and the resistors R5a , R6 , R7 , and R8 . Further, τ b is a constant value determined by the values of the resistor R 1 and the integrating capacitor C 3 of the pulse width modulator 16a.
By selecting a≦1, the present invention makes the change Δτ y in τ y relative to the change Δτ x in τ x proportional to Δτ x , and Δτ
x
The value can be made much smaller.
以上説明したように本発明によれば簡単な回路
構成で、入力パルス幅と比例関係にあり、入力パ
ルス幅以下の微小偏位を得るパルス幅変換回路を
提供できる。 As described above, according to the present invention, it is possible to provide a pulse width conversion circuit which is proportional to the input pulse width and obtains a minute deviation smaller than the input pulse width with a simple circuit configuration.
第1図は従来のパルス幅変換回路図、第2図は
本発明による第1の実施例を示すパルス幅変換回
路、である。
11a,11b…電圧比較器、12…定電流
源、13a…放電用電子スイツチ、15…フリツ
プフロツプ、16a…パルス幅変調器、C2,C3
…積分コンデンサ、R1,R5a,R6,R7,R8…抵
抗。
FIG. 1 is a diagram of a conventional pulse width conversion circuit, and FIG. 2 is a pulse width conversion circuit showing a first embodiment of the present invention. 11a, 11b... Voltage comparator, 12... Constant current source, 13a... Electronic discharge switch, 15... Flip-flop, 16a... Pulse width modulator, C 2 , C 3
… Integrating capacitor, R 1 , R 5a , R 6 , R 7 , R 8 … Resistor.
Claims (1)
る定電流源と、該定電流源の出力電流で前記パル
ス幅τxに比例した端子電圧まで直線的に充電され
る第1の積分コンデンサと、端子電圧が指数関数
的に増加する第2の積分コンデンサと、一方の入
力端子に前記第2の積分コンデンサの端子電圧を
印加して他方の入力端子に印加した電圧と比較す
る第1の電圧比較器と、前記第1の積分コンデン
サの端子電圧に重みa(a≦1)を付けて前記第
1の電圧比較器の前記他方の入力端子に印加した
電圧に加算する手段と、一方の入力端子に前記第
1の積分コンデンサの端子電圧を印加して該端子
電圧のハイレベル中に他方の入力端子に印加した
トリガパルスで出力する第2の電圧比較器と、該
第2の電圧比較器の出力でセツトし、前記第1の
電圧比較器の出力でリセツトするフリツプフロツ
プとを備えて該フリツプフロツプの出力端子から
前記第2の積分コンデンサへの充電時定数で定ま
るパルス幅τbと前記パルス幅τxに重みaを付けた
パルス幅aτxとを加算したパルス幅τy=aτx+τbな
るパルスを得たことを特徴とするパルス幅変換回
路。1. A constant current source driven in proportion to an input signal with a pulse width τ x , and a first integrating capacitor that is linearly charged with the output current of the constant current source to a terminal voltage proportional to the pulse width τ x . a second integrating capacitor whose terminal voltage increases exponentially; and a first integrating capacitor whose terminal voltage is applied to one input terminal and compared with the voltage applied to the other input terminal. a voltage comparator; means for adding a weight a (a≦1) to the terminal voltage of the first integrating capacitor to the voltage applied to the other input terminal of the first voltage comparator; a second voltage comparator that applies the terminal voltage of the first integrating capacitor to its input terminal and outputs an output in response to a trigger pulse applied to the other input terminal while the terminal voltage is at a high level; and the second voltage comparator. a flip-flop that is set by the output of the voltage comparator and reset by the output of the first voltage comparator, and a pulse width τ b determined by the charging time constant from the output terminal of the flip-flop to the second integrating capacitor and the pulse. A pulse width conversion circuit characterized in that a pulse width τ y =aτ x +τ b is obtained by adding a pulse width aτ x with a weight a to the width τ x .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7236180A JPS56169420A (en) | 1980-05-30 | 1980-05-30 | Pulse width converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7236180A JPS56169420A (en) | 1980-05-30 | 1980-05-30 | Pulse width converting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56169420A JPS56169420A (en) | 1981-12-26 |
| JPH0123005B2 true JPH0123005B2 (en) | 1989-04-28 |
Family
ID=13487093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7236180A Granted JPS56169420A (en) | 1980-05-30 | 1980-05-30 | Pulse width converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56169420A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6775365B2 (en) * | 2016-09-16 | 2020-10-28 | ローム株式会社 | Insulated switching power supply and power supply control |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710113Y2 (en) * | 1977-08-30 | 1982-02-26 |
-
1980
- 1980-05-30 JP JP7236180A patent/JPS56169420A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56169420A (en) | 1981-12-26 |
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