JPH0123006B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width extension circuit that is a basic logic circuit element when configuring a fail-safe information processing device.

In the field of railway signal systems, information processing using a negative mode is known as a fail-safe information processing method. Negation mode refers to a mode in which there is always an output voltage, but the control signal has no voltage. When the constant output voltage V is set to a truth value of 1, the control signal corresponds to a truth value of 0, and all The truth value degenerates to 0 due to circuit failure.

When a train enters a certain blocked section, information about the train entry is processed in this negative mode. According to this information processing mode, in the event of a failure in the track circuit or a failure in the processing circuit that receives the information, a signal with a truth value of 0 corresponding to ``a train is in the blocked section'' will be generated, so that the following train It is possible to prevent people from entering the closed section and maintain security. Further, if a truth value of 0 occurs in the output when there is no control signal, there is an advantage that it can be determined as a failure.

In this negative mode information processing system,
There are cases where it is desired to extend the time width of the output pulse. For example, when driving a relay using the output pulse of a wheel detector, the pulse width of the output pulse of the wheel detector is too short to drive the relay. It is necessary to extend the time span enough for driving.
In this case, the fail-safe nature of the information processing system in negative mode is not compromised; in other words, in the event of a circuit failure, this is equivalent to a train stopping within the blocked section. To,
A pulse width extension circuit is required so that the pulse width will not be shortened due to circuit failure or the output pulse will continue to be generated.

It is an object of the present invention to provide such a fail-safe pulse width extension circuit, ie, a pulse width extension circuit in which an output pulse is generated or the pulse width is extended due to a circuit failure.

In order to achieve this object, the present invention provides a pulse width extension circuit that includes a delay circuit and an AND storage circuit and extends the pulse width of an input signal, wherein the input signal is always at a voltage and is a control signal. is given in a voltage-free mode, the delay circuit is a circuit that generates an output pulse after a certain time delay after the input voltage is input, and does not generate an output in the event of a circuit failure, and the AND memory circuit has two Only when there is an input voltage at one of the two input terminals,
The circuit stores and outputs the input voltage input to the other input terminal, and the output voltage disappears due to circuit failure, and the input signal is connected to the input terminal of the delay circuit,
The delay circuit is connected to the other input terminal of the AND storage circuit, the output of the delay circuit is connected to the one input terminal of the AND storage circuit, and the output is taken out from the AND storage circuit. shall be.

The delay circuit and the AND storage circuit described above are hereinafter referred to as an asymmetric error delay circuit and an asymmetric error AND storage circuit because the output characteristic when the circuit fails is an asymmetrical error with respect to the output when the circuit is normal.

In the pulse width extension circuit with the above configuration, when the input signal changes from having a voltage to having no voltage corresponding to the control signal, the asymmetric error AND memory circuit changes the voltage input to the other input terminal to no voltage. , preset to no output voltage state.
In this way, when the asymmetric error AND memory circuit is directly preset by the input signal, the input signal is This provides the advantage of immediate response to signals.

Next, when the input signal changes from no voltage to voltage, the asymmetric error delay circuit generates a delayed output pulse with a fixed time delay after the input signal changes to voltage. The delayed output pulse is applied to one input terminal of the asymmetric error AND storage circuit.

At this time, the input signal with voltage has already been applied to the other input terminal of the asymmetric error AND storage circuit. Therefore, the asymmetric error AND storage circuit stores and outputs the input voltage input to the other input terminal using the delayed output pulse as a set signal. As a result, a pulse width extension output that is extended according to the time element of the delayed output pulse is obtained from the asymmetric error AND storage circuit.

If a circuit failure occurs in the asymmetric error delay circuit,
Since no delayed output pulse is produced, the asymmetric error AND storage circuit is not set. Further, if a circuit failure occurs in the asymmetric error AND storage circuit, its output voltage disappears. In either case, the pulse width is not shortened and is therefore fail-safe.

The pulse width extension circuit according to the present invention is a waveform operation that handles fail-safe on the time axis, and is clearly distinguished from logical operation. Waveform operations are operations on the time axis, while logical operations are operations on the amplitude axis orthogonal to the time axis, and the two are logically orthogonal and completely different.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The content of the present invention will be specifically described below with reference to the accompanying drawings, which are examples. FIG. 1 is a circuit diagram of a pulse width extension circuit according to the present invention, and FIG. 2 is a time chart thereof. In Fig. 1, 1 is an input pulse in a mode in which the voltage disappears as a signal;
That is, an input terminal to which a negative mode input pulse is input, 2 a power input terminal to which a hot side power supply voltage +V ₀ is input, and 3 an output terminal.

4 is a phase inversion circuit using an asymmetric error AND circuit. An asymmetric error AND circuit is a logic circuit in which when the logic circuit itself fails, the output only erroneously becomes either the truth value 1 or the truth value 0. This asymmetric error logic circuit is published in Japanese Patent Publication No. 45-29054 (Fail-Safe Logic Operation Oscillator),
30777 (Fail-Safe Three-Value Logic Circuit) or Electrical Research Institute Research Report No. 695 (1962), etc., it has become publicly known, and has a circuit configuration as shown in FIG. 3, for example. In FIG. 3, RCA is a rectifier circuit that determines the output polarity, and A is a logic operation oscillator. This logical operation oscillator A oscillates only when positive input voltages are applied to all input terminals a, b, and c, and produces a positive output at the output terminal e. When driving logical operation oscillator A with one input, input terminals a, b, and c are used in common; when driving with two inputs, input terminals a, b, and c are used in common.
Any two of b and c may be made common, and inputs may be given to this common input terminal and the remaining one input terminal. In addition, in FIG. 3, transistors Q ₁ to ^{Q 4} are replaced with PNP transistors,
A logic operation oscillator with a negative input, which oscillates only when a negative input is applied to all input terminals a, b, and c, is also known from the above-mentioned publication. Also,
By reversing the directions of the diodes D ₁ and D ₂ and making the transistor Q ₅ an NPP type, it is possible to configure a rectifier circuit RCA in which the output polarity at the output terminal e is negative.

In the embodiment shown in FIG. 1, the asymmetric error logic circuit 4 has a negative voltage doubler rectifier circuit RCA ₁ connected in cascade to a logical operation oscillator A that oscillates when all inputs become positive DC voltages, Voltage doubler rectifier circuit RCA ₁
A negative polarity DC voltage -V is taken out as an output.

C ₁ is a differentiating circuit having a time constant determined by the input resistance of the asymmetric error logic circuit 4, and D ₁ is a clamp diode that clamps the differential output of this differentiating circuit C ₁ to the hot side power supply voltage +V ₀ of the asymmetric error logic circuit 4. It is.

5 is a memory circuit, _C2 is a differential circuit having a time constant determined by the input resistance of the memory circuit 5, and _D2 is a clamp diode.

The memory circuit 5 operates as a self-holding circuit that is set by the differential output of the differentiating circuit _C2 inputted through the input line H and reset at the leading edge of the input pulse applied through the input line H. This memory circuit 5 includes an asymmetric error logic circuit 6 similar to the asymmetric error logic circuit 4, that is, a logic operation oscillator A ₂ that oscillates when all inputs are of positive polarity.
A voltage doubler rectifier circuit that determines the output polarity (positive polarity)
An asymmetrical error logic circuit 6 having RCAs ₂ connected in series is provided, and the output of this asymmetrical error logic circuit 6 is fed back via a feedback circuit 7 to an input line d serving as a set input.

Next, the operation of the pulse width extension circuit will be explained with reference to the time chart of FIG.

First, as shown in Figure 2 a, voltage is always present.
The input pulse in the negative mode to input terminal 1 given by is in the "no voltage" state, that is, the "signal present" input state at t ₀ , and this input state remains for T ₁ hour from t ₀ to t ₁ . Suppose it continues.
This "no voltage" negative mode signal corresponds to, for example, an entry detection signal when a train enters a blocked section.

When the input pulse becomes "no voltage", the asymmetric error logic circuit 6 of the memory circuit 5 to which the input pulse is input via the input line A stops oscillating, so the output pulse appearing at the output terminal 4 is as shown in FIG. As shown in the figure, the state becomes "no voltage". That is, the memory circuit 5 is preset to a "no voltage" state at the leading edge of the input pulse.

Next, at time t ₁ , when T ₁ hour has elapsed from time t ₀ , when the input pulse becomes "voltage present" as shown in Figure 2a, at that moment, the trailing edge of the input pulse becomes as shown in Figure 2b. A differential output from the differential circuit _C1 is obtained. This differential output is clamped to the hot side power supply voltage + _V0 by the action of the clamp diode _D1 .

The differential output is input to the asymmetric error logic circuit 4 through the input line LO. When this differential output is input, the asymmetric error logic circuit 4 performs an oscillating operation, and as shown in _FIG . V is obtained. This DC output -V continues for a time Td depending on the time constant of the differentiating circuit _C1 from time _t1 , and becomes "no voltage" again at time _t2 after time Td has elapsed.
becomes. Therefore, the asymmetric error logic circuit 4 functions as a circuit that shapes the waveform of the output of the differentiating circuit and at the same time inverts the phase.

At t ₂ , the DC output of the output line is “no voltage”
At the moment when , a differential output from the differentiating circuit _C2 as shown in FIG. 2d is obtained at the trailing edge of the pulse. This differential output is clamped to the hot side power supply voltage + _V0 by the action of the clamp diode _D2 . Then, when this differential output is input to the memory circuit 5 via the input line I, the input pulse input to the memory circuit 5 via the input line I is
As shown in Figure a, since the state is generally "voltage present", the input conditions for the asymmetric error logic circuit _A2 constituting the memory circuit 5 are satisfied, the asymmetric error logic circuit 6 operates in oscillation, and the output terminal The output appearing at 3 becomes "voltage present" as shown in FIG. 2e. The polarity of the output appearing at output terminal 3 is determined by the voltage doubler rectifier circuit.
The RCA ₂ has the same polarity (positive polarity) as the differential output at the input line port on the set side, and this is fed back to the set side via the feedback circuit 7. As a result, the memory circuit 5 is self-maintained by the feedback input, so even if there is no differential output input to the set side, the output from the output terminal 3 of the memory circuit 5 is as shown in FIG. As shown in e,
It is maintained in the “voltage present” state. That is, the memory circuit 5 operates with the differential output at the trailing edge of the input pulse input to the input terminal 1 as the set input. In this case, the time point at which the memory circuit 5 is set is
Since it is time _t2 when a differential output as shown in FIG. 2d is generated at the input line ho on the set input side, the input pulse is delayed by the time Td from time _t1 when the input pulse becomes "voltage present". That is, on the output terminal 3 side, a negative mode output pulse delayed by the time Td is obtained.

Next, the fail-safe performance of this pulse width extension circuit in the event of a circuit failure will be described. First, if the clamp diode D ₁ or D ₂ has a short-circuit fault, the asymmetric error logic circuit 4 or 6 will not oscillate. Therefore, the output of output terminal 3 is “signal present”
It is fail-safe because it will be extended to the “no voltage” side corresponding to .

If the differentiating circuit C ₁ or C ₂ is short-circuited, the input voltage is lower than the oscillation start voltage of the asymmetric error logic circuit 4 or 6, so the asymmetric error logic circuit 4 or 6 does not oscillate and becomes fail-safe.

If the clamp diode D ₁ or D ₂ is disconnected,
Since the clamping effect is eliminated, the input becomes lower than the oscillation start voltage of the asymmetric error logic circuit 4 or 6, and the asymmetric error logic circuit 4 or 6 does not oscillate.
It is fail safe.

If the differentiating circuit _C1 or _C2 is disconnected, there is no input to the asymmetric error logic circuit 4 or 6, and the asymmetric error logic circuit 4 or 6 does not oscillate.
It is fail safe.

As can be understood from the above description, the circuit 8 including the asymmetric error logic circuit 4, the capacitors C ₁ , C ₂ and the clamp diodes D ₁ , D ₂ has no output voltage at all times and only inputs when the input voltage is present. An asymmetric error logic circuit is constructed which produces an output with a delay of a certain time Td from time and which does not produce an output due to a circuit failure. Furthermore, the memory circuit 5 is an asymmetric error AND memory circuit that performs information processing in a negative mode in which the output voltage disappears when an input signal is applied, and does not produce an output due to a circuit failure. The pulse width extension circuit according to the present invention has a circuit configuration in which these circuits 8 and 5 are connected by lines A and E.

FIG. 4 is a circuit diagram of another embodiment of the pulse width extension circuit according to the present invention. This embodiment shows a specific example where the period of the input pulse applied to the input terminal 1 is shorter than the period of the reset signal. In the figures, the same reference numerals as in FIG. 1 indicate functionally identical parts. The voltage doubler rectifier circuit RCA ₁ constituting the asymmetric error logic circuit 9 is set so that its output has positive polarity, and serves as a buffer circuit for the input signal.

The UJT is a single junction transistor, is supplied with an operating power supply voltage Vs, and forms a relaxation oscillation circuit together with resistors R ₁ , R ₂ , R ₃ and capacitor C ₃ . C ₄ is a coupling capacitor and D ₃ is a clamp diode.

Next, the operation of the above circuit will be explained with reference to the time chart of FIG.

First, before a negative mode input pulse P (pulse width P) with a period T ₂ as shown in FIG. The asymmetric error logic circuit 9 is in oscillation operation, and a positive DC voltage is also generated on its output line. This DC voltage charges the capacitor C ₃ at a period T ₃ according to the time constant determined by the resistor R ₁ (FIG. 5b). Here, the period T ₃ is T ₃ ≫ (T ₂ - P)
There is a relationship between When the voltage at point C, which is the charging voltage of capacitor _C3 , exceeds the peak point voltage of the single junction transistor UJT, the single junction transistor UJT oscillates, and the two points on its base side produce a pulse q as shown in Figure 5 c. ₁ occurs. This pulse q ₁ passes through a coupling capacitor C ₄ and is clamped to the hot side supply voltage V ₀ by a clamp diode D ₃ (Fig. 5d).
and is applied to one of the inputs of the memory circuit 5 through a line ho. Since a positive DC voltage is input to the other input of the memory circuit 5 via the input line A, the input conditions for the asymmetric error logic circuit 6 constituting the memory circuit 5 are established, and the asymmetric error logic circuit 6
performs an oscillating operation, and a positive DC voltage determined by the voltage doubler rectifier circuit RCA ₂ is generated at its output terminal 3. Since this DC voltage is fed back to the input line ho side via the feedback circuit 7, the memory circuit 5 is self-retained, and even if the pulses q ₁ and q ₂ (Fig. 5 c, d) disappear, the output terminal 3 remains unchanged. is positive polarity DC voltage +V
continues to occur (Fig. 5e).

However, when a negative mode input pulse P with a period T ₂ is input to the input terminal 1 at time t ₀ , the input conditions of the asymmetric error logic circuits 9 and 6 become "no voltage", so the asymmetric error logic circuits 9 and 6 The oscillation operation of the output terminal 6 is stopped, and the output of the output terminal 3 is set to the "no voltage" state (FIG. 5e).

From the time one input pulse P disappears until the next input pulse P is input, the input terminal 1 is "with voltage", but the period T ₂ of the input pulse P causes the single junction transistor UJT to oscillate. Since the relationship T _{3 ≫} (T ₂ - P) exists for a charging period T ₃ that _is sufficient for (shown by the broken line in FIG. 5b), and the single junction transistor UJT cannot oscillate (shown by the dotted line in FIG. 5c). Therefore, the input pulse P has a period
While the voltage is input at _T2 , the input conditions of the asymmetric error logic circuit 6 constituting the memory circuit 5 are not satisfied, and the output of the output terminal 3 continues to be set to the "no voltage" state (FIG. 5e).

The input pause time of the input pulse P is the charging period T ₃
If the length is longer, the DC voltage generated on the output line of the asymmetric error logic circuit 9 will cause the capacitor C ₃
is sufficiently charged, the single junction transistor UJT oscillates, and an oscillation pulse q ₁ is generated. Therefore, the asymmetric error logic circuit 6 that constitutes the memory circuit 5 oscillates, and the output of the output terminal 3 becomes "with voltage", and at the same time, it is self-maintained by the feedback input via the feedback circuit 7, and the output of the output terminal 3 becomes "with voltage". The state will be reset.
In this case, since the reset time _t2 is delayed by the charging period Td from the leading edge _t1 of the input pulse P input last, the output terminal 3 has
An output pulse delayed by the time Td will be obtained. (Figure 5e).

In Figure 4, if T ₃ < T ₂ -P, the first
The operation is similar to the one shown in the figure. This will be explained with reference to the time chart in FIG. First, when a negative mode input as shown in FIG. 6a enters the line in FIG. 4, an input pulse P is generated and the memory circuit ₅ is reset.
Since an output pulse q ₁ is generated at the UJT (Fig. 6c),
The memory circuit 5 is set by the output pulse q ₂ of the clamp circuit supplied through the line ho, producing an output voltage at its output terminal 3 (FIG. 6e). That is, each time a negative mode input is input to terminal 1, the pulse width is extended by time Td.

Next, the fail-safe property of the above pulse width extension circuit will be explained.

First, resistors R ₁ , R ₂ , R ₃ or capacitor C ₃
If a disconnection failure occurs or a failure occurs in the single junction transistor UJT, the oscillation pulse q ₁ cannot be obtained, so the asymmetric error logic circuit 6 does not oscillate and is fail-safe. Furthermore, since AC coupling is provided by the capacitor C ₄ and the clamp diode D ₃ , if these are broken, the oscillation pulse q ₁ will not be transmitted to the asymmetric error circuit 6, thus providing a fail-safe condition.

Furthermore, regarding the case where a failure occurs in the voltage doubler rectifier circuit RCA ₁ shown in Fig. 4, for example, the capacitor shown in Fig. 3
For example, if C ₀ is short-circuited, there is a risk that the power supply voltage V ₀ will occur at the line in Figure 4. However, when the standoff ratio of the single junction transistor UJT is η, the condition of V ₀ ≪ηVs is By designing the power supply voltage Vs of the single-junction transistor UJT to a satisfactory level, it is possible to stop the oscillation operation of the single-junction transistor UJT in the event of a failure as described above, which is fail-safe. In addition,
Instead of the single-junction transistor UJT, a PUT (Program mable
Unijunction Transistor) can also be used.

Furthermore, in the pulse width extension circuit shown in Fig. 4, even when no input pulse P is input to input terminal 1, the single junction transistor UJT oscillates at a constant period, and an oscillation pulse q ₁ is repeatedly generated at a constant period. Therefore, there is an advantage that the asymmetric error logic circuit 6 can be constantly excited by the oscillation pulse _q1 .

In the above embodiment, the asymmetric error logic circuits 4, 6,
9 is composed of logic circuits A ₁ and A ₂ that oscillate when the input polarity is positive, but in addition, it is composed of logic circuits that oscillate when the input polarity is negative, or It can also be constructed from a logic circuit that oscillates when the polarity is positive and negative.

As an example of these modifications, FIG. 7 shows a specific example in which the asymmetric error logic circuits 4 and 6 in FIG. 1 are constructed by logic circuits B ₁ and B ₂ that oscillate when the input polarity is negative. ing. However, the hot side power supply voltage is −V ₀ , and the clamp diode
It is necessary to reverse the directions of D ₁ and D ₂ .

By the way, the asymmetric error logic circuit 9 in FIG.
For convenience of explanation, this is a buffer circuit inserted, and when configuring line 1, the asymmetric error logic circuit 9
The input and output of the asymmetric error logic circuit 9 will be as shown in FIG. , the functional identity remains intact. If line a in Fig. 4 is constructed by line a', then
The pulse width extension circuit shown in the figure is expressed by a block diagram as shown in FIG. 8, similar to that in FIG. In other words, there is an asymmetric error delay circuit 8 which does not always have an output voltage and produces an output after a fixed time delay from the time of input only when the input voltage is present, and which does not produce an output due to a circuit failure. A circuit configuration that performs information processing in a negative mode in which the output voltage disappears when a signal is applied, and is provided with an asymmetric error storage circuit 5 that does not produce an output due to a circuit failure, and these are connected by lines A and E. becomes.

In FIG. 8, the asymmetric error delay circuit 8 in the one shown in FIG. 1 produces the output pulse in FIG. _2d only after the rising edge t1 in FIG.
In the case shown in the figure, the output as shown in Figure 5d is produced only when there is an input of (T ₂ - P), so the information of the negation mode where the input voltage is always present and the output is produced when the input voltage disappears. information processing, which is the opposite of processing;
In other words, information processing is performed in a fixed mode. Information on the negative mode is often used as information on train entry into a blocked section, whereas information on the negative mode is often used as information on train exit from the blocked section.

The memory circuit 5 in FIG. 8 always has an output voltage, and when a signal (input pulse) is input, the output voltage disappears, so it operates as a negative mode logic circuit.

Therefore, as is clear from the abstracted block diagram of FIG. 8, the pulse width extension circuits shown in FIGS. The input signal given in the negative mode is directly input as a reset signal to the input terminal on the side where the memory is lost, while the input signal given in the negative mode is inputted to the input terminal on the side where the AND memory circuit 5 can store the memory. It can be said that the configuration is such that the asymmetric error delay circuit 8 processes this as a fixed mode and inputs it as a set signal.

Furthermore, in order to further extend the pulse width, the circuit shown in FIG. 8 can be connected in cascade to form a circuit configuration as shown in FIG. 9. In this case as well, the output pulse width is extended in the event of a circuit failure in each part, so it is fail-safe.

In addition, in FIG. 8, between the input terminal 1 and the asymmetric error delay circuit 8 (to the line), or between the input terminal 1 and the asymmetric error AND storage circuit 5 (to the line), or between the asymmetric error delay circuit 8 and the asymmetric Between the error logical AND storage circuit 5 (line ho),
It is clear that even if an asymmetric error amplifier circuit whose output voltage disappears due to a circuit failure or an asymmetric error logic circuit shown in FIG. 3 is inserted, the overall function will not change.

As described above, according to the present invention, the output pulse disappears or the pulse width is extended due to a circuit failure, resulting in a fail-safe situation, such as when driving a relay in negative mode information processing. Therefore, it is possible to provide a fail-safe pulse width extension circuit which is very suitable when there is a need to extend the pulse width.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a pulse width extension circuit according to the present invention, FIG. 2 is a time chart thereof, and FIG. 3 is a circuit diagram of an example of an asymmetric error logic circuit constituting the pulse width extension circuit according to the present invention. FIG. 4 is a circuit diagram of another embodiment of the pulse width extension circuit according to the present invention, FIGS. 5 and 6 are time charts thereof, and FIG. 7 is another embodiment of the pulse width extension circuit according to the present invention. The circuit diagram in Figure 8 is the circuit diagram in Figure 1.
FIGS. 4 and 7 are block diagrams of a pulse width extension circuit according to the present invention which abstractly illustrate the embodiments shown in FIGS. 4 and 7, and FIG. 9 is a block diagram of yet another embodiment. 1, 2...Input terminal, 5...Asymmetric error AND storage circuit, 4, 6...Asymmetric error logic circuit, 8...Asymmetric error delay circuit.

Claims (1)

[Scope of Claims] 1. A pulse width extension circuit that extends the pulse width of an input signal, including a delay circuit and an AND memory circuit, wherein the input signal has a constant voltage and the control signal has no voltage. The delay circuit is a circuit that generates an output pulse with a certain time delay after the input voltage is input, and does not generate an output in the event of a circuit failure. Only when there is an input voltage at one of the input terminals,
The circuit stores and outputs the input voltage input to the other input terminal, and the output voltage disappears due to a circuit failure, and the input signal is connected to the input terminal of the delay circuit,
The delay circuit is connected to the other input terminal of the AND storage circuit, the output of the delay circuit is connected to the one input terminal of the AND storage circuit, and the output is taken out from the AND storage circuit. Pulse width extension circuit. 2 The delay circuit and the AND storage circuit are:
2. The pulse width extension circuit according to claim 1, wherein the pulse width extension circuit is connected to a hot side power source by a clamped capacitor coupling. 3. The pulse width extension circuit according to claim 1 or 2, wherein the delay circuit is a relaxation oscillation circuit using a single junction transistor. 4. The delay circuit includes a first differentiating circuit that differentiates the trailing edge of the input signal, a circuit that shapes the waveform of the output of the first differentiating circuit and at the same time inverts the phase, and a circuit that differentiates the trailing edge of the output of the circuit. The pulse width extension circuit according to claim 1 or 2, characterized in that the pulse width extension circuit is constructed by sequentially connecting a second differentiating circuit with a second differentiation circuit.