JPH0123799B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In order to make the audio content understandable during high-speed playback such as double speed or triple speed on a video tape recorder or recording machine, it is necessary to restore the original pitch of the audio. The so-called helium audio in an underwater house is also difficult to understand unless it is returned to its original pitch.

Conventionally, many pitch converters of this type have been proposed. However, one that is inexpensive and has sufficient performance has not yet been realized.

The present invention provides a pitch converter that can be realized at a price that can be applied to consumer products and has sufficient clarity.

Conventionally, in order to convert the pitch to lower the pitch, the input audio signal is thinned out to a certain length, and the time axis of the thinned out signals is expanded and connected. One method is to use random access memory (RAM). This combines a RAM and an address multiplexer to allow writing and reading to be performed at the same time, and the increase speed of the write address and read address is different.When lowering the pitch, the increase speed of the write address is faster than that of the read address. Enlarge. In this method, thinning occurs naturally by overtaking or overtaking write addresses and read addresses. However, at this time, a level jump occurred in the signal waveform and a large click noise was generated, and this noise occurred several to ten times per second, making it extremely difficult to hear.

This invention uses random access memory,
The read address is increased at a constant rate, but the write address is increased intermittently in relation to the read address, and the writing is started and stopped at the zero-crossing point of the input audio signal, so that the segments are separated from each other. Next, there is no waveform discontinuity or large slope change, no click noise occurs, and the S/N ratio is very high.

FIG. 1 shows an example of the present invention, where 10 is a random access memory (RAM), which has a configuration of, for example, 1024 words. Then, the input audio signal from the terminal 20 is converted into a digital signal, for example, 8-bit data, by the A/D converter 30, and the data is transferred to the RAM.
Give 10 inputs. Further, 8-bit data obtained from the output of the RAM 10 is converted into an analog signal by a D/A converter 40, and an output audio signal is taken out at a terminal 50.

On the other hand, separate clocks from the timing pulse generation circuit 60 are written to the address counter 70.
W and the read address counter 70R, the outputs of the counters 70W and 70R are supplied to the input terminals A and B of the multiplexer 80, the timing pulse from the timing pulse generation circuit 60 is supplied to the switching terminal S of the multiplexer 80,
A 10-bit address signal is taken out from the multiplexer 80 and supplied to the address terminal of the RAM 10. In this invention, the pitch is 1/N (N>1)
write address counter 70W.
The frequency of the clock supplied to the read address counter 70R is set to be N times that of the clock supplied to the read address counter 70R. N need not be an integer. Additionally, a write enable signal from the timing pulse generator circuit 60 is supplied to the RAM 10.

As shown in FIG. 5, when the addresses of 1024 words of the RAM 10 are schematically expressed as a ring, the write address specified by the arrow W is determined by the output of the write address counter 70W, and the address specified by the read address counter 70R is determined by the output of the read address counter 70R. The read addresses designated by arrows R are then changed in the clockwise direction in the figure.

In the present invention, the read address is increased at a constant speed V, while the write address is increased intermittently as follows.

That is, in a certain state as shown in FIG. 6A, the write address is stopped. Even in this state, the read address is increased at a constant speed V. Then, when the read address catches up with the write address and the difference between the write address and the read address becomes α as shown in FIG. 6B, the write address is started. Therefore, the output of the write address counter 70W and the output of the read address counter 70R are subtracted by the subtracter 9.
0 to subtract the latter from the former, and the subtracted output is supplied to the comparator 100 and compared with the reference value α,
When the difference between the write address and the read address reaches α, a start signal is supplied from the comparator 100 to the start-stop control circuit 110.

However, the write address is not started immediately when the difference between the write address and the read address reaches α, but is started from the zero-crossing point in one direction of the input audio signal after the difference reaches α. Therefore, data from the A/D converter 30 is supplied to a one-way zero cross detection circuit 120 to detect a zero cross of the input audio signal, for example from negative to positive, as shown in FIG. If the most significant bit of the data is set to 0 at the negative part of the input audio signal and 1 at the positive part, the zero cross from negative to positive will occur at the time _t0 when the most significant bit changes from 0 to 1. A detection signal can be obtained. Then, the detection signal is supplied to the start/stop control circuit 110.

In this way, the start signal from the comparator 100 and the detection signal from the one-way zero cross detection circuit 120 detect the zero cross from negative to positive of the input audio signal after the difference between the write address and the read address becomes α. At this point, a start signal is supplied from the start/stop control circuit 110 to the write address counter 70W to start the counter 70W, that is, the write address.

The write address is N・as shown in FIG. 6C.
Increase at a rate of V. Even in this state, the read address is increased at a constant speed V. Writing and reading in this state are as shown in FIG. 4, that is, the figure shows the case where N=3, and the contents of the write address counter 70W correspond to the contents of the read address counter 70R, that is, the write address corresponds to the read address. The data changes at a rate N times faster, and writes and reads are performed at a rate of one read for every N writes.

Then, as shown in FIG. 6D, when the write address increases by β after the start, the write address is stopped. Therefore, the clock from the timing pulse generation circuit 60 is supplied to the write address run length counter 130, and this clock is counted from the time when the start signal is obtained from the start/stop control circuit 110, that is, from the time when the write address starts, and β When the count is counted, a stop signal is supplied from the counter 130 to the start/stop control signal 110.

However, the write address is not stopped immediately when the write address increases by β after the start, but is stopped at the above-mentioned zero-crossing point from negative to positive of the input audio signal after the write address increases by β. That is, the stop signal from the write address run length counter 130 and the detection signal from the one-way zero cross detection circuit 120 described above determine the zero cross from negative to positive of the input audio signal after increasing by β from the start. At this point, the start/stop control circuit 110 supplies a stop signal to the write address counter 70W to stop the counter 70W, that is, the write address.

Then, the above-described operations are repeated.

In this case, α is chosen to be around 1/4 to 1/2 of the address. However, α does not require much precision.
Therefore, as shown in the figure, a subtracter 90 and a comparator 100
Instead of configuring it with , it is also possible to configure it with a simple gate combination circuit that can detect when the difference between the write address and the read address falls within a certain range.

Further, the upper limit of β is set so that the write address does not overtake the read address, and the lower limit is set so that the difference between the write address and the read address is larger than α. In practice, β is chosen to be about 1/2 of the address. It does not necessarily have to be a fixed number, and may be a random number. When generating random numbers, for example, the A/D converter 30
It is possible to use the contents of the lower few bits of the data from when the write address starts. However, in that case, it is necessary to convert so that the above-mentioned conditions are satisfied.

In this way, the read address is increased at a constant speed, the write address is increased intermittently in relation to the read address, and the start and stop of writing is controlled from the negative input audio signal, for example, as shown in Figure 3. By performing this at the positive zero crossing point, there will be no waveform discontinuity or large slope change at the joint between segments, no click noise will occur, and the S/N ratio will be very good.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of the pitch converter of the present invention, and FIGS. 2 to 6 are diagrams for explaining the same. 10...Random access memory, 70W is a write address counter, 70R is a read address counter, 80 is a multiplexer, and 110 is a start/stop control circuit.

Claims (1)

[Scope of Claims] 1. An audio pitch converter which A/D converts an audio signal and applies it to the input of a random access memory, and outputs the output signal of the random access memory by D/A converting the audio signal, which Read address generation means for increasing the read address of the access memory at a constant speed V; write address generation means for generating the write address of the random access memory; and control for start-stop control of the write address generation means. and a zero-cross detection means for detecting a zero-cross of a signal input to the random access memory, and the control means detects a zero-cross of the signal by the zero-cross detection means after the difference between the write address and the read address becomes within a certain range. Start the write address from the time it is detected and write at a constant speed N・V
(However, N>1), and after increasing by more than a certain level after the start, the audio pitch converter stops increasing the write address when the zero-crossing of the signal is detected by the zero-crossing detection means.