JPH0123967B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a pulse width modulation (PWM) device used for outputting error signals of digital servo systems.

Conventional configuration and its problems In order to feed back the error information detected by the digital servo system to the servo motor drive circuit, it is necessary to first convert it into an analog quantity. Particularly in digital-to-analog conversion (hereinafter referred to as DA conversion) used in servo systems, it is desirable that the relationship between input and output be a linear relationship, and it is necessary to ensure at least unitary increase. In addition, in order to improve the accuracy of the system, it is necessary to reduce the quantization error.
Error information involves handling a large number of bits.

As a system that satisfies the above-mentioned conditions with a simple configuration, the PWM system, which is configured with a reference clock and a counter, is optimal. However, since the PWM method changes the ratio of "H" and "L" for a predetermined period, unless the output is averaged,
Analog quantities cannot be obtained. For this reason, D
-The A conversion time requires at least one cycle of the PWM wave, and is further delayed by the phase shift caused by the low-frequency wave generator for averaging. This means that the feedback of error information is delayed in time, which is a big problem for servo systems.

One way to improve this problem is to shorten the period of the PWM wave and increase the cut-off frequency of the low-band generator. However, shortening the PWM period means increasing the frequency of the reference clock, which is limited by the maximum operating frequency of the counter. Also, if you try to shorten the period of the PWM wave without changing the frequency of the reference clock, the number of counts for one period will decrease. This increases the quantization error, so
There were various problems that were considered undesirable.

Purpose of the Invention The purpose of the present invention is to improve the periodicity of the PWM wave and solve the above-mentioned problems without changing the frequency of the reference clock or the resolution of DA conversion (the number of bits of digital signal input). It is something.

Structure of the Invention A PWM counter that counts a reference clock and performs pulse width modulation according to a predetermined upper bit of a digital signal input, and a PWM counter that counts the reference clock and calculates the period of the pulse width modulated wave that is the output of the PWM counter a time reference generator that generates an output reference signal for determining the reference clock; and a time reference generator that decodes the count output of the time reference generator to have the same period as the output reference signal and a time width that is the same as the period of the reference clock. a counter for counting the output reference signal of the time reference generator or the pulse signal of the pulse generator; a counter for counting the count value of the counter and the remaining lower bits of the digital signal input; a pattern generator that generates a pattern signal of "H" or "L" according to the pattern signal; and a pulse output of the pulse generator and a pulse width modulated wave of the PWM counter are added or combined according to the pattern signal of the pattern generator. PWM with subtracting 1-bit modulator
By dividing the PWM wave as evenly as possible in time, the periodicity of the PWM wave can be increased without increasing the frequency of the reference clock.

DESCRIPTION OF EMBODIMENTS FIG. 1 shows a configuration diagram of a PWM device in an embodiment of the present invention. In Figure 1, 1 is a time reference generator, 2 is a pulse generator, and 3 is a PWM
counter, 4 is a counter, 5 is a pattern generator,
6 is a 1-bit modulator. The time reference generator 1 receives a reference clock as an input, and is composed of a binary counter consisting of m T-type flip-flops (hereinafter referred to as T-FF) corresponding to the upper m bits of a digital signal input. It determines the period of waves. The pulse generator 2 decodes the count output of the time reference generator 1 and generates a pulse whose width is equal to the period of the reference clock and whose period is equal to the period of the PWM wave determined by the time reference generator. The PWM counter 3 is an m-bit binary counter consisting of m presettable TFFs and a specific count value (minimum value in the case of an asynchronous down counter, maximum value in the case of an asynchronous up counter). and an inhibit gate that inhibits the input reference clock based on the output of the detector. Pulse generator 2
The upper m bits of the digital signal input are preset at the timing of the preset pulse ○a output from the preset, and after the preset is completed, the reference clock is counted and the inhibit gate is closed when the counter reaches the minimum or maximum value. to stop the counting operation. Then, upon receiving the next pulse output ○a, the preset is again performed, and the same operation is repeated thereafter. As a result, a PWM wave having a time width of the count period corresponding to the preset value is outputted from the inhibit gate. The counter 4 receives as input a periodic pulse ○ which determines the period of the PWM wave output from the time reference generator 1, and is composed of a binary counter consisting of n TFFs corresponding to the lower n bits of the digital signal input. The period of the PWM wave is counted by repeating it 2 ⁿ times. The pattern generator 5 is composed of a gate circuit that receives the count value of the counter 4 and the data of the lower n bits of the digital signal input, and the period of one modulation pattern ○E which outputs the modulation pattern ○E is as follows. PWM
The period is set to be the same as that of wave ○a. This modulation pattern ○E has one period of ²ⁿ times (same as the ²ⁿ period of PWM wave ○A), and the number of “H” or “L” patterns corresponds to the data of the lower n bits of the digital signal input. It matches the value (0 to 2 ⁿ -1). Furthermore, consideration is given to outputting "H" or "L" patterns at as even intervals as possible with a cycle of 2 ⁿ times. The 1-bit modulator 6 performs 1-bit modulation using the preset pulse ○a as a time width reference, the modulation pattern ○e as a modulation signal, and the PWM wave ○a as a modulated signal. In other words, the 1-bit modulator 6 outputs the modulation pattern ○A only when outputting the preset pulse ○A (a pulse with a time width equivalent to one cycle of the reference clock and whose rise or fall timing is aligned with the reference clock). Depending on the information, the PWM wave is forcibly fixed at "H" or "L" to output the final PWM wave. Note that one period of the reference clock corresponds to one bit of data of the digital signal input. In other words, since the modulation pattern ○E is repeated ²ⁿ times in terms of the period of the PWM wave, the total period is ²ⁿ periods in terms of the period of the PWM wave ○I. One period is 2 ^m periods in terms of the standard clock period, so when expressed in terms of the standard clock period, the total period is 2 ^n+m periods, of which the output of the 1-bit modulator 6 is “H”. The number of times (converted to the reference clock cycle) matches the number of data of the digital signal input. Therefore, 1
Modulating the bit modulator 6 only during the period in which the preset pulse A is outputted corresponds to modulating the information amount of one bit.

FIG. 2 shows a specific circuit of the pattern generator (5 in FIG. 1) in an embodiment of the present invention.
The case where n=3 will be explained below. FIG. 3 shows a timing chart of the same specific circuit. In Fig. 2, counter 4 is for each T-FF
The output signals from the previous stage are expressed as Q ₀ , Q ₁ , and Q ₂ . In addition, digital signal input also starts from the lower bit.
They are expressed as D ₀ , D ₁ , D ₂ , ..., D _n , D _n+1 , D _n+2 . AND7 is 1 in 8 times, AND8 is 1 in 4 times.
times, AND9 is D ₀ , D ₁ , D ₂ evenly once every two times, and without overlapping in time, respectively.
is outputting. The outputs of these AND7, 8, and 9 are combined by OR10 to form the modulation pattern ○E for the modulation signal.

When the pattern generation method is generally described using an equation, it can be expressed as the following equation.

(Pattern) = D ₀・₀・₁・……・_o-2・Q _o-1 +D ₁・₀・₁・……・_o-3・Q _o-2 +…… +D _o-2・₀・Q ₁ +D _o-1・Q ₀ (1) Another method to output pattern ○E as evenly as possible according to the digital signal input is as follows.
The following formula can be given.

(Pattern) = D ₀・Q ₀・Q ₁・……・Q _o-2・_o-1 +D ₁・Q ₀・Q ₁・……・Q _o-3・_o-2 +…… +D _{o- 2}・Q ₀・₁ +D _o-1・₀ (2) However, if counter 4 is configured with an asynchronous down counter, it is possible to use the method of equation (2) or use an asynchronous up counter. When configured, using the method of formula (1), T-FF
Care must be taken because hasards occur due to the propagation delay. However, unless a hasard occurs during the period in which the preset pulse ○a is being output, there is no problem in practice. FIG. 3 shows the timing of each signal when the time reference generator 1 and the counter 4 are both configured as asynchronous down counters and the method of equation (1) is used. In this example, the preset pulse A is obtained by detecting the time when all T-FFs of the time reference generator 1 are at "L". Further, the periodic pulse ○u which becomes the clock input of the counter 4 is obtained from the T-FF output of the final stage of the time reference generator 1.
In this case, the propagation delay from the falling edge of preset pulse ○A to the rising edge of _Q0 is m・τ(m
is the number of T-FF stages, and τ is the propagation delay per T-FF stage). Modulation pattern ○E is after Q ₀ changes,
Output. Therefore, after the preset pulse falls, there is a delay of m·τ due to the propagation delay, and the modulation pattern ○E is output, so the modulation pattern ○E is completely completed by the next preset pulse ○A. The state can be stabilized, and the state does not change while the preset pulse ○a is being output.

FIG. 4 shows a specific circuit of the 1-bit modulation circuit (6 in FIG. 1) in the embodiment, and FIG. 5 shows a timing chart of the specific circuit. When the output of pulse generator 2 is “L”
Since the output of AND12 is “L” and the output of NAND15 is “H”, the PWM wave ○I is OR13, AND
16 together, AND14, AND17,
Although one of the outputs is fixed to “L”, the other gate is open, and the PWM wave ○I is OR18.
is input and output as is. Next, when the preset pulse ○a is "H", its operation changes depending on the modulation pattern ○e. In other words, when modulation pattern ○E is "H", the output of AND14 becomes "L" and has no effect, and
Since the output of NAND15 becomes “L”, PWM
AND16 output is “L” regardless of the state of wave ○a
is fixed to , and it passes through OR18 as it is. In other words, when modulation pattern ○e is “L”
This means that the PWM wave A is modulated (deleted) to the negative side for a period corresponding to 1 bit at the preset timing. Conversely, when modulation pattern ○E is "L", AND17 has no effect and the output of AND12 becomes "H", so the output of OR13 becomes "H" regardless of the state of PWM wave ○A. ”, and it is OR18 as it is.
passes. In other words, the modulation pattern ○e is “H”
When , it means that the PWM wave A is modulated (added) to the positive side for a period corresponding to 1 bit at the preset timing.

In Fig. 5, the timing relationship between each input of the 1-bit modulator 6, NAND 15 for deleting 1 bit, AND 12 for adding 1 bit, and the PWM wave output after modulation (output signal of the 1-bit modulator) is digitalized. Signal input lower 3 bits are (011)
This is shown using an example. Here, since modulation pattern ○E changes in response to the falling edge of preset pulse ○A, modulation pattern ○E is completely stable during the period when preset pulse ○A is "H", and AND12, NAND15 The pulse width of the preset pulse A is always equal to the pulse width of the preset pulse A (that is, equal to the period of the reference clock corresponding to one bit), and there is no variation. By the way, the preset pulse ○a also serves as the preset signal for the PWM counter 3, so the preset pulse
At the rising edge of pulse ○a, PWM counter 3 is preset, and PWM wave ○a rises. Therefore, from the rise of preset pulse ○a,
There is some time delay before the PWM wave ○i rises. Furthermore, PWM counter 3
If there is variation in the delay time required for presetting each T-FF, the delay in the rise of PWM wave A will vary depending on the digital input signal serving as preset data, which is undesirable. However, the 1-bit modulator 6 not only deletes 1 bit, but also adds it, and the timing is almost equal to the preset pulse ○a (approximately 1 stage in terms of gate).
In practice, the delay time required for FF presetting and its dispersion can be completely corrected.
This can be said to be an extremely important advantage in improving the precision of DA conversion.

As described above, according to this embodiment, all the timings are matched by counting the reference clock, and the output signal of the pulse generator also serves as the preset signal of the PWM counter, thereby achieving the object of the present invention. Even if a counter with a simple configuration such as an asynchronous type is used, it is possible to obtain a PWM wave in which propagation delay does not become an error factor in practical use.

In the embodiment, the time reference generator 1 and the counter 4 are mainly constructed using an asynchronous down counter, but it is possible to use an asynchronous up counter or other counters. Needless to say.

Effects of the Invention The PWM device of the present invention has a PWM counter that receives predetermined upper bits of a digital signal input, a time reference generator that determines the period of the PWM counter, and a period equal to the period of the PWM counter, a pulse generator having a pulse width corresponding to one bit of the digital signal input; a counter for counting the period of the PWM counter; By providing a pattern generator that generates a modulation pattern and a 1-bit modulator that adds or subtracts the pulse output of the pulse generator and the pulse width modulated wave of the PWM counter based on the pattern signal output from the pattern generator. , reference clock frequency and D-A
Simple configuration without changing conversion resolution
The practical effect is great because the periodicity of the PWM wave can be increased and the time required for averaging the PWM wave can be shortened.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of a PWM device in an embodiment of the present invention, Fig. 2 is a specific circuit diagram of a pattern generator in the same embodiment, Fig. 3 is an operation waveform diagram of the specific circuit in Fig. 2, and Fig. 4 5 is a specific circuit diagram of the 1-bit modulator in the embodiment, and FIG. 5 is an operating waveform diagram of the specific circuit of FIG. 4. 1...Time reference generator, 2...Pulse generator,
3...PWM counter, 4...Counter, 5...
Pattern generator, 6...1 bit modulator.

Claims (1)

[Claims] 1. A PWM counter that counts a reference clock and performs pulse width modulation according to a predetermined upper bit of a digital signal input, and a PWM counter that counts the reference clock to determine the period of the pulse width modulated wave that is the output of the PWM counter. a time reference generator that generates an output reference signal; and a pulse that is obtained by decoding the count output of the time reference generator and has the same period as the output reference signal and has the same time width as the period of the reference clock. a counter for counting the output reference signal of the time reference generator or the pulse signal of the pulse generator; and a counter for counting the output reference signal of the time reference generator or the pulse signal of the pulse generator; a pattern generator that generates a pattern signal of "H" or "L"; and 1 that adds or subtracts the pulse output of the pulse generator and the pulse width modulated wave of the PWM counter according to the pattern signal of the pattern generator. a bit modulator;
A pulse width modulator characterized in that a pulse width modulated wave is obtained from a bit modulator.