JPH0125227B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor circuit device in which a plurality of semiconductor circuit elements such as memories are arranged on a substrate and are electrically connected to each other.

FIG. 1 is a diagram showing connection terminals of a semiconductor integrated circuit element, in which 1 is a semiconductor integrated circuit main body (hereinafter referred to as "IC"), and 2 and 3 are its input/output pins.
The capacitance of these input/output pins differs depending on the position where the pin is arranged. For example, the capacitance C ₁ of front pin 2 is small, and the capacitance C ₂ of pin 3 is large.

Conventionally, IC1 having input/output pins as described above
A plurality of ICs are mounted on the hybrid board 4 as shown in FIG.
are commonly connected to constitute common input/output pins 5 and 6 of the hybrid IC circuit.

In such a hybrid circuit, the IC1
If the number of is N, then the internal capacitance seen from pin 5 is N times the capacitance of pin 2, and similarly the internal capacitance seen from pin 6 is N times the capacitance of pin 3. It will be doubled. However, pin 5 and pin 6
The difference in capacitance is N times the difference in capacitance between pins 2 and 3 of internal IC1. Generally, in the operation of an electric circuit element, a large difference in capacitance between the pins of the element causes an increase or decrease in operation speed, resulting in an inconvenient problem. However, in the conventional technology of hybrid circuits, it is used despite the above-mentioned performance problems due to the advantages of regular wiring patterns and ease of design.
This problem becomes particularly important in hybrid circuits of high-speed memory elements.

An object of the present invention is to provide a semiconductor circuit device that solves the above problems.

The present invention will be explained in detail below with reference to Examples.

In FIGS. 3 and 4, parts having the same functions as those in FIG. 2 are given the same symbols.

FIG. 3 is a circuit configuration diagram of an embodiment of the present invention, in which a plurality of ICs 1 are arranged on a substrate (or a board) 4, and pins 2 of IC 1 have a small capacitance and pins 2 have a large capacitance. The input/output pins 5 and 6 of the hybrid board 4 are configured by alternately connecting the pins 3 and 3 of the hybrid board 4. Pin 2 with a small capacitance and pin 3 with a large capacitance of IC1 are known in advance from the design pattern of IC1 and the configuration of each layer, so pins 5 and 6 on the hybrid board 4
internal IC1 so that the difference in capacitance between
It is easy to select and connect each pin. Further, the number of internal IC1s and the number of pins may be an even number or an odd number. In this way, when the capacitance of each input/output pin of internal IC1 is known in advance,
When connecting pins 2 and 3 in common, pin 2 with a small capacitance and pin 3 with a large capacitance of each IC 1 are connected on the board 4 so that the variation in total capacitance after connection is minimized. By selecting this, it is possible to reduce variations in capacitance between the input/output pins 5 and 6 of the hybrid board 4.

FIG. 4 is a configuration diagram of another embodiment of the present invention,
In order to correct variations in capacitance between input/output pins 5 and 6 in the embodiment shown in FIG. This makes it possible to more accurately equalize input and output capacitance.

Although the present invention is applied to a hybrid circuit in this embodiment, it goes without saying that the present invention can also be applied to other devices in which a plurality of semiconductor circuit elements are arranged on a substrate such as a board.

As explained above, according to the present invention, the difference in input and output capacitance between input and output pins can be reduced even in a semiconductor device in which a plurality of semiconductor circuit elements are arranged on a substrate and electrically connected. As a result, it is possible to make the film substantially uniform, thereby improving characteristics and design margins. Therefore, high performance can also be provided in hybrid IC circuits for high-speed memory elements.

[Brief explanation of drawings]

Fig. 1 is a diagram showing connection terminals of a semiconductor integrated circuit element, Fig. 2 is a connection diagram of a conventional hybrid IC 1 circuit, Fig. 3 is a circuit connection diagram of an embodiment of the present invention, and Fig. 4 is a diagram of the present invention. FIG. 3 is a circuit connection diagram of another embodiment. 1... Semiconductor integrated circuit element, 2, 3... Input/output pin, 4... Hybrid board, 5, 6... Common input/output pin, 7... Correction capacitance.

Claims (1)

[Claims] 1. A first semiconductor integrated circuit having a first terminal having a relatively large capacitance and a second terminal having a relatively small capacitance; a second semiconductor integrated circuit having a terminal and a second terminal having a relatively small capacitance, and first and second common wiring, the first terminal of the first semiconductor integrated circuit and the second semiconductor integrated circuit A second terminal of the circuit is coupled to the first common wiring, and a second terminal of the first semiconductor integrated circuit and a first terminal of the second semiconductor integrated circuit are coupled to the second common wiring. Characteristic semiconductor circuit device. 2. The semiconductor circuit device according to claim 1, wherein the first and second semiconductor integrated circuits constitute a memory having terminals arranged to correspond to each other. 3. The semiconductor circuit device according to claim 1 or 2, wherein the first and second terminals each constitute an input/output terminal. 4 comprising a plurality of common wirings and a plurality of semiconductor integrated circuits each having a plurality of terminals to be coupled to the common wirings, the capacitance of each of the terminals being uneven, and at least one of the plurality of common wirings. First, the semiconductor circuit device according to claim 1, wherein a correction capacitance is added to reduce the difference in capacitance between the common wirings. .