JPH0125293B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase discrimination circuit that is installed in a protective relay of a power system and determines the phase relationship between two input AC signals.

Conventionally, there has been a phase discrimination circuit of this type as shown in FIG. In Figure 1, V ₁ and V ₂ are signals that are AC voltages detected from two points on a transmission line of a power system (not shown), and 1 is a signal that inputs signals V ₁ and V ₂ and compares their phases. A division detection circuit 2 outputs a signal V ₁₀ as a discrimination signal when the polarities are the same, inputs the signal V ₁₀ , has an operating time T ₁ and a return time 0, and the signal V ₁₀ is an operating time. A time limit circuit that outputs the signal V _T1 when T ₁ or more continues, 3 is the signal
Inverter 4 that inverts V _T1 inputs signal _T1 output from inverter 3, has operating time T ₂ and recovery time 0, and outputs signal V ₀ when signal _T1 continues for more than operating time T ₂ . It is a timed circuit.

FIG. 2 is a waveform diagram of the operation of the phase discrimination circuit shown in FIG. 1. The operation will be explained with reference to FIG.
In order to simplify the explanation, the explanation will be made on the assumption that the phase difference θ between the signals V ₁ and V ₂ suddenly switches from 45° to 135° at time t ₀ . Signal V ₁ ,
V ₂ consists of a 50 Hz sine wave as shown in Figure 2a, and the former has a phase difference θ (45° until time t ₀ ,
After time t ₀ , the wave has advanced by 135°), and is half-wave rectified for the positive period and negative period in the discrimination detection circuit 1, then converted into a rectangular wave, further logically ANDed, and finally synthesized. A signal _V10 having a waveform as shown in FIG. 2b is output. signal
Therefore, V ₁₀ is output as high during a period in which the signals V ₁ and V ₂ both have the same polarity. In the time limit circuit 2, in a period in which the phase difference θ between the signals V ₁ and V ₂ is θ=45°<90, the signal V ₁₀ continues for more than the operating time limit T ₁ (for example, 5 ms), ₀ signal as shown previously
Output V _T1 . However, in the period when the phase difference θ after time t ₀ is θ = 135° > 90° (the right side of Figure 2), the signal
Does not output V _T1 . When such a signal V _T1 is inverted by the inverter 3 and input to the time limit circuit 4, the time limit circuit 4 changes the operating time T ₂ (with some margin) from the time t ₀ when the phase difference θ=135°. The signal V ₀ is output at time t ₁ after a period of 12 ms (for example, 12 ms) has elapsed.
In other words, the signal V ₀ has a phase difference θ between the signals V ₁ and V ₂ .
There is no output when the angle is 45°, there is output when the angle is 135°,
The limit for both is 90°.

By the way, if distortion occurs in the signals V ₁ and V ₂ ,
The signal V ₁₀ output from the discrimination detection circuit 1 does not have a pulse width corresponding to the phase difference θ between the signals V ₁ and V ₂ due to distortion, and the waveform shown in FIG. 2b cannot be obtained. .

FIG. 3 is a diagram showing a waveform in which a noise pulse is superimposed on the signal V ₁ in this way, causing distortion. Third
The waveforms shown in Figures a, b, c, and d correspond to the waveforms shown in Figures a, b, c, and d, respectively. Because the noise pulse was superimposed on the signal V ₁ ,
The signal V ₁₀ becomes a pulse with a crack,
Since the time limit _T1 is not continuous, the signal V _T1
is not output. Therefore, the timer circuit 4
It is no longer suppressed by V _T1 and outputs a signal V ₀ at time t ₀₁ . That is, the phase discrimination circuit distinguishes between the signals V ₁ and V ₂ due to the noise pulse being superimposed on the signal V ₁ .
This means that the phase difference θ=45° between them was incorrectly determined, and the signal V ₀ was output.

Since the conventional phase discrimination circuit has the above-described configuration, it has the disadvantage that it easily malfunctions when distortion occurs in the input signal due to noise pulses.

This invention was made in order to eliminate the drawbacks of the conventional circuits as described above, and provides a phase discrimination circuit that does not easily malfunction even when noise pulses are superimposed on an AC signal to be phase discriminated, causing distortion. The purpose is to provide.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram showing the configuration of the present invention, and parts having the same reference numerals as those in FIG. 1 indicate the same parts. 5 is an inverter that inverts the signal V ₁₀ and outputs the signal ₁₀ ; 6 is an inverter that inputs the signal ₁₀ , has an operation time t (= 2 ms) and a recovery time 0;
_7-1 and 7-2 are _a time limit circuit that outputs V _t
8-1 and 8-2 are diodes connected in series between the output terminals of the switch circuits 7-1 and 7-2, and 9 is a connection point between the diodes 8-1 and 8-2 and the ground. connected, switch circuit 7-
A capacitor constitutes an integrating circuit together with the collector resistor R _T of 1, and a signal of the voltage of capacitor 9 is 10.
11 is an _inverter that inverts the signal V _T1B of the level detection circuit 10, and outputs it to the _timer circuit ₄ . supply.

Next, with reference to the waveform diagram shown in _FIG .
The operation when no noise pulse is superimposed on V ₂ will be explained. In addition, to simplify the explanation, the time
At t ₃ , the phase difference θ between signals V ₁ and V ₂ changes from 45°.
The explanation will be given assuming that the angle changes suddenly to 135°. signal
V ₁ and V ₂ are determined by the discrimination detection circuit 1 to determine the phase difference θ between the sine wave shown in FIG. 5a and the sine wave shown in FIG. 5b.
It is converted into a signal V ₁₀ having a pulse width corresponding to , and becomes a signal ₁₀ which is inverted by an inverter 5. When signal ₁₀ goes high, switch circuit 7-
1 transistor T is turned on, and the following signal ₁₀
Accordingly, the transistor T is repeatedly turned on and off as shown in FIG. 5c.

Since the signal ₁₀ is also input to the time limit circuit 6, if this continues for 2 ms or more, the operation time t = 2 ms
The timer circuit 6 generates a signal V _t 〓 as shown in FIG. 5d.
Output. Further, the signal V _t 〓 of the time limit circuit 6 is input to the transistor T of the switch circuit 7-2, and during the period when this signal is high, this transistor T is
It turns on as shown in , and turns off at other times.

When the transistor T of the switch circuit 7-1 is turned off, its collector resistance R _T and diode 8
The current passing through -1 charges capacitor 9,
The signal V _CT is connected to the collector resistor R _T as shown in Figure 5f.
starts to rise with a time constant determined by capacitor 9,
It exceeds the level V _L in a time period T ₁ (=5ms) and continues to rise until the signal V _t 〓 changes to high.

When the signal V _t 〓 becomes high, the switch circuit 7-2
The transistor T is turned on, and the capacitor 9 is grounded through the diode 8-2 and the transistor T, so that it is discharged and the signal V _CT becomes low.

The level detection circuit 10 makes the signal V _T1B high as shown in FIG. 5g during a period in which the signal V _CT exceeds the level V _L. As shown in the figure, the pulse of the signal V _T1B is generated only during a period when the phase difference θ between the signals V ₁ and V ₂ is 45°, and is inverted by the inverter 11 and sent to the timer circuit 4.
is input. Therefore, during the period when the phase difference θ=45° during which the signal V _T1B is output as a pulse, the time limit circuit 4 cannot output the signal V ₀ due to its operation time limit _T2 , and the phase difference θ=135°. Then, after the operation time _T2 , the signal _V0 is output as shown in FIG. 5h.

In this way, the phase discrimination circuit does not output the signal V 0 during the period when the phase difference θ between the signals V ₁ and V ₂ is 45°, but outputs the signal V ₀ during the period when the phase difference θ _is 135°. , the logic level of the signal V ₀ corresponds to the result of discriminating the phase difference θ.

Next, the operation when a noise pulse is superimposed on the signal _V1 will be explained with reference to FIG. The waveforms a to h in FIG. 6 are shown corresponding to the waveforms a to h in FIG. 5. As shown in FIG. 6a, noise pulses are superimposed on the signal V ₁ at times t ₃ , t ₆ and t ₉ , so that cracks appear in the signal V ₁₀ (FIG. 6b) at that time. However, the operation time limit t of the time limit circuit 6
is 2 ms, which is longer than the width of the noise pulse, so that the timer circuit 6 does not output the signal V _t at times t ₃ , t ₆ and t ₉ (FIG. 6d). Therefore, the capacitor 9 outputs a signal V _CT with a waveform similar to that in FIG. 5 f without being affected by the noise _pulse , as shown in _FIG . It will be similar to the one in Figure 5.

In other words, the phase discrimination circuit does not malfunction even when a noise pulse is superimposed on _the signal V ₁ ,
Correctly discriminate between V ₂ .

Note that even when the noise pulse is superimposed on the signal V ₂ , the same effect as described above will occur. Further, as shown in FIG. 7, the inverter 5 to level detection circuit 10
It is also possible to introduce the output of a time width measuring circuit 12 consisting of the following, and provide a time limit circuit 13 with an operation time limit of 0 and a return time limit _T2 , and the same effect as in the above embodiment can be obtained.

As described above, according to the present invention, even if noise pulses or the like are superimposed on the AC signal whose phase difference is to be determined and distortion occurs, it is possible to immediately prevent malfunctions and improve reliability. This has the effect of providing high phase discrimination.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional phase discrimination circuit, FIGS. 2 and 3 are waveform diagrams explaining the operation of the phase discrimination circuit shown in FIG. 1, and FIG. 4 is a phase discrimination circuit according to an embodiment of the present invention. 5 and 6 are waveform diagrams illustrating the operation of the phase discrimination circuit shown in FIG. 4, and FIG. 7 is a block diagram of a phase discrimination circuit according to another embodiment of the present invention. 1... Division detection circuit, 2, 4, 6, 13... Time limit circuit, 3, 5, 11... Inverter, 7-1,
7-2... Switch circuit, 8-1, 8-2... Diode, 10... Level detection circuit. In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Claims] 1 Input two AC signals to be phase-discriminated, and process these AC signals including rectification, waveform conversion, and comparison to make the logic levels different during periods when the AC signals have the same polarity and different polarity. a division detection circuit that generates a division signal;
The first signal is off during the period in which the division signals have the same polarity.
a switch circuit, and a first timer circuit having a first operation time period longer than the width of the noise pulse superimposed on the alternating current signal and starting a timed operation during a period in which the introduced classification signal exhibits a different polarity. , a second switch circuit that is turned on by a signal from the time limit circuit; and a second switch circuit that is charged with a predetermined time constant through a first diode when the first switch circuit is off, and is charged with a predetermined time constant when the second switch circuit is on. A capacitor that discharges instantaneously through a diode No. 2 and a detection level set corresponding to a predetermined phase difference of the AC signal, and when the voltage of the introduced capacitor becomes equal to or higher than the detection level. comprising a level detection circuit that outputs a signal, and a second time limit circuit having a predetermined second operation time limit set corresponding to the phase difference and into which the signal of the level detection circuit is introduced;
A phase discrimination circuit whose output signal is the signal of this second time limit circuit.