JPH0127425B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor display device, and more specifically, in order to selectively drive a large number of liquid crystal display elements arranged in a matrix, a charge storage capacitor and a charge control gate are connected to a liquid crystal display device. The present invention relates to a semiconductor display device arranged in a matrix pattern corresponding to display elements.

When displaying characters, figures, etc. using a liquid crystal panel, a semiconductor display is used in which fine liquid crystal display elements are arranged in a matrix and a display control element is provided below the liquid crystal surface in correspondence with each liquid crystal display element. equipment is used. Driving this type of semiconductor display device is
It has a first electrode drive line provided in large numbers in the X direction and a large number of second electrode drive lines provided in the Y direction, and the first electrode and second electrode drive lines correspond to the display element to be driven. By applying a predetermined voltage to the line, a display control element (for example, a MOS transistor) placed at the intersection of both drive lines is driven,
The display element is controlled to be turned on and off.

Since the semiconductor display device has a large scale as an IC, it is difficult to check each display element using these drive lines.In particular, it is difficult to sufficiently detect short circuits and disconnections between drive lines in each direction. The problem is that it cannot be carried out on a regular basis. Therefore, in the end, it was not possible to check for defects in the wiring unless the liquid crystal was placed and assembled.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor display device in which mutual short circuits and disconnection faults in each drive line can be easily checked at the wafer stage.

The features of the configuration of the present invention for achieving the above object include a large number of first electrode drive lines, and a large number of first electrode drive lines arranged to intersect with the first electrode drive lines while maintaining electrical insulation. A two-electrode drive line is provided corresponding to each intersection of the first electrode drive line and the second electrode drive line, and is responsive to a potential difference applied to the first electrode drive line and the second electrode drive line. In the semiconductor display device, the first electrode drive line and the second electrode drive line are connected to the second electrode drive line. The first test wiring arranged in the first layer and connected to all the first electrode drive lines and the second test wiring connected to all the second electrode drive lines are arranged in the second layer. The reason is that it has a multi-wiring structure.

The connection between these test wires and the first electrode or second electrode drive line can be disconnected after a predetermined test is completed, allowing normal use.

Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

The drawing shows an electrode wiring pattern of a semiconductor display device according to the present invention. This semiconductor display device 1 has gate electrode _drive lines X ₁ , _{X 2} , Source electrode drive lines Y ₁ , which are arranged in parallel with
Y ₂ , ..., _Yo , and MOS transistors T ₁₁ , T ₁₂ , T ₁₃ , ... for driving liquid crystal display elements (not shown) are provided corresponding to the intersection points of these drive lines.
...T _1o , T ₂₁ , T ₂₂ , T ₂₃ , ...T _2o , ...T _o1 ,
T _o2 , ...T _oo are formed on a semiconductor substrate (not shown), and the gates and sources of these transistors are connected to corresponding gate electrode drive lines and source electrode drive lines, respectively, as shown in the figure. At the same time, each drain is grounded via a storage capacitor C provided corresponding to each transistor.

The source electrode drive lines Y ₁ to _{Y o} are formed as first layer aluminum wiring on the semiconductor substrate, while the gate electrode drive lines X ₁ to _{X o} are similarly formed as first layer polysilicon wiring. has been done. The source electrode drive lines Y ₁ to _{Y o} each have pads.
A ₁ to A _o are provided, and each end of the drive lines Y ₁ to _{Y o} is connected to an external terminal. Similarly, the gate electrode drive lines X ₁ to _{X o} have pads B ₁ to B _o , respectively, and each end is connected to an external terminal.

Therefore, by selectively applying a predetermined potential to the drive lines X ₁ to X _o and Y ₁ to _{Y o} , a desired value can be obtained.
The MOS transistors can be selectively driven, and thereby the liquid crystal elements provided corresponding to each transistor can be selectively driven and controlled to display desired characters and figures.

The semiconductor display device 1 configured as described above is inspected for disconnection of each drive line, short circuit between the gate electrode drive lines X ₁ to X _o and the source electrode drive lines Y ₁ to _{Y o} , shorting of the capacitor, etc. The first test wiring 2 and the second test wiring ₃ are connected to the drive line
~X _o and Y ₁ ~ _{Y o} are provided in a second layer wiring area different from the first layer where they are arranged.

The first inspection wiring 2 includes gate electrode drive lines X ₁ to
The other end of X _o is connected to each drive line X ₁ to _{X o} , and corresponds to pads C ₁ to C _o provided corresponding to pads B ₁ to B _o , and pads A ₁ to A _o . They are respectively connected to pads D ₁ to _{D o} provided as follows.
Note that the pads C ₁ to _{C o} correspond to each gate electrode drive line X ₁ to X _o
The pads D ₁ -D _o are not connected to the respective source electrode drive lines Y ₁ -Y _o .

The second inspection wiring 3 includes source electrode drive lines Y ₁ to
The other end of Y _o is connected to each drive line Y ₁ to _{Y o} , and is also connected to pads E ₁ to _{E o} provided corresponding to pads A ₁ to A _o , respectively.

Also in this case, the pads E ₁ -E _o are electrically insulated from the source electrode drive lines Y ₁ -Y _o .

Next, a procedure and method for testing the semiconductor display device 1 using the first and second testing wirings 2 and 3 provided in this manner will be described.

First, by checking continuity between pads B ₁ and C ₁ , B ₂ and C ₂ , and so on, the gate electrode drive line is
It is possible to check for disconnections in X ₁ , X ₂ , ...X _o . This is because the first inspection wiring 2 is commonly connected to the other ends of the gate electrode drive lines X ₁ to X _o .

Similarly, between pads A ₁ and E ₁ , between A ₂ and E ₂ ,...
By checking the conductivity of..., it is possible to check for disconnections in the source electrode drive lines _Y1 to _Yo .

Next, by checking continuity between the first test wiring 2 and the second test wiring 3, it is determined whether there is a short circuit between any gate electrode drive line and any source electrode drive line. You can check whether it is true or not. If it is found that there is a short circuit, in order to release the common connection between the second inspection wiring 3 and the source electrode drive lines Y ₁ to Y _o , connect the wiring 3 and each drive line Y ₁ to Y o. Connection and wiring between Y _o and
The interconnection between each drive line Y ₁ -Y _o is cut off, and the wiring 3 and each source electrode drive line Y ₁ -Y _o are electrically insulated from each other, and then the pad A By checking the conduction state between ₁ and _D1 , between _A2 and _D2 , and so on, it is possible to know which source electrode drive line is short-circuited with any gate electrode drive line.

Next, in order to check whether there is a short circuit between each source electrode drive line Y ₁ -Y _o and the substrate, all the transistors are The gate potential of T ₁₁ to _Too is maintained at a potential that turns off the transistor, and in this state, continuity between each pad A ₁ to A _o and the ground wiring 4 is checked. This makes it possible to know whether there is a short circuit between each of the source electrode drive lines Y ₁ to _Yo and the ground.

Next, by checking continuity between the first inspection wiring 2 and the ground wiring 4, it is possible to check whether there is a short circuit between any of the gate electrode drive lines and the ground wiring. .

Finally, a potential that turns on each transistor is applied to the first inspection wiring 2 to turn on all the transistors. In this state, the connection between each source electrode drive line Y ₁ to _Yo and the ground wiring 4 is By checking the conduction state between the two, it is possible to identify the source electrode drive line in which the capacitor C is short-circuited.

In addition, the first inspection wiring 2 and each gate electrode drive line
The connections with X ₁ to _{X o} may be disconnected after the above-mentioned test is completed.

According to the present invention, as described above, by using a two-layer wiring structure and adding two inspection wirings, it is possible to efficiently inspect each electrode drive line for failures such as disconnections and short circuits, and in practice Before disposing display elements and assembling a semiconductor display device, serious screen defects can be identified at the wafer stage, which has the advantage of simplifying inspection.

[Brief explanation of drawings]

The drawing is a plan view showing the wiring pattern of the semiconductor display device of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor display device, 2...First inspection wiring, 3...Second inspection wiring, 4...Ground wiring, X1 _{-Xo ...} Gate electrode drive line, _Y1 - _Yo ...
Gate electrode drive line, C...capacitor, T ₁₁ ~
_Too ...MOS transistor, _A1 ~ _Ao , _B1 ~ _Bo ,
C ₁ ~C _o , D ₁ ~D _o , E ₁ ~ _{E o} ...Put.

Claims (1)

[Claims] 1. A large number of first electrode drive lines connected to the first electrodes of a large number of display element driving transistors arranged in a matrix on a semiconductor substrate, and a large number of second electrodes connected to the second electrodes of the transistors. a drive line, and selectively drives a desired display element driving transistor by selectively applying a drive signal to the first and second electrode drive lines; A first inspection wiring in which the first electrode drive line and the second electrode drive line are arranged in a first layer, and which is connected to one end of each of the first electrode drive lines, and the second electrode drive line. and a second test wiring to which all ends of the wires are connected, and the first and second test wiring are arranged in a second layer to form a multi-wiring structure. semiconductor display device.