JPH0127473B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a pattern change point detection circuit that can obtain a contour table in a short time from video data read by an optical character reading device. When reading characters and figures written on paper using an optical character reading device, an electrical signal is obtained by a scanner using a charge-coupled device (abbreviated as CCD), converted into a bit pattern, and stored in memory. do. For example, when one character is written, the range in which that one character is written is divided into multiple elementary areas (dots), and if each elementary area is judged as "black", "1" is displayed. , and if it is determined to be "white", it is binarized to "0" and stored in the memory. Then read the information stored in memory,
By identifying the boundaries between “1” and “0” in the vertical and horizontal directions, pattern detection is performed to decipher characters.
I recognize that the information resulting from the boundary judgment for all of the binarized "1"/"0" mentioned above was memorized regardless of whether the dot position was a boundary point (change point) or not. , the total number of elementary regions divided for one character is on average 40 x 60 dots, which is an excessive amount of information. Therefore, instead of storing all the data resulting from boundary determination in memory, data compression is performed to extract only the information on the detected change point position, and for one character, the left and right information as shown in Figure 1 b2 is compressed. A contour table and upper and lower contour tables as shown in b1 of the same figure are obtained, and original information is reproduced from them. The contour table shows the bit positions where the above-mentioned "1"/"0" changes occur (in Figure 1a, "〇" marks are vertical change points, "X" are horizontal change points,
The marks are used to store addresses (change points in both the vertical and horizontal directions). Figure 1 shows the scan order for detecting change points for the number "2", 15 lines in the Y-axis direction, that is, the address (X, Y), as follows: {(X, 1), X=1 to 12}, { (X, 2), X = 1 ~ 12}, ... {(X, 15), The scan order for detecting the change point for Y) is {(1, Y), Y=1 to 16}, {(2, Y), Y=1 to 16} ... {(11, Y), Y= 1 to 16}, and the “X” mark near the outline indicates the point of change in the left/right (along the X-axis) direction when scanning about the Y-axis, and the “〇”
indicates a change point in the vertical (along the Y-axis) direction when scanning with respect to the X-axis, and the "" mark indicates a case where the change point occurs in both the vertical and horizontal directions. As a conventional technique for obtaining such a contour table, as shown in FIG. ), Y=1 to 15}, and then the bit correspondence between it and the current data with X=n, {(n, Y), Y=1 to 15}, between the matching bits of the Y address, for example, The 15 exclusive OR operation circuits EOR compare each other, and when they match, it outputs "0" and when they do not match, it outputs "1".
Check the EOR output individually and find the position where the output of "1" is obtained as the change point of the pattern ("x" mark in Figure 1 a)
Then, the address at that time is stored as shown in FIG. 1 b2. Alternatively, one EOR circuit may be provided and EOR detection may be performed while shifting the previous data and current data one bit at a time.
In this way, check the EOR detection output of all bits,
This is a result of detecting the position of a change point therein. The results detected in this way are shown in Figure 1 b2, and are marked with an "X" as follows: when Y=1, X is 1, 12; when Y=2, X is 1, 12; when Y=3, X is 2, 5... location is shown. In addition, as shown in FIG. 2B, the detection of change points (marked with "○") in the vertical direction using the data scan in the direction described above is performed using the previous data with X=n-1, {(n-1, Y ), Y=1~16)}, and the current data with X=n, the continuity with {(n, Y), Y=1~16), is determined by n-1, 2) to (n-1, 16),
(n, 1), (n, 2) to (n, 16), and perform EOR operation between adjacent address bits using, for example, 11 EOR circuits. If they match, it will be "0", if they do not match, it will be "0". Output “1” and
Check these 11 EOR outputs individually, and the position where an output of "1" is obtained is the change point ("〇" in Figure 1 a).
This is stored as shown in FIG. 1 b1. Alternatively, one EOR circuit may be prepared and the EOR detection may be performed while sequentially shifting the above bit information. In other words, the changing point positions marked with "〇" in Figure 1 b1 are as follows: When X=1, Y is 1, 3, 11, 13; When X=2, Y is 1, 4, 10, 14; When X=3, Y is are 1, 5, 10, 15... This vertical/horizontal calculation means calculates the scanning direction using previous data {(X, m-1), X=1 to 12},
If the current data is {(X, m), It will be a good thing. However, this conventional method has the disadvantage that it is necessary to check each displacement point bit by bit for the results of the individually detected EOR circuit. Figure 2B
If eight EOR circuits are used, the presence or absence of 8-bit displacement points can be determined at the same time, but the result must be checked bit by bit for each displaced bit. In this case, it is meaningless to use eight EOR circuits and obtain displacement point information at the same time. In this method, we add a judgment circuit (which can be easily configured with an 8-input AND circuit) that determines that all 8 bits are "0" for the result of the EOR circuit, and
It is conceivable to speed up the processing by providing a bypass method only when all bits do not contain displacement information, but if even one bit contains displacement information, it is necessary to examine all 8 bits, which is complicated. The effect becomes weaker as the characters become more pronounced. The more times such displacement information is checked, the longer it will take to obtain the contour table. The purpose of the present invention is to improve the above-mentioned drawbacks, and for this purpose, it is possible to extract only change point information indicating a substantial change from among multiple bits of change point information that are simultaneously EOR-processed with a minimum number of times. Furthermore, by using input data in the same scan direction, detection of change points in the vertical/horizontal (V/H) directions is realized with the same circuit, and a contour table can be obtained in a short time. An object of the present invention is to provide a change point detection circuit. The configuration diagram of the embodiment of the present invention shown in FIG. 3 will be described below. In FIG. 3, REG1 is an 8-bit first register that stores the previous scan information _B0 to _B7 ;
MPX1 is for data switching to perform horizontal (“X” mark in Figure 1) direction processing and vertical (“〇” mark in Figure 1) direction processing for input signals Y ₀ to Y ₇ in the same scan direction. The first multiplexer, EOR is an exclusive OR operation circuit, AND is an AND operation circuit,
REG2 is a second register that receives an output switched and obtained by multiplexer MPX2, which will be described later, and outputs the value and its inverted value. MPX2 is a second register that switches and accepts the output of the exclusive OR EOR and the output of the AND circuit. 2 multiplexer, PEC, detects the bit position of "0" that appears on the high-order bit position ( ₀ : Most Significant Bit) side in the inverted output of the second register REG2, and inverts and outputs that bit position and outputs "0". a high-order encoder (priority encoder) that detects whether there is a plurality of NOT is a negation circuit. The operation will be explained below. 8-bit current signal from a signal reader (not shown)
Y ₀ to Y ₇ [(X, m), X=1 to 8] is input to the input terminal IP, and the V/H of the first multiplexer MPX1
Set the terminal signal to “1” (high level state),
For example, signal processing in the vertical direction (detection of "O" in FIG. 1) is performed. Therefore, the input signals Y ₀ to _{Y 7} become one input signal of the EOR circuit, and the first register REG1
The previous signal B ₀ ~B ₇ [(X, m-1), X=1~
8] is the input terminal 1 of the first multiplexer MPX1
The signals are input to B to 8B, and appear at output terminals 01 to 08 by the above V/H switching, and become the other input of the EOR circuit. The output of this EOR circuit is inputted to the input terminals 1A to 8A of the second multiplexer MPX2 switched by signal 1, and then the second register
Set to REG2. The inverted outputs ₀ to ₇ of the second register REG2 detect the position of "0" from the MSB ₀ bit information side in the high-order encoder PEC.
For example, if the signal pattern input to the second register REG2 circuit is "01010000", its inverted outputs ₀ to ₇ will be "10101111", and the high-order encoder
PEC detects the first “0” at the second position from the left of this input pattern, and outputs the inverted output “001”, which is expressed in binary as “110” (decimal conversion is 6), to P1, Since it is output to the bit terminals of P2 and P4, P1, P2, and P are output via the NOT circuit NOT.
Notify the change point detector CHD of “110” output to terminal 4. Here, there is only one more "0" in the inverted outputs A ₀ to _{A 7} at the fourth position from the left, so
“0” is output to the EF terminal via the inverter NOT. The truth table of the high-order encoder PEC is shown in the table below.

[Table] In the above, A0 indicates MSB (most significant bit) and A7 indicates LSB (least significant bit). It also indicates that X may be 1 or 0. When the EF pin is “0”, the high-order encoder
The inverted output “001” of the PEC is applied to the decoder DEC, which takes the “1’s complement” of the input signal pattern and outputs the second D ₆ from the top of the output terminal of the decoder DEC as “ Outputs the output pattern “1011111” which makes the output “0”. Then, the outputs P1, P2, of the high-order encoder PEC,
When the change point detector CHD captures P3, a timing pulse is generated once. Then, the second multiplexer MPX2 is switched to the input terminals 1B to 8B by the switching signal 1, the output of the decoder DEC is applied to one direction of the AND circuit, and the output terminal of the second register REG2 is switched so that A ₀ ~A ₇
Applied to the other side of the AND circuit. Output A at this time _{is 0}
~A ₇ was “01010000”, so the decoder DEC
The output obtained by performing a logical product with the output pattern "10111111" becomes "00010000", and this signal pattern is held in the second register REG2. Therefore, this inverted output ₀ to ₇ is sent to the high-order encoder PEC.
Since “11101111” is applied, the inverted output 1,
P2,4 becomes "011" which is the inversion of the binary number "100", and "100" is sent to the change point detector CHD. Then, the output "011" is applied to the decoder DEC, but "1" is output to the terminal EF and an operation end flag is set indicating that all the changing points have been completed, so the input current signal Y ₀ ~ It is detected that there are only two change points at _Y7 . That is, since the output of the EOR circuit was "01010000", the 7th and 5th ones counting from the right, that is, the 6th
It is only necessary to extract the fact that there is a change point at two bit positions, the bit position and the fourth bit position, in two steps, and then proceed to process the next input data. Next, in the case of signal processing in the horizontal direction (marked with "x" in Figure 1a) using the same input signals _Y0 to _Y7 , the switching signal V/H for the first multiplexer MPX1 is set to "0". (low level state) sets the input terminal to the 1A to 8A side. Then, the output B7 from the first register REG1 is input to the terminal 1A, and the terminals 2A to 8A are input to the terminal 1A.
The current signals Y ₀ to _{Y 6} from the IP are inputted to one side of each of the EOR circuits via output terminals 01 to 08. Also, the current signals Y ₀ to _{Y 7} are input to the other EOR circuit. Therefore, the logical operation in the EOR circuit is the operation of B ₇ Y ₀ , YnYn ₊₁ (n=0 to 6). This includes the last bit of the previous data and the data shifted by 1 bit from the current data.
An EOR operation will be performed, and the subsequent operations will be performed in the same manner as in the vertical direction described above. In this way, according to the present invention, the hardware for signal processing is connected and configured, and the signals to be processed to obtain contour data are temporarily stored in the register and processed while being compared with the next data. Compared to the case where all bits are accumulated until the judgment is completed, if there is no change point in the pattern, the end flag is set only by the initial comparison judgment, so the next data is immediately fetched and the processing is stopped. Speed is increased. In addition, when detecting the position of a pattern change point, the processing direction can be easily changed by giving a signal that determines the processing direction to the multiplexer, and there is no need to transfer the captured data to another memory, making it efficient. This can be said to be a contour table operation circuit suitable for processing.

[Brief explanation of drawings]

Figure 1 shows a diagram and outline table for explaining pattern change point detection for the number "2", Figure 2 is a diagram explaining horizontal direction processing and vertical direction processing for detecting pattern change points, and Figure 3 shows a diagram explaining pattern change point detection. FIG. 1 is a configuration diagram of an embodiment of the present invention. EOR...Exclusive OR operation circuit, REG1, REG
2...Register, MPX1, MPX2...Multiplexer, PEC...High-order encoder, DEC...Decoder, CHD
...change point detector.

Claims (1)

[Scope of Claims] 1. A first register that holds the previous data of optically read characters; and a switchable output of either the output of the first register or a shift signal of the current input signal for horizontal and vertical processing. a first multiplexer for switching; an exclusive OR operation circuit that compares the output of the first multiplexer with current input signal data; and a second switching multiplexer that holds the output of the exclusive OR operation circuit or data of the sequential processing process. a register, a second multiplexer for switching between the output of the exclusive OR operation circuit, an output obtained by ANDing the output of the decoder below and the output of the second register, and a high-order bit for the output of the second register. A high-order encoder that measures the position of the high-order bit, and a decoder that resets the bit after knowing the high-order bit, and detects a pattern change point of the optical character reading output using the output of the high-order encoder. A pattern change point detection circuit characterized by: