JPH0127509B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In separating data pulses from a reproduced signal read from a magnetic recording medium, the present invention provides a plurality of reproduced data pulses between window pulses for data pulse separation generated in synchronization with the reproduced signal. The present invention relates to an information reading device that blocks transmission of a signal read from the magnetic recording medium when a signal is detected.

There are various types of magnetic storage (recording) devices used in electronic computers, such as magnetic tapes, magnetic disks, and magnetic drums, which are superior to perforated paper tapes in terms of reliability and processing speed.

For example, when a magnetic head 2 (reading and writing means) is brought into contact with a perspective view of a magnetic disk 1 as shown in FIG. A track 1a as shown in Figures a and b is formed.
The track 1a has information recording bands such as sectors 4 and 5.

Generally, when writing on a magnetic disk rotated by the magnetic head 2, the data is first read out, synchronized with the reproduction signal read from the disk, and written just before the data area to be recorded. controlled to switch to mode. During this switching operation, the data arrangement within that sector is disturbed and becomes discontinuous, so an area called a "gap" is created and the above switching operation is performed within this area to buffer the synchronization disturbance. The structure is such that the actual writing is performed after synchronization is completely achieved again and the beginning of the data area is reliably detected.

By the way, when writing is performed using the magnetic head 2, the previously recorded data (including writing by formatting) is overwritten, and within that gap, the transition from read mode to record mode is performed. Due to variations in the switching position, etc., when recording, previously recorded data may remain unused.
A so-called out-of-sync portion that is unrelated to the synchronization pattern may be formed.

Therefore, the next time data is read, or when the recorded information is read in order to synchronize prior to switching to the recording mode when performing the next recording, the aforementioned data remains. etc., it not only does not contribute to synchronization at all, but also erroneously detects a signal that should have no meaning, causing the entire system to be out of synchronization, and even in the write operation, the expected error occurs before and after switching to the write mode within the gap. may cause external malfunction,
There is a risk that problems such as the entire system becoming out of synchronization may occur.

For example, in the enlarged view of sector 4 in Figure 1b, 4a is an IDAM (ID Address Mark) area;
G ₁ and G ₂ are gap areas, and 4b is DAM (Data
Address Mark) area, when data is written in the gap G1 to the gap _G2 , the magnetic head 2 (FIG. _1a ) is switched from the reading state to the writing state. In this time disturbance region L, discontinuity, that is, disturbance occurs in the arrangement of data signals when changing from reading to writing.

In addition, since the writing position is detected and writing is started at an accurate timing, when reading is performed prior to writing, data disturbances, including past recordings remaining due to the above-mentioned deviations and variations in the recording position, can be avoided. There may be some parts where this occurs. This situation will be explained using pulse waveforms recorded in gaps G ₁ and G ₂ .

Note that the signals in the gaps G ₁ and G ₂ normally have the same form as data, but signals that have no meaning as data are written.

First, signal 6 in Fig. 2a is a clock pulse (clock signals P _C1 to P _C6 and a data pulse (information signal)).
Consists of P _D1 to P _D4 . The presence of adjacent clock pulses (for example, P _D1 ) means that information of "1" is transmitted, and the absence of data pulses between adjacent clock pulses (for example, P _C2 and P _C3 ) means that information of "0" is transmitted. has been transmitted.

Incidentally, in this type of device, the following countermeasures against rotational unevenness are generally taken to ensure that data can be reliably read even if the position of the data pulse changes due to rotational unevenness or the like.

That is, when rotational irregularities such as wow and flutter occur in the rotation of the disk 1 (FIG. 1a), the position of the data pulse shifts and is no longer detected at the correct position. This situation is shown by data pulse P _D2 in FIG. 2a.

When uneven rotation of disk 1 occurs in this way, the position of the data pulse, that is, the clock pulse
The time between reading P _C3 and reading data pulse P _D2 becomes unstable, causing a reading error. In order to improve this, first, a built-in oscillator generates the signal shown in FIG. 2b (synchronized with the clock pulses P _C1 to P _C6 of signal 6). Then the clock pulse formed on signal 7
After time t ₂ (t ₂ to 1/4t ₁ ) based on P _C1 , P _C2 , ... (pulse interval is t ₁ ), the gate is opened for only time t ₃ (t ₃ to 1/2t ₁ ) Create signal 8 [Figure 2 c]. Furthermore, when the data pulses P _D1 to P _D4 shown in Fig. 2a are detected during this time t ₃ (≒2 μsec), the pulses are generated with a delay of time t ₂ + t ₃ from the clock pulse [see Fig. 2 d]. For example, when a data pulse P _D1 is detected, a data pulse P' _D1 is generated at a position delayed by a time t ₂ +t ₃ from the clock pulse P _C1 ]. In this way, even if disk 1 has uneven rotation, stable data pulses P' _D1 to P' _D3 can be generated.
(Signal 9) can be read.

That is, if the deviation of the clock pulse is as small as this rotational unevenness, the data can be read accurately by creating a window pulse for data reading using the method described above.

However, if there is a large synchronization disturbance on the magnetic disk, such as a disturbance in the timing of switching from the read mode to the write mode of the magnetic head, as described above, It is difficult to compensate for this even with the above-mentioned method that is effective against rotational irregularities, and there is a risk that the synchronization of the entire system will be disrupted and unexpected malfunctions will occur.

The disturbance L which occurs when the head is switched from reading to writing shown in FIG. 1b can be explained in FIGS. 3a-d.

For example, suppose that a signal having a pattern of a clock pulse P _C1 , a data pulse P _D1 , and a clock pulse P C2 has been written on the track 1 a on the magnetic disk by the magnetic head 2, as shown in the signal 10 in FIG. _3a . Write operation (recording) in this state
Assume that as a result of repeatedly performing the above, the pulse P _E (clock pulse or data pulse) and the clock pulses P _C11 to P _C14 remain on the track 1a without being erased. Therefore, if a read operation is performed in this state,
These pulses P _E , P _C11 to _{P C14} will also be reproduced.

On the other hand, _the built-in oscillator generates the signal 11 _shown in _{FIG .} The pattern becomes discontinuous and runs on its own, and synchronization is lost between sections 11a. Then, from clock pulse _PC7 , the synchronization state is resumed.

Signal 12 in Figure 3c is a signal that opens the gate only for time t3 after time _t2 with reference to the clock pulses P _C1 to P _C7 [Figure 3b], similar to signal ₈ in Figure 2c. be. However, the clock pulse P _C3 in Figure 3b
Since P _C6 is not synchronized with the clock pulses P _C11 to P _C13 of FIG. 3a, the open gate of signal 12 transmits the pulses P _E , P _C11 , P _C12 of FIG. 3 a as data pulses. I end up. Therefore, as shown in FIG. 3d, the signal 13 becomes the wrong pulses P _E , P' _C11
P′ _C12 , resulting in disturbance of signal access to the DAM region 4b shown in FIG. 1b.

In other words, since the gap is originally a buffer area for synchronization, the data has no meaning, but during this period it may not be possible to absorb the disturbance and the synchronization of subsequent data may be disrupted, or the disturbance data reproduced by the magnetic head. If it is mistakenly detected as other meaningful data, there is a risk of unexpected malfunction.

The information recording and reproducing apparatus of the present invention prevents the above-mentioned disturbance by blocking the transmission of the pulses P _E , P' _C11 , P' _C12, etc., which are causing disturbances due to large clock fluctuations due to out-of-synchronization, etc. The present invention will be explained below.

FIG. 4 is a circuit diagram of the information recording and reproducing apparatus of the present invention, in which the signal read by the magnetic head 2 (reading and writing means) shown in FIG. applied.
5A to 5O show waveforms of signals flowing through each signal line in the circuit configuration diagram shown in FIG. 4 (vertical axis is voltage, horizontal axis is time).

In FIG. 4, signal 1 input to terminal 14
The waveform of 0 is shown in FIG. 5a, and this signal 10
is the same as the signal 10 shown in FIG. 3a. Signal 10 is input to one gate of AND circuits 22 and 23, respectively.

On the other hand, the input signal 10 is a PLL (Phase Locked
Loop) circuit 15 (phase locked circuit),
The PLL circuit 15 outputs a clock signal 15a shown in FIG. 5b using a built-in oscillator. Signal 15a is the clock pulse P _C1 and P _C2 of signal 10.
(the time interval between P _C1 and P _C2 is t ₁ ), but immediately after the data pulse P _D2 , there is a difference between the data pulse and the subsequent pulse due to variations in the switching operation position of the magnetic head as described above. Assume that a discontinuous part of the synchronization occurs, and the subsequent pulse P _E ,
It is assumed that a state of disorder exists until synchronization with P _C11 to _{P C13} is lost and clock pulse P _C14 arrives.

The delay circuit 16 inputs the signal 15a and waits for the time t ₂
(~1/4t ₁ ) signal 16 in Figure 5c.
Output a. Flip-flop 17 receives signal 16
In order to invert the signal at the rising pulse of the signal 16a, the output terminals Q and Q output a pulse signal 17a shown in FIG. 5d and a pulse signal 17b shown in FIG. 5e, respectively. This Q,
The output pulse signal of Q is a data window pulse located approximately midway between the clock pulses of input signal 10 for reading data. Also, the reason why the bipolar pulses are obtained from Q and Q here is that the flip-flop 17 inverts the output at each rising edge of the input signal, so the polarity of the subsequent output depends on the initial state of Q and Q. Since it is not decided,
This is because either the Q or Q pulse can be used as the data window pulse (for example, in Figure 5, the clock pulse
The output pulse of Q that is at a high level between P _C1 and P _C2 is used for data reading). For this reason, AND circuits 22 and 23, flip-flops 18 and 19, and flip-flops 20 and 21 are connected to the Q terminal side and Q terminal side of the flip-flop 17, respectively.
is provided.

And gate 22 outputs signal 10 and signal 1.
7a, its output is signal 2 in Figure 5f.
Since the AND gate 23 inputs the signal 10 and the signal 17b, its output becomes the signal 23a in FIG. 5g.

In this embodiment, the Q output of the flip-flop 17 is a data window pulse, and the
The data path P _D1 located within the data window of FIG. 5d can be detected by the circuit 22 as shown in FIG. 5f, and if the input signal 10 is a normal signal without disturbance, the clock pulse For example, since there is only one data pulse between P _C1 and P _C2 (only when the data is “1”),
A single data pulse can be obtained at the output of the AND circuit 22, as shown in FIG. 5f.

The outputs of the AND circuits 22 are respectively supplied to flip-flops 18;
8 is set at the falling edge of the output 22a of the AND circuit 22 to invert the output, and is forcibly reset at the falling edge of the output 17a of the flip-flop 17 shown in FIG. 5d. The output of the flip-flop 18 is then further supplied to the flip-flop 20.
is set so that the output is inverted at the fall of the output of the flip-flop 18, and is forcibly reset at the fall of the Q output of the flip-flop 17, that is, the data window pulse.

If we now look at the interval between the clock pulses P _C1 and P _C2 in the input signal of FIG. 5a, there is one data pulse P _D1 , which is a normal signal. In this case, the output 18a of the flip-flop 18 is the output pulse 22a of the AND circuit 22 (FIG. 5f) as shown in FIG. 5h.
rises at the falling edge of , flip-flop 1
7 falls at the falling edge of the output 17a (FIG. 5d), the pulse is passed to the flip-flop 20.
Since the falling edge of the pulse shown in FIG. 5h and the falling edge of the output of the flip-flop 17, that is, the falling edge of the data window pulse (FIG. 5 d), are the same, nothing is output from the output of the flip-flop 20.

However, if we look at the parts P _C2 , P _D2 , and P _E in Figure 5a, we can see that P _D2 , P _E
Since these two pulses fall within the data window output from the flip-flop 17, two pulses appear at the output of the AND circuit 22, as shown in FIG. 5f. When this pulse is supplied to the flip-flop 18, as shown in FIG. 5h, the output pulse that rises at the falling edge of the first pulse (corresponding to P _D2 ) is transmitted to the flip-flop 17 in FIG. Before the falling edge of the data window pulse, it is reversed at the falling edge of the second pulse (corresponding to P _E ), so in the end the pulse has the time width from the falling edge of pulse P _D2 to the falling edge of pulse P _E. will be output. Therefore, when this pulse is supplied to the flip-flop 20, a pulse 20a (FIG. 5j) having a time width from the falling edge of this pulse to the falling edge of the data window pulse in FIG. 5d is outputted.

In other words, when the input signal is normal and there is one data pulse within the data window (indicates data “1”; when there is no pulse, data is “0”)
If there is no output from the flip-flop 20 and, conversely, some output pulse is obtained from the flip-flop 20, it means that two or more pulse signals exist within the data window of FIG. 5d. This means that the data is out of order. This is the internal clock (Figure 5b and input signal 1).
This is nothing but a result of being out of synchronization with 0.

The above operation is exactly the same for the AND circuit 23, the flip-flop 19, and the flip-flop 21, and the flip-flop 1
When an abnormality occurs within the window outputted from the output Q of the flip-flop 21, the detection pulse appears in the output signal 21a of the flip-flop 21. 5g shows the waveform of the output signal 23a of the AND circuit 23, FIG. 5i the waveform of the output signal 19a of the flip-flop 19, and FIG. 5k the waveform of the output signal 21a of the flip-flop 21.

Then, the output 2 of flip-flops 20 and 21
0a and 21a are respectively supplied to an OR circuit 25, and when a disturbance detection pulse based on disturbance (out of synchronization) is output from any flip-flop, the OR circuit 25 outputs a signal 25a as shown in FIG. (a signal that detects the start of disturbance) is output.

The timer 26 falls down with the signal 25a and rises after a certain period of time, so that the timer 26 goes down with the signal 25a and starts up with the signal 25a shown in FIG.
6a is output. The AND gate 24 (blocking means) receives the signal 26a and the terminal 27, and receives the signal 27a shown in FIG. 13] and outputs the signal 24a shown in FIG. 5 from the terminal 28. The signal 24a is derived from the signal 27a by pulses P _E , P′ _C11 ,
P′ _C12 is removed and pulses input within a certain period of time after the start of disturbance are blocked, so the gap _G1 caused by variations in the writing start position within the gap shown in Fig. 1b, etc. Gap
Due to the disturbance part L between _G2 and G2, a clock pulse read in a different state from the normal state will not be mistakenly identified as a data pulse, and runaway or malfunction will not occur. Therefore, information can be read and written accurately and smoothly without disturbing access to the DAM area 4b (shown in FIG. 1b).

[Brief explanation of drawings]

Fig. 1a is a perspective view showing the contact between the disk and the head, Fig. 1b is a plan view of the track formed on the disk, and Figs. Waveform diagrams, Figures 3a to 3d are waveform diagrams of signals illustrating reading errors at the time of disturbance, Figure 4 is a circuit configuration diagram of the information recording and reproducing apparatus of the present invention,
5a to 5o are waveform diagrams of signals flowing through the circuit of the device of the present invention. DESCRIPTION OF SYMBOLS 1... Magnetic disk, 1a... Track, 2... Magnetic head, 15... PLL circuit, 16... Delay circuit, 1
7-21...Flip-flop circuit, 22-24...
AND gate, 25... OR gate, 26... timer circuit, 14, 27, 28... terminal.

Claims (1)

[Scope of Claims] 1. Reproducing means for reading signals from a magnetic recording medium; and clock generating means having a phase synchronization circuit for generating a clock signal in synchronization with a clock pulse in a reproduced signal read by the reproducing means. , means for generating a window pulse for separating data pulses in the reproduced signal based on the clock signal; detecting means for detecting the presence of a plurality of the reproduced signals while the window pulse is being generated; An information reading device comprising: means for blocking transmission of the reproduction signal for a predetermined period of time when a plurality of the reproduction signals are detected by the detection means.