JPH0127590B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device with improved contact holes assuming that it will be used in an environment where it is exposed to radioactive irradiation.

[Technical background of the invention and its problems]

As is well known, radiation irradiation increases leakage current between the source and drain regions. Conventionally, C (complementary type) has taken measures to reduce leakage current.
As a MOS transistor, the one shown in FIG. 4 is known. 1 in the figure is a P-type well region provided on the surface of an N-type semiconductor substrate (not shown). On the surface of this well region 1, an N ⁺ type source region 2, a drain region 3, a P type layer 4, and a P ⁺ type region 5 for substrate contact are provided. Here, the P ⁺ type region 5 is formed in a location different from the element region where the source and drain regions 2 and 3 are formed. A gate electrode 6 made of polycrystalline silicon is formed on the channel region between the source and drain regions 2 and 3. An interlayer insulating film (not shown) is provided on the entire surface of the substrate including the gate electrode 6, and the source region 2,
A source contact hole 7, a drain contact hole 8, and a substrate contact hole 9 are provided in portions corresponding to the drain region 3 and the P ⁺ type region 5, respectively.

However, the CMOS transistor shown in FIG. 4 has the following drawbacks.

In order to firmly fix the substrate current, it is necessary to provide the substrate contact hole 9 at a location different from the element region, which leads to a decrease in the degree of integration.

For the same reason as above, substrate resistance is introduced between the P ⁺ type region 5 and the element region. As a result, the substrate potential of the device tends to fluctuate due to the substrate current, and latch-up is likely to occur.

Further, as another conventional CMOS transistor, the one shown in FIG. 5 is known.
This transistor has a structure in which a source contact hole 11 and a substrate contact hole 12 are provided at the same location. however,
According to the transistor in FIG. 5, P ⁺ type region 1
3 is formed in contact with the source region 2, it is necessary to make the source, drain, and gate (SDG) regions large, which leads to a decrease in the degree of integration.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to provide contact holes for the source and the substrate at the same location without causing a decrease in the degree of integration. An object of the present invention is to provide a semiconductor device that can prevent an increase in leakage current.

[Summary of the invention]

The gist of the present invention is to have the following two points.

By providing a contact hole that engages both the source region and the semiconductor region at the same time, it is possible to avoid providing a contact hole for the substrate in a separate location away from the element region as in the conventional method, and improve the degree of integration. To aim for.

By providing a semiconductor region of the same conductivity type as the semiconductor substrate directly below the gate electrode and at least on the outer edge of the source region in a direction perpendicular to the gate electrode, leakage current between the source and drain regions that increases due to radiation irradiation can be reduced. To reduce.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A CMOS transistor according to an embodiment of the present invention will be described below in the order of manufacturing steps with reference to FIGS.

First, a P-type well region 21 is formed on the surface of a silicon substrate (not shown), and then a buffer SiO ₂ film 22 and a Si ₃ N ₄ film are formed on the well region 21.
Patterning the Si ₃ N ₄ film to create Si ₃ N ₄ pattern 23
was formed (as shown in Figure 1a). Next, this
Field oxidation was performed using the Si ₃ N ₄ pattern 23 as a mask to form a field oxide film 24 (as shown in FIG. 1b). In addition, in the same figure b, 25 indicates an element region. Next, the Si ₃ N ₄ pattern 24
After removing the SiO ₂ film 22 on the element region 25, a gate oxide film 26 with a thickness of about 500 Å was formed (as shown in FIG. 1c). Furthermore, the element region 25
After forming a resist 28 on the entire surface except for the SDG region 27, using this resist 28 as a mask, boron is applied to the element region at an acceleration voltage of 40 keV and a dose of 5×.
Ion implantation was performed under the condition of 10 ¹² /cm ² to form a P-type region 29 as a semiconductor region. Here, the P-type region 29 was formed at a part of the outer edge of the SDG region 27 and perpendicular to the gate electrode described later (see d in Fig. 1).
(Illustrated). After that, the resist 28 is removed,
A gate electrode 30 made of polycrystalline silicon was formed on the well region 21 via a gate oxide film 26 by a normal process, and an N ⁺ type source region 31 and a drain region 32 were formed. Subsequently, after forming an interlayer insulating film 33 on the entire surface, the interlayer insulating film 33 and the gate oxide film 26 corresponding to the source region 31 and the P-type region 29 are simultaneously opened to form contact holes 34 for the source and the substrate. At the same time, a contact hole 35 for the drain was formed by opening the interlayer insulating film 33 corresponding to the drain region 32. After this, gate oxide film 26 and interlayer insulating film 3
A CMOS transistor was manufactured by forming a metal wiring 36 on the substrate 3 (as shown in FIG. 1e, FIG. 2, and FIG. 3). Here, Figure 2 is a plan view of Figure 1 e, and Figure 3 is a plan view of Figure 1 e.
The figure is a sectional view taken along the line XX in FIG. 2.

As shown in FIGS. 2 and 3, the CMOS transistor according to the present invention includes a P-type region 29 provided in the element region 25 at a part of the outer edge of the SDG region 27 and perpendicular to the gate electrode 30. The structure is such that source and substrate contact holes 34 are provided to electrically connect the source region 31 and the P-type region 29.

Therefore, according to the CMOS transistor according to the present invention, unlike the conventional CMOS transistor shown in FIG. 4, there is no need to provide a new location for making contact with the substrate. Therefore, contact can be made between the source region 31 and the substrate at the same time without reducing the degree of integration.

Further, since contact can be made between the source region 31 and the substrate at the same time, the substrate current can be significantly reduced compared to the conventional method, and fluctuations in the substrate potential of the device can be reduced to prevent latch-up.

Furthermore, since the P-type region 29 is provided in the element region 25 at a part of the outer edge of the SDG region 27 and perpendicular to the gate electrode 30, the P-type region 29 is provided between the source and drain regions 31 and 32 in an environment exposed to radiation. Increase in leakage current can be reduced.

In the above embodiment, ion implantation for forming the P-type region was performed after the formation of the gate oxide film, but the gate oxide film may be formed after the ion implantation.

Further, in the above embodiment, the P-type region is provided at a part of the outer edge of the SDG region and perpendicular to the gate electrode, but the present invention is not limited to this. That is, it may be provided in the element region directly under the gate electrode and at least on the outer edge of the source region in a direction perpendicular to the gate electrode.

Further, in the above embodiment, the case where the present invention is applied to a CMOS transistor has been described, but the present invention is not limited to this, and the present invention can be similarly applied to an n-channel type MOS transistor.

〔Effect of the invention〕

As detailed above, according to the present invention, contact holes for the source and the substrate can be provided at the same location without reducing the degree of integration, and an increase in leakage current between the source and drain regions can be prevented. This makes it possible to provide highly reliable semiconductor devices such as CMOS transistors.

[Brief explanation of drawings]

FIGS. 1a to 1e show CMOS according to an embodiment of the present invention.
2 is a plan view of the transistor shown in FIG. 1 e, FIG. 3 is a sectional view taken along the line X--X of FIG.
FIG. 2 is a plan view of a CMOS transistor. 21... P-type well region, 23... Si ₃ N ₄ pattern, 24... field oxide film, 25... element region, 26... gate oxide film, 27... SDG
region, 29...P type region, 30... gate electrode,
31... N ⁺ type source region, 32... drain region, 33... interlayer insulating film, 34, 35... contact hole, 36... metal wiring.

Claims (1)

[Claims] 1. A semiconductor substrate, a source and drain region provided on the surface of this substrate, a gate electrode provided on the same substrate via a gate oxide film, and a region immediately below the gate electrode and at least the outer edge of the source region on the surface of the substrate. What is claimed is: 1. A semiconductor device comprising: a semiconductor region of the same conductivity type as a substrate and provided in a direction perpendicular to a gate electrode; and a contact hole electrically connected to both the source region and the semiconductor region at the same time.