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JPH0128515B2 - - Google Patents
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JPH0128515B2 - - Google Patents

Info

Publication number
JPH0128515B2
JPH0128515B2 JP56034582A JP3458281A JPH0128515B2 JP H0128515 B2 JPH0128515 B2 JP H0128515B2 JP 56034582 A JP56034582 A JP 56034582A JP 3458281 A JP3458281 A JP 3458281A JP H0128515 B2 JPH0128515 B2 JP H0128515B2
Authority
JP
Japan
Prior art keywords
copper foil
inner layer
printed wiring
multilayer printed
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56034582A
Other languages
Japanese (ja)
Other versions
JPS57149789A (en
Inventor
Yoshinori Kamikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP3458281A priority Critical patent/JPS57149789A/en
Publication of JPS57149789A publication Critical patent/JPS57149789A/en
Publication of JPH0128515B2 publication Critical patent/JPH0128515B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、内層パターンが共通化された多層印
刷配線基板の電子部品接続方法に関する 電子機器の小型化、接続技術およびパツケージ
ングに使用されている多層印刷配線基板は、両面
印刷配線基板と比較して実装密度の向上や、雑音
に対して強いという特徴を持つているが、一方で
は製造コストが高いことや完成された基板の回路
変更が困難である等の欠点があつた。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for connecting electronic components to a multilayer printed wiring board with a common inner layer pattern. Compared to double-sided printed wiring boards, it has improved packaging density and is more resistant to noise, but it also has drawbacks such as high manufacturing costs and the difficulty of changing circuits on completed boards. It was hot.

特に、製造コストをできるだけすくなくする方
法として、部品の電源やアース用として使用され
る内層パターンをマスラミネーシヨン方式により
共通化する方法があり、これによつて内層パター
ンの大量生産を可能にしてコストの低減を計つて
いる。
In particular, as a method to reduce manufacturing costs as much as possible, there is a method of using the mass lamination method to standardize the inner layer patterns used for power supply and grounding of components.This makes it possible to mass produce inner layer patterns and reduce costs. We are planning to reduce this.

しかしながら、上記した方法において以下に述
べるような欠点を有している。
However, the above method has the following drawbacks.

すなわち、第1図で示すように、基板1に部品
の基板との接続部の径2が太いもの、又はねじな
どの取付部品の取付穴3が大きい部品(以下デイ
スクリート部品)を実装しようとすると内層パタ
ーン4の電気的短絡を起こしてしまい、これらの
部品を取付ける場合に内層パターン4を、取付け
られる部品に対応した取付穴を作成しなければな
らず、結果的に多層板としてそれぞれ独得なパタ
ーンを持つたものを準備しなければならず、安価
な多層印刷配線基板の提供や、標準化の障害とな
つていた。
In other words, as shown in Fig. 1, if you are trying to mount a component with a large diameter 2 at the connection part with the board on the board 1, or a component with a large mounting hole 3 for a mounting part such as a screw (hereinafter referred to as a discrete component), This will cause an electrical short circuit in the inner layer pattern 4, and when attaching these parts, it is necessary to create mounting holes in the inner layer pattern 4 corresponding to the parts to be attached, and as a result, each multilayer board has its own unique characteristics. It was necessary to prepare a board with a pattern, which was an obstacle to the provision of inexpensive multilayer printed wiring boards and to standardization.

本発明は、以上のような点に鑑みなされたもの
で、従来から使用されている内層パターンをその
まま用いてこのパターンと電気的短絡を起こすお
それのある場合には、そのパターンの銅箔部を内
側と外側とに分離し同一層内において、上記の短
絡による他への影響を除去した多層印刷配線基板
の電子部品接続方法を提供する。
The present invention has been made in view of the above points, and when a conventionally used inner layer pattern is used as it is and there is a risk of electrical short circuit with this pattern, the copper foil portion of the pattern is removed. To provide a method for connecting electronic components of a multilayer printed wiring board, which eliminates the influence of the above-mentioned short circuit on other parts within the same layer by separating the inner and outer parts.

以下本発明を適用した一実施例を第2図以下の
図面を参照しながら説明する。
An embodiment to which the present invention is applied will be described below with reference to FIG. 2 and the following drawings.

第2図は、本発明を適用した一実施例を示し、
その多層印刷配線基板の一部分を拡大してさらに
一部分を切欠した外観図である。
FIG. 2 shows an embodiment to which the present invention is applied,
FIG. 2 is an enlarged external view of a portion of the multilayer printed wiring board with a portion thereof cut away.

図中、多層印刷配線基板は、複数の層から構成
され表面に外層11、内部に複数の内層12(図
中では、1つの内層のみ示さず)からなる。前記
内層12には表面が複数の非銅箔部(以下円状ク
リアランスという)13部分を除いて、全体にわ
たつてパターン化された銅箔部14が構成されて
いる。
In the figure, the multilayer printed wiring board is composed of a plurality of layers, including an outer layer 11 on the surface and a plurality of inner layers 12 (only one inner layer is not shown in the figure). The inner layer 12 has a copper foil portion 14 whose surface is patterned over the entire surface except for a plurality of non-copper foil portions (hereinafter referred to as circular clearances) 13.

さらに前記外層11と内層12とを貫ぬいて部
品取付穴15が設けられ、外層11に載置された
デイスクリート部品のリード線を挿入し所望の内
層と電気的接続を可能とする。
Furthermore, a component attachment hole 15 is provided through the outer layer 11 and the inner layer 12, through which a lead wire of a discrete component placed on the outer layer 11 can be inserted to make electrical connection with a desired inner layer.

16は、前記部品取付穴15に挿入されるリー
ド線が太い場合に、前記内層12の表面の銅箔部
を2分するために設けられる穴である。この穴1
6は図示しないが一般的な穴をあけ機によつてあ
けられるもので、内側を銅メツキされないノンス
ルーホールである。
Reference numeral 16 denotes a hole provided to divide the copper foil portion on the surface of the inner layer 12 into two when the lead wire inserted into the component mounting hole 15 is thick. this hole 1
Reference numeral 6 indicates a non-through hole that is drilled using a general hole punching machine (not shown) and whose inside is not plated with copper.

17は、外層11の表面にある配線パターンを
示す。
Reference numeral 17 indicates a wiring pattern on the surface of the outer layer 11.

なお、第3図は、第2図の内層12だけを取出
して上からみた平面図、第4図は、第2図の外層
11の上からみた平面図を示す。
3 shows a plan view of only the inner layer 12 of FIG. 2 taken out and viewed from above, and FIG. 4 shows a plan view of the outer layer 11 of FIG. 2 seen from above.

以上のような本発明の多層印刷配線基板の接続
方法について、その作用を説明する。
The operation of the multilayer printed wiring board connection method of the present invention as described above will be explained.

まず、内層12のクリアランス13の直径が2
mmで、一定の間隔で第3図のように全体に広がつ
ているパターンを保有する基板において、前記ク
リアランス13の直径よりも大きい直径を有する
電子部品のリード線に対する取付けは、取付穴1
5が小さいとそのままでは前記内層12パターン
の電気的短絡を起こしてしまい、部品の実装は不
可能となる。
First, the diameter of the clearance 13 of the inner layer 12 is 2
mm, and has a pattern that extends over the entire surface at regular intervals as shown in FIG.
If 5 is small, an electrical short circuit will occur in the inner layer 12 pattern, making it impossible to mount components.

従つて、前記内層12の銅箔部14を第3図の
内側銅箔部14aと外側銅箔部14bとに電気的
に断つた形で二分割できるように複数個からなる
穴16を設ける。
Therefore, a plurality of holes 16 are provided so that the copper foil portion 14 of the inner layer 12 can be electrically separated into two parts, an inner copper foil portion 14a and an outer copper foil portion 14b as shown in FIG.

前記穴16によつて、リード線に接する内層銅
箔部を外側銅箔部と分離し内層パターンの短絡を
防止する。
The hole 16 separates the inner layer copper foil portion in contact with the lead wire from the outer copper foil portion, thereby preventing short circuits in the inner layer pattern.

なお、前記穴16は隣接するクリアランス13
との間の銅箔を切断するために前述したようにノ
ンスルーホールであり、この穴16の孔あけ工程
は、外層11のエツチング終了後に行うことが最
適である。
Note that the hole 16 has an adjacent clearance 13.
As mentioned above, this hole 16 is a non-through hole for cutting the copper foil between the outer layer 11 and the outer layer 11. It is best to perform the drilling process for this hole 16 after the etching of the outer layer 11 is completed.

以上のように、本発明は、内層パターンが共通
化された多層印刷配線基板において、従来実装で
きなかつた電子部品が新たな内層パターンを準備
することなく実装可能となり、従つて共通化の実
現や標準化の実現に大いに項献が期待でき、さら
に製品のコスト低減や、納期短縮、そして工数の
縮減に大いに寄与するものである。
As described above, the present invention enables electronic components that could not be mounted conventionally to be mounted on a multilayer printed wiring board with a common inner layer pattern without preparing a new inner layer pattern. It is expected that this will greatly contribute to the realization of standardization, and will also greatly contribute to reducing product costs, shortening delivery times, and reducing man-hours.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の多層印刷配線基板の接続方
法、第2図は、本発明を適用した一実施例の多層
印刷配線基板の一部拡大切欠概観図、第3図は、
第2図の内層12を取り出した平面図、第4図
は、第2図の外層11のみを取り出した平面図。 11…外層、12…内層、13…クリアラン
ス、14,14a,14b…銅箔部(内側、外
側)、15…部品取付穴、16…穴。
FIG. 1 shows a conventional method for connecting a multilayer printed wiring board, FIG. 2 shows an enlarged partially cutaway schematic diagram of a multilayer printed wiring board according to an embodiment of the present invention, and FIG.
2 is a plan view showing the inner layer 12 taken out, and FIG. 4 is a plan view showing only the outer layer 11 shown in FIG. 2 taken out. DESCRIPTION OF SYMBOLS 11... Outer layer, 12... Inner layer, 13... Clearance, 14, 14a, 14b... Copper foil part (inside, outside), 15... Component mounting hole, 16... Hole.

Claims (1)

【特許請求の範囲】[Claims] 1 内装パターンが共通に構成された多層印刷配
線基板の電子部品接続方法において、内装パター
ン内に複数個の非銅箔部(クリアランス)を設
け、前記クリアランスの一部を破壊する大きさの
電子部品が実装される際に、あらかじめ前記破壊
されるクリアランスの近傍に位置する他の複数の
クリアランスのそれぞれに介在する銅箔部を周辺
の銅箔部より切断するようにし、電子部品と接す
る銅箔部とは切離して弧立化するようにしたこと
を特徴とする多層印刷配線基板の電子部品接続方
法。
1. In a method for connecting electronic components to a multilayer printed wiring board having a common interior pattern, a plurality of non-copper foil parts (clearances) are provided in the interior pattern, and the electronic component is large enough to destroy part of the clearances. When the electronic component is mounted, the copper foil portions intervening in each of the other multiple clearances located near the clearance to be destroyed are cut from the surrounding copper foil portions, and the copper foil portions in contact with the electronic components are cut off from the surrounding copper foil portions. A method for connecting electronic components to a multilayer printed wiring board, characterized in that the electronic component is separated from the board and formed into an arc.
JP3458281A 1981-03-12 1981-03-12 Method of connecting electronic part of multilayer printed circuit board Granted JPS57149789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3458281A JPS57149789A (en) 1981-03-12 1981-03-12 Method of connecting electronic part of multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3458281A JPS57149789A (en) 1981-03-12 1981-03-12 Method of connecting electronic part of multilayer printed circuit board

Publications (2)

Publication Number Publication Date
JPS57149789A JPS57149789A (en) 1982-09-16
JPH0128515B2 true JPH0128515B2 (en) 1989-06-02

Family

ID=12418308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3458281A Granted JPS57149789A (en) 1981-03-12 1981-03-12 Method of connecting electronic part of multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS57149789A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3820955B2 (en) 2001-10-12 2006-09-13 日本電気株式会社 Build-up substrate and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5543639B2 (en) * 1973-12-29 1980-11-07

Also Published As

Publication number Publication date
JPS57149789A (en) 1982-09-16

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