JPH0128534B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a CCD (charge coupled device) comb filter.

The practical application of CCD comb filters in the TV field has been rapidly promoted in recent years. into a comb filter
The advantages of using a CCD are the high precision of the delay time determined by the clock frequency and the ease of addition and subtraction. Considering the application of the NTSC system to TV receivers, it is known that color and luminance signals can be easily separated by using a comb filter, since a frequency interleaving color subcarrier transmission system is used. The figure of merit indicating the quality of this separation is the level difference (hereinafter referred to as suppression ratio) between the peak level and the adjacent notch level in the comb characteristic. Here, the peak level refers to the Y signal at a frequency that is an integral multiple of the horizontal scanning frequency f _h , that is, nf _h , where the energy of the Y signal is originally concentrated and distributed in the brightness channel that extracts the brightness signal (hereinafter referred to as the Y signal).
It shows the response of the signal, and the notch level shows the response of the Y signal at a frequency that is an odd multiple of half of the horizontal scanning frequency f _h , where the energy of the color signal (hereinafter referred to as the C signal) is concentrated and distributed, that is, 2 m + 1/2 f _h . . Of course, in the color channel for extracting the C signal, the response of the C signal at the frequency 2m+1/2f _h is called the peak level, and the response of the C signal at the frequency nf _h is called the notch level. The practical value for this suppression ratio is 30dB or more.
Considering the response deterioration in the frequency band near the subcarrier frequency f _sc of 3.58 MHz, approximately 40 dB or more is desirable. This deterioration of the response in the high range reduces the horizontal resolution, making it impossible to take advantage of the original characteristics of the comb filter. When a CCD is used to realize a comb filter, the factors that determine the suppression ratio are the non-transfer efficiency of the CCD and the phase difference between sampling points in two CCD channels (hereinafter referred to as channels A and B). Here we will take an example using a 1H delay line with 682.5 elements driven at a sampling frequency of 3f _sc . Drive at the frequency 3f _sc (10.7MHz)
The CCD comb filter uses a so-called alternating sampling method in which sampling is performed alternately every half cycle to send signals to channels A and B. Channel A at the time of addition or subtraction;
The time difference between B and B is 63.5μs (1H delay time), so if channel A is 683.5 elements, channel B
A 1.0 element CCD configuration is adopted. As is clear from the above explanation, in the alternate sampling method, the phase of the sampling point of information for each 1H delay time is shifted by 180°. The brightness channel is a 683.5 element channel section (hereinafter referred to as the main section)
and a 1.0 element delay stage section (sub section) B1, and the color channel consists of the main section and the sub section B1.
It consists of a 1.0 element sub-section B2 provided separately from the sub-section B2, and addition and subtraction of each channel is performed in the form of charges at a PN junction provided at the output section.
To obtain the C signal, a subtraction must be performed, and for this purpose it is necessary to invert the input signal by 180° and supply it to the sub-section B2. But in reality,
The same effect is obtained by applying the opposite signals to the two input gates to the sub-section B1 by taking advantage of the characteristics of the charge preset input method.

Figures 1a and 1b show the configuration of the input section and output section of a general CCD comb filter, and their driving waveforms, respectively. In Fig. 1a, terminals G _1M , G _2M ,
The gate portions connected to each of G _1S , G _2S , P1, P2, and OG are provided on the p-type semiconductor substrate 12 via a gate insulating film (not shown), and the n ⁺ diffusion layer 11, 11', 11'' are p-type semiconductor substrate 12 and
It is configured by forming a PN bond, and furthermore, the channel A
Alternatively, the buffer amplifier 13 for detecting the potential change of the n ⁺ diffusion layer (floating diffusion layer) 11' due to the charge sent from B with low impedance is
Constructed on-chip with MOSFETs. Of course, since the potential of the n ⁺ diffusion layer 11' is periodically reset to the potential of the terminal RD by the pulses of the terminal P1, the output _V0 of the buffer amplifier 13 has a hold waveform with the reset level as a reference. Figure 1b
The drive waveform shown in FIG. 1A is supplied to the corresponding terminals of channels A and B in FIG. 1a. In the charge preset input method, generally a DC bias is applied to the terminals G _1M and G _1S , and a TV signal superimposed on the DC bias is applied to the terminals G _2M and G _2S . However, if channel B shown in FIG. 1a is sub-section B1, then sub-section B2
Needless to say, a DC bias is applied to the terminal _G2S , and a TV signal superimposed on the DC bias is applied to the terminal _G1S . At the input section of the CCD comb filter, charges corresponding to the signal are sampled under the gate section (hereinafter referred to as _G2 gate) connected to terminals G _2M and G _2S . In channel A, a charge is charged under the _G2 gate by the preset pulse to the terminal ID1 during the off period of the drive pulse waveform of the terminal P1,
It is discharged to the n ⁺ diffusion layer (input diode) 11 during the sampling opening time td ₁ , but the terminal P
Charge is transferred to the transfer stage at time t ₂ when the drive waveform No. 1 is turned on. Therefore, the effective sampling point is time t ₂
It is. Similarly, channel B (sub parts B1 and B
2), sampling is performed during the off period of the drive waveform of terminal P2, and the sampling opening time is
After discharging during the period td ₂ , the charge is transferred to the transfer stage at time t ₄ when the drive waveform of terminal P 2 is turned on, so the effective sampling point is time t ₄ . The non-transfer efficiency characteristic can be ignored since a value of 2×10 ^-5 or less is obtained in a normal process, and the effect on the suppression characteristic of the CCD comb filter is small.

However, the effective sampling point is time
Phase difference T1 between t ₂ and t ₄ and phase difference T between times t ₁ and t ₃
The amount of shift from 180° in No. 2 greatly controls the characteristics of the CCD comb filter, so it is considered to be an important factor. In reality, it is easy to provide a 180° phase difference between the OFF points of the pulse waveforms of terminals ID1 and ID2, but it is difficult to create a 180° phase difference between the ON points of the drive pulse waveforms of terminals P1 and P2. It is difficult to control. For this reason, the conventional drive system has the disadvantage that it is not possible to equalize the sampling opening time, that is, to make td ₁ =td ₂ .

FIG. 2 is a circuit diagram showing an example of a conventional clock driver for driving a CCD comb filter. Actually, there is also a pulse generation logic section on the pulse supply side to the terminals ID1, ID2, and PI, but it is omitted here. A pulse with a duty ratio of 50% is supplied to the terminal PI, and the inverter has an E/D configuration.
Inverted by MOSFET M1, M2 and connected to terminal N
1 is sent to a high-speed bootstrap circuit or a high-speed buffer circuit B1 (hereinafter referred to as B1 circuit). The output terminal N2 of the B1 circuit is connected to a bootstrap circuit or a buffer circuit B2 (hereinafter referred to as the B2 circuit) having the same circuit configuration as the B1 circuit, and is also connected to a push pull circuit for sending drive pulses to the terminals P1 and P2 at low impedance. It is also connected to MOSFETs M4 and M5 in the circuit configuration.
Furthermore, the pulse speeded up by the B2 circuit is transferred to the terminal N3.
output from the push-pull circuit configuration.
Supplied to MOSFETs M3 and M6.

Figure 3 shows the terminals PI of each circuit element in Figure 2,
The operating waveforms at N1, N2, P1, and P2 are shown. The pulse with a frequency of 3f _sc supplied to the terminal PI undergoes large waveform distortion in the MOSFETs M1 and M2 of the first stage inverter, resulting in a waveform with a long rise time and short fall time, and is sent to the terminal N1 of the next stage B1 circuit. Sent. Here, the B1 circuit with terminal N1 as the gate
Since the threshold voltage of MOSFET is constant, the output waveforms of MOSFETs M1 and M2 of the first stage inverter cross the threshold voltage at times t _a , t _b , t _c
Therefore, the pulse waveform of the potential change at the output terminal N2 of the B1 circuit has a duty ratio greater than 50%. Here, if the period T = t _b - t _a and T = t _c - t _b , then T = > T = and a pulse with a waveform that clearly has a duty ratio greater than 50% is sent from terminal N2 to B2 circuit. Supplied. Push-pull circuit
MOSFETs M3 and M6 dynamically change their operation according to the pulse waveform at terminal N2 and the complementary pulse waveform at terminal N3, so a pulse with a duty ratio approximately corresponding to the pulse waveform at terminal N2 is applied to terminal P1. Output. First, when the potential of the terminal N2 changes to a rising state, the potential of the terminal P1 shows a rising transition, and the potential of the terminal P2 becomes a falling transition state. Further, when the potential of the terminal N2 changes to a falling state, the potential of the terminal P1 shows a falling transition due to a rising transition change of the potential of the terminal N3, and the potential of the terminal P2 becomes a rising transition state. At this time, since the change in the potential of the terminal N2 directly determines the duty ratio of the drive pulse waveform of the terminals P1 and P2, the high level period of the potential of the terminal P1 is approximately equal to the period T〓, and the high level of the potential of the terminal P2 The period is approximately equal to the period T〓. Therefore, the duty ratio of the drive pulse waveform appearing at the terminals P1 and P2 deviates from 50%.

The clock driver in this example is integrated into an IC on a CCD chip along with other logic sections such as the pulse generation logic section, but since its dynamic characteristics are determined at the time of circuit design and mask pattern design, once integrated into an IC, Subsequent control of the characteristics of the clock driver becomes almost impossible. At the time of mask pattern design, the B1 circuit and B
Even if the rise time and fall time of the two circuits are controlled, there are differences between the design target characteristics and the actual characteristics, there is a shift in threshold voltage due to process variations, and there are differences in transconductance g _n (hereinafter simply g _n ), due to the existence of fluctuations, etc.
It was extremely difficult to make the duty ratios of the drive pulse waveforms of the terminals P1 and P2 equal to 50.0%. In practice, a suppression ratio of 40 dB or more cannot be obtained unless the phase difference T1 between sampling points times t ₂ and t ₄ shown in FIG. 1b is within ±0.8 ns with respect to 46.56 ns.

When such a phase shift exists at the sampling point, the characteristics of the CCD comb filter are that a frequency shift occurs at the peak level and notch level, and the attenuation of the notch level decreases, resulting in a deterioration of the suppression ratio. Since the absolute gain of the level also deteriorates as the frequency becomes higher, a problem arises in that the horizontal resolution where the energy spectrum is concentrated in the high frequency region deteriorates.

Furthermore, in terms of image quality, since there is little attenuation at frequencies where the regular Y signal and C signal spectra are concentrated, not only dot interference becomes noticeable due to the leakage of the C signal into the luminance channel, but also the leakage of the Y signal into the color channel. As a result, cross-color interference becomes more noticeable. As is clear from the above explanation, shifting the sampling point from the normal phase difference does not take advantage of the original advantages of the CCD comb filter. In the conventional CCD comb filter driving method, the phase difference between the sampling points is set to 0.8 ns.
The drawback was that it was almost impossible to fit it into the following.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for driving a CCD comb filter that eliminates the above-mentioned drawbacks by adding a duty control section to the input inverter section of a conventional clock driver.

According to the present invention, a CCD comb filter that alternately samples one CCD main channel and two CCD subchannels every half cycle is driven by a charge preset input method.
In a method for driving a comb filter, two control MOSFETs are provided in parallel with each of the load MOSFET and the drive MOSFET of the inverter stage in the drive circuit for supplying two-phase pulses for driving the CCD channel, and each gate of the MOSFET is connected to the drive MOSFET. A DC bias from each part and a complementary DC bias via an analog inversion circuit of the drive circuit are supplied to A method for driving a CCD comb filter is obtained, which is characterized in that the CCD comb filter is operated while the sampling points coincide with each other and the sampling points are shifted by 180°.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram of a clock driver showing an embodiment of the CCD comb filter driving method of the present invention. In this figure, the same components as in FIG. 2 are given the same symbols. In this example, for the sake of convenience, an example using an n-channel MOSFET formed into an IC on a p-type semiconductor substrate will be explained.
Needless to say, it can also be applied to MOSFETs.

In this embodiment, a MOSFET for duty control of drive pulses appearing at terminals P1 and P2 is added to the circuit configuration of the conventional clock driver shown in FIG.
The configuration is such that M7, M8 and analog inverting circuits M9, M10 for DC bias control are added. MOSFETs M7 and M8 are designed to solve the problem of conventional clock drivers, where it is impossible to control the duty ratio of the pulse waveform due to the extreme difference between the rise time and fall time of the first stage inverter. is added to the first stage inverter's load MOSFET M2 and drive MOSFET M1.
g _n is added to each of . here,
It is preferable that the MOSFET M7 is the same type of FET as the enhancement type drive MOSFET M1, and the MOSFET M8 is the same type as the depletion type load MOSFET M2. Also,
W/L of MOSFET M7 and M8 to greatly change the dynamic operation of the pulse of terminal N1.
(Channel width/Channel length) are as above.
It is desirable that the W/L is about the same as that of MOSFETs M1 and M2. Furthermore, in this example,
Analog inverting circuits M9 and M10, which are E/D configuration inverters, are provided for DC bias control of the gates of MOSFETs M7 and M8, and one terminal VI
DC bias (hereinafter referred to as VI bias) applied externally to the two MOSFETs M7 and M8
It has become possible to change g _n . In this case, the VI bias is not only supplied to MOSFET M9 as an input of the analog inversion circuit, but also to MOSFET M8. And the output V1 of the analog inversion circuit is MOSFET
It is supplied to the gate of M7.

Next, the operation of this embodiment will be explained. Figure 5 shows the terminals PI, N1, N of each circuit element in Figure 4.
2, the operating waveforms at P1 and P2 are shown. FIG. 6 is a diagram showing the input/output characteristics of the analog inversion circuit shown in FIG. 4, where the horizontal axis represents VI bias and the vertical axis represents output V1. When the high level period of the pulse waveform output from the terminal N1 is 50% or less of one cycle (hereinafter referred to as the first case), the VI bias is set to a high level VI near the power supply voltage _VDD . Then, the output level V1 of the analog inversion circuit is
7 or lower. In fact, MOSFETs M9 and M10 have such characteristics.
It is preferable to determine the beta ratio of At this time
Since a high-level DC bias is always applied to the gate of MOSFET M8, its g _n is
It is larger than g _n of MOSFET M2. In other words, the pulse waveform of terminal PI turns off and terminal N
When the pulse waveform No. 1 is in a rising transition state, the gate potential of MOSFET M2 dynamically rises from 0V to the power supply voltage _VDD , so the average _{g n} is lower than that of MOSFET M8. There is. Therefore, the potential change at the terminal N1, which is the output of the first stage inverter, is more than twice as fast as in the case of the conventional clock driver shown in FIG. But in reality, MOSFET
With the addition of M7 and M8, the PN junction capacitance at the terminal N1 increases, so it is predicted that the speed will only increase by about twice. Also, when the pulse waveform of terminal PI turns on and the pulse waveform of terminal N1 enters a falling transition state,
The dynamic discharge operation of the potential at the terminal N1 due to the g _n of the MOSFET M1 is slowed down by the steady conduction current of the MOSFET M8. This is MOSFET M
7 and M8 do not exist, which means that the fall time of the pulse waveform at the terminal N1 is degraded compared to the case of the conventional circuit configuration shown in FIG. Therefore, the threshold voltage of the next stage B1 circuit is crossed at times t _a ′, t _b ′, and t _c ′. Here, the period T〓′=t _b ′
−
If t _a ′, T〓′=t _c ′−t _b ′, it is improved compared to the conventional circuit operation shown in FIG. 3, and the period T〓′=
It can be set to T〓′. This was achieved by being able to extend the high level period of the pulse waveform at terminal N1 by increasing the rise time and slowing the fall time. if
The potential of the VI bias is too large and the period T〓′>
When T〓′ is reached, if the potential of the VI bias is adjusted to decrease a little, the period T〓′=
The conditions for T〓′ can be obtained. The duty ratio of the drive pulse waveform of terminals P1 and P2 is the same as that of terminals N2 and N3.
It is appropriate to duty-control the output of the first-stage inverter, since it almost adapts to the duty ratio of the pulse waveform. As described above, the B1 circuit and the B2 circuit are constituted by a high-speed bootstrap circuit or a high-speed buffer circuit, and drive MOSFETs M3, M5, M4, and M6 of the push-pull circuit. As mentioned above, since the pulses at the terminals N2 and N3 are complementary pulses, the push-pull circuit dynamically changes its operation with low power consumption.
In other words, when the pulse waveform at terminal N2 rises (the pulse waveform at terminal N3 falls),
MOSFET M4, M5 are on state (MOSFET
M3 and M6 are turned off), the drive pulse at the terminal P1 goes high, and the drive pulse at the terminal P2 goes low. These terminals P1, P2
Since the dynamic change in the output pulse approximately corresponds to the potential change at the terminal N2, the duty ratio of the drive pulse waveform at the terminals P1 and P2 is approximately equal to the duty ratio of the pulse waveform at the terminal N2. Therefore, by setting the potential of the VI bias so that the period T〓'=T〓', it is possible to obtain a duty ratio of 50% for the drive pulse waveforms of the terminals P1 and P2. The control method is to measure the duty ratio while observing the output pulse waveform of the clock driver.
A fine adjustment method using external control is used to keep it within 50.0%.

Next, the high level period of the pulse waveform of terminal N1 is 1
A case where the ratio is 50% or more compared to the period will be explained. This corresponds to a case where the duty ratio of the pulse waveform at the terminal PI of the clock driver is 50% or less, and there is a problem in the logic section (not shown) on the pulse supply side to the terminal PI. In this case, select a low level VI〓 as the input VI bias of the analog inversion circuit, and set the output V1 to a high level VI〓 that is higher than the threshold voltage of MOSFET M7.
Use g _n of MOSFET M7. Since the VI bias is set to a low level VI〓, MOSFET M
8's g _n becomes smaller. Here, when the pulse waveform of the terminal PI transitions to OFF, the pulse waveform of the terminal N1 changes state to a high level. At this time
Even if MOSFET M1 is cut off
Since MOSFET M7 is in the on state, terminal N1
Slows down the rise transition state change of the pulse waveform.
In addition, when the pulse waveform of terminal PI is set to the on state and the pulse waveform of terminal N1 transitions to a low level, g _n of MOSFET M7 is set to the ON state.
g _n to speed up the falling transition state change of the pulse waveform of the terminal N1. Therefore, terminal N
The high level period of the pulse waveform of No. 1 approaches 50%. Other operational changes and control methods are the same as in the first case described above, so their explanations will be omitted.

In this embodiment described above, MOSFET
The beta ratio of the combined circuit of M1, M2, M7, and M8 is maintained such that the low level of the pulse waveform at terminal N1 is below the threshold voltage of the B1 circuit. VI
When the duty ratio of the driving pulse waveforms of terminals P1 and P2 is set to 50% by adjusting the bias only, the sampling pulses for driving the CCD comb filter are mutually controlled as shown in Figure 1b.
As a pulse having a phase difference of 180°, a separately provided pulse generation logic section outputs terminals ID1 and ID in Figure 1a.
2, so the sampling opening time
td ₁ and td ₂ can be made equal. The pulse generation logic section and clock driver are integrated into one chip.
It is integrated into an IC, and its master clock is 21.5MHz.
(6f _sc ). In addition, the sampling pulse width of terminals ID1 and ID2 corresponds to the pulse width of the master clock, and the timing is also synchronized with the master clock, so the phase difference is
It is 180°. Furthermore, when the CCD comb filter is driven by the clock driver of this embodiment shown in FIG. In addition to easily controlling the duty ratio of the drive pulse waveform, you can also control the sampling opening time.
Since td ₁ and td ₂ can be set equally, the performance of the CCD comb filter can be greatly improved.
That is, if the opening time td ₁ = td ₂ , the first
The sampling points at the inputs of channels A and B shown in Figure a are alternately shifted with a phase difference of 180°. At this time, if the deterioration of the non-transfer efficiency is small, the suppression ratio of the CCD comb filter characteristic does not decrease and a value of 40 dB or more can be obtained.

Furthermore, since the pulse waveform can be set so that the sampling point does not shift, gain deterioration does not occur in the high frequency range, and resolution deterioration in the horizontal direction can be avoided. Of course, since the degree of separation between the C signal and the Y signal is large, vertical dot interference and cross color interference are also improved. In this way, in this example
The driving method of the CCD comb filter has great advantages, and its performance can be improved by external adjustment, which greatly contributes to improving yield, which is an important factor in reducing the cost of ICs when they are put into mass production. . In addition, since there are fewer circuit elements added to a conventional clock driver, it does not lead to an increase in the occupied area, and since only a single bias adjustment terminal is added, it does not become a major bottleneck when packaging an IC.

In addition, in this example, MOSFET M7, M
The DC bias of 8 may be applied independently from the outside, or the same effect can be obtained by applying the output V1 of the analog inversion circuit to the gate of MOSFET M8 and directly applying the VI bias to the gate of MOSFET M7. Needless to say. Also,
Neither setting the source terminal of MOSFET M9 to a negative potential nor connecting the drain terminal of MOSFET M10 to a bias power source other than the power supply voltage _VDD does not impair the spirit of the present invention.

According to the CCD comb filter driving method of the present invention, the duty control and DC bias control circuits added to the first stage inverter of the clock driver change the dynamic transition state of the first stage inverter, and the CCD comb filter By matching the sampling opening times of the two-phase pulse that drives the channel section of the filter and the charge presetting pulse between the CCD main channel and the CCD subchannel, the phases of the main and subchannels can be adjusted.
Since ideal alternate sampling is performed with a 180° shift, a decrease in resolution in the horizontal direction is avoided, dot interference and cross color interference in the vertical direction are improved, and the drive method takes full advantage of the original characteristics of the CCD comb filter. This results in the effect that .

[Brief explanation of drawings]

Figure 1a is a diagram showing the configuration of the input/output section of a general CCD comb filter, Figure 1b is a driving waveform diagram of the main terminals in Figure 1a, and Figure 2 is a diagram of the conventional CCD comb filter.
A circuit diagram showing an example of a clock driver for driving a comb filter, FIG. 3 is an operating waveform diagram in FIG. 2, and FIG. 4 is a clock driver of an embodiment of the CCD comb filter driving method of the present invention. circuit diagram,
5 is an operating waveform diagram in FIG. 4, and FIG. 6 is a diagram showing input/output characteristics of the analog inversion circuit in FIG. 4. 11, 11', 11''...n ⁺ diffusion layer, 12...
p-type semiconductor substrate, 13... buffer amplifier, B
1, B2...High-speed bootstrap circuit or high-speed buffer circuit, M1-M10...MOSFET.

Claims (1)

[Claims] 1. In a CCD comb filter driving method that uses a charge preset input method to drive a CCD comb filter that samples alternately every half period between one CCD main channel and two CCD subchannels, two-phase pulses are used. It has two MOSFETs as the first-stage inverter of the drive circuit for driving the CCD channel for supplying power, and a duty control control circuit consisting of two MOSFETs is added to this first-stage inverter, and the MOSFET of the first-stage inverter and duty control circuit for
The MOSFETs are each connected in parallel, and the duty control circuit also has a DC bias control circuit that supplies DC bias to the other MOSFET in a complementary relationship to the DC bias supplied to one MOSFET. is also added, and by adjusting the DC bias supplied to one of the MOSFETs of the DC bias control circuit and the duty control circuit, the sampling opening time of the two-phase pulse and the charge preset pulse can be adjusted to
A method for driving a CCD comb filter, characterized in that the CCD main channel and the CCD subchannel are aligned and the sampling point is shifted by 180°.