JPH0128968B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program control device for preventing program runaway in a microcomputer.

Conventional configurations and their problems Recently, various microcomputers have been devised. All of these operate by repeating the following sequence.

That is, (1) the contents of the memory at the address indicated by the program counter are stored in the instruction register.

(2) The decoder decodes the instruction that is the contents of the instruction register.

(3) Based on the decoding results, various control signals are output from the decoder and executed.

(4) Increment the program counter value by 1.

Therefore, if the program counter malfunctions and indicates the wrong address, or if the contents of the memory are destroyed for some reason, the erroneous instruction will be decoded by the decoder, and the microcomputer will not operate correctly. At this time, in particular, instructions that are not defined as instructions cannot be decoded by the decoder, and thereafter the microcomputer stops operating at all and enters a so-called deadlock state.

OBJECTS OF THE INVENTION In view of the above drawbacks, an object of the present invention is to control a program to avoid a deadlock state even when an undefined instruction is input to an instruction register in order to improve the execution speed of instructions. It provides equipment.

Structure of the Invention In order to achieve the above object, the present invention includes a memory that stores instructions, a program counter that provides an address signal to the memory, a register that sequentially holds the contents of the memory, and a register that is connected to the register output. an instruction register that holds an instruction being executed; a register control circuit that controls writing from the memory to the register and incrementing the program counter; and outputs a status signal that becomes active when the register is not empty;
a programmable logic array that decodes the instruction register output and the state signal and outputs a decodable signal that becomes active when decodable; and a programmable logic array that receives the state signal and the decodable signal and makes the decodable signal inactive. and a deadlock detection circuit that detects that the state signal is active and outputs a deadlock generation signal, and the deadlock detection circuit detects that the state signal is active and outputs a deadlock generation signal, and the deadlock detection circuit detects that the state signal is active even though an instruction is present in the register. The programmable logic array first detects a state in which the instruction is not decoded, and as a result, presets the program counter to a predetermined value and starts accessing the memory again, thereby decoding undefined instructions into the programmable logic array. This also prevents the program control device from becoming deadlocked when input to the array.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

The figure shows the configuration of a program control device in an embodiment of the present invention.

In the figure, 1 is a program counter that is normally incremented by a control signal a that is the output of a Q register control circuit, which will be described later.
Presetting can also be performed using control signal b, which is the output of PLA (Programmable Logic Array). A memory 2 stores instructions, and outputs the contents of the address indicated by the program counter 1. Reference numeral 3 denotes a FIFO-type Q register consisting of a plurality of registers for temporarily storing the contents of memory 2. 4 is a Q register control circuit that outputs a control signal a and a status signal d based on control signals b and c, which are output signals of PLA, which will be described later;
A control signal a is output so that each register in the Q register always stores a new instruction temporarily, and when at least one of the registers composing the Q register 3 contains an instruction that has not yet been output to the instruction register described below. It outputs a status signal d which is a logic 1 only when the signal is turned on, and a logic 0 otherwise. Reference numeral 5 denotes an instruction register which receives the output of the Q register 3 as an input and holds an instruction while the instruction is being executed.
6 is a PLA which inputs the output of the instruction register 5, the status signal d, and the output of the deadlock detection circuit described below, decodes these, and outputs various control signals.
The program is programmed to decode the contents of the instruction register 5 only when the status signal d is logic 1. However, the output signal of the deadlock detection circuit, which will be described later, is decoded completely separately from other input signals of the PLA 4, and it is programmed to output the control signal b when it becomes logic 1. 7 inputs the status signal d and the control signal e,
This is a deadlock detection circuit which detects a state in which the state signal d is logic 1 and the control signal e is logic 0, and at this time, the output connected to the input of the PLA 6 becomes logic 1.

Note that the above-mentioned c is a control signal output from the PLA 6, which becomes logic 1 when one instruction has been executed. Notifies that one of the contents of register 3 has been used. Further, b is a control signal output from the PLA 6, which presets the program counter 1 to a predetermined value and resets the state of the Q register control circuit 4 when the signal is at logic 1. e is
This is a control signal obtained by calculating the logical sum of all decode lines of PLA 6. Therefore, when an undefined instruction is input to the instruction register 5, and the contents of the instruction register 5 are defined instructions, It is a logic 0 only when the state signal d is a logic 0.

The operation of the program control device configured as described above will be explained below. First, in a normal state, the Q register control circuit 4 controls the Q register 3 and the program counter 1 using the control signal a so that the Q register 3 is always filled with new instructions. That is, the contents of memory 2 indicated by program counter 1 are loaded into the Q register by control signal a, program counter 1 is incremented, and memory 2 at the next address is loaded.
access.

The instructions stored in the Q register 3 in this manner are taken into the instruction register 5 by the control signal c. Since the control signal c is also output to the Q register control circuit 4, the control signal a becomes logic 1 at this time, and the above-described operation is performed.

The instruction taken into instruction register 5 is
It is decoded by the PLA 6, and then the instruction is executed based on the decoded result. Then, in the last cycle of instruction execution, the control signal c is outputted again, and the next new instruction is inputted to the instruction register 5 from the Q register 3. However, when a new instruction does not yet exist in Q register 3, this instruction is not decoded and executed. This is because, as mentioned above, PLA 6 is programmed to decode the contents of instruction register 5 only when status signal d is logic 1. Then, as described above, the Q register control circuit 4 operates to take in a new instruction into the Q register 3. (Hereinafter, this state will be referred to as "Q wait") When a new instruction is taken into the Q register 3, the state signal d becomes logic 1.
Decoding starts with PLA6. On the other hand, when waiting for Q, the control signal e becomes a logic 0, but the state signal d also becomes a logic 0, so the output of the deadlock detection circuit 7 becomes a logic 0.

Next, because program counter 1 malfunctions or the contents of memory 2 are destroyed,
Consider a case where an undefined instruction is input to the instruction register 5. At this time, since the instruction is not decoded by the PLA 6, all output signals of the PLA 6 become logic 0 as in the case of waiting for Q described above. However, this time, unlike the Q wait state, the PLA 6 does not decode even after a period of time has elapsed, and enters a so-called deadlock state. However, at this time, a state occurs in which the state signal d is logic 1 and the control signal e is logic 0. Then, the del lock detection circuit 7 operates and makes its output signal logic 1.
Therefore, this state is decoded by PLA6,
The control signal b becomes logic 1, and the program counter 1 is loaded with preset data. Subsequent processing is performed by setting this preset data as the starting address of the program for post-deadlock processing. Since the control signal b is also connected to the Q register control circuit 4, the state at the time of deadlock is reset and fetching of instructions for post-delock processing is started.

As described above, according to this embodiment, even when an undefined command is input to the PLA 6, a deadlock state does not occur, and this can be quickly avoided.

Effects of the Invention As described above, the present invention has a memory that stores instructions, a program counter that provides an address signal to the memory, a register that sequentially holds the contents of the memory, and a register that is connected to the register output during execution. an instruction register for holding an instruction; a register control circuit for controlling writing from the memory to the register and incrementing the program counter; and outputting a status signal that becomes active when the register is not empty; a programmable logic array that decodes a register output and the state signal and outputs a decodable signal that becomes active when decodable; a programmable logic array that receives the state signal and the decodable signal as input; By providing a deadlock detection circuit that detects that the state signal is active and outputs a deadlock generation signal, it is possible to prevent the program counter from malfunctioning or the contents of the memory to be destroyed and an undefined instruction to be written in the programmable state. Even when input to the logic array, a deadlock state does not occur, which can be avoided, and the reliability of the microcomputer can be improved. In addition, the hardware required to improve this reliability is a deadlock detection circuit, etc. compared to a conventional program control device with a Q register, and the hardware required has not increased significantly. Value is great.

[Brief explanation of drawings]

The figure is a block diagram of a program control device according to an embodiment of the present invention. 1...Program counter, 2...Memory, 3
...Q register, 4...Q register control circuit, 5
...Instruction register, 6...PLA, 7...Deadlock detection circuit.

Claims (1)

[Claims] 1: a memory that stores instructions; a program counter that provides an address signal to the memory; a register that sequentially holds the contents of the memory; an instruction register that is connected to the register output and holds the instruction being executed; a register control circuit that controls writing to the register from memory and incrementing of the program counter and outputs a status signal that becomes active when the register is not empty; and a register control circuit that decodes the instruction register output and the status signal; A programmable logic array that outputs a decodable signal that becomes active when decodable, and receives the state signal and the decodable signal as input, and detects that the decodable signal is inactive and the state signal is active. 1. A program control device comprising: a deadlock detection circuit that outputs a deadlock generation signal.