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JPH0129323B2 - - Google Patents
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JPH0129323B2 - - Google Patents

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Publication number
JPH0129323B2
JPH0129323B2 JP57202325A JP20232582A JPH0129323B2 JP H0129323 B2 JPH0129323 B2 JP H0129323B2 JP 57202325 A JP57202325 A JP 57202325A JP 20232582 A JP20232582 A JP 20232582A JP H0129323 B2 JPH0129323 B2 JP H0129323B2
Authority
JP
Japan
Prior art keywords
resistor
capacitor
circuit
input terminal
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57202325A
Other languages
Japanese (ja)
Other versions
JPS5991720A (en
Inventor
Takeo Sakurai
Osamu Hatori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP20232582A priority Critical patent/JPS5991720A/en
Publication of JPS5991720A publication Critical patent/JPS5991720A/en
Publication of JPH0129323B2 publication Critical patent/JPH0129323B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/04Frequency selective two-port networks
    • H03H11/10Frequency selective two-port networks using negative impedance converters

Landscapes

  • Networks Using Active Elements (AREA)

Description

【発明の詳細な説明】 技術分野 本発明は周波数依存負性抵抗即ちFDNR
(Frequency Dependent Negative Resistance)
回路を使用したローパスフイルタに関し、更に詳
細には、デジタル・アナログコンバータに於いて
変換時に発生する特定周波数帯のノイズ等を効率
良く遮断することが可能なアクテイブフイルタに
関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to frequency dependent negative resistance or FDNR.
(Frequency Dependent Negative Resistance)
The present invention relates to a low-pass filter using a circuit, and more specifically to an active filter that can efficiently block noise in a specific frequency band generated during conversion in a digital-to-analog converter.

従来技術 特定周波数帯のノイズを効率良く遮断するため
に、GIC(Generalized Impedance Converter)
回路の一つであるFDNR回路を含む従来のアク
テイブフイルタは、第1図に示す如く構成されて
いる。即ち、信号伝送ライン1と接地された共通
ライン(グランド)との間に順次に接続された第
1の抵抗R1と第1のコンデンサC1と第2の抵抗
R2と第3の抵抗R3と第4の抵抗R4と第2のコン
デンサC2とから成る直列回路と、一方の入力端
子(非反転入力端子)が第1の抵抗R1と第1の
コンデンサC1との間に接続され、他方入力端子
(反転入力端子)が第2の抵抗R2と第3の抵抗R3
との間に接続され、出力端子が第3の抵抗R3
第4の抵抗R4との間に接続された第1の演算増
幅器A1と、一方の入力端子(非反転入力端子)
が第4の抵抗R4と第2のコンデンサC2との間に
接続され、他方の入力端子(反転入力端子)が第
2の抵抗R2と第3の抵抗R3との間に接続され、
出力端子が第1のコンデンサC1と第2の抵抗R2
との間に接続された第2の演算増幅器A2からな
る周波数依存負性抵抗回路即ちFDNR回路2a
を含み、更に、入力端子3と出力端子4との間
に、第5、第6、第7、第8、第9、及び第10の
抵抗R5,R6,R7,R8,R9,R10、第3及び第4
のコンデンサC3,C4、第3の演算増幅器A3を含
む。尚、互いに並列接続された第3のコンデンサ
C3と第5の抵抗R5とはライン1に直列に接続さ
れ、また第6及び第7の抵抗R6,R7もライン1
に直列接続されている。これに対して、第4のコ
ンデンサC4と第8の抵抗R8とはライン1とグラ
ンドとの間に並列接続されている。第3の演算増
幅器A3の非反転入力端子は信号伝送ライン1に
接続され、反転入力端子は第10の抵抗R10を介し
て接地され、この出力端子と反転入力端子との間
に第9の抵抗R9が接続されている。
Conventional technology In order to efficiently block noise in specific frequency bands, GIC (Generalized Impedance Converter)
A conventional active filter including an FDNR circuit, which is one of the circuits, is configured as shown in FIG. That is, a first resistor R1 , a first capacitor C1 , and a second resistor are connected in sequence between the signal transmission line 1 and a grounded common line (ground).
R 2 , a third resistor R 3 , a fourth resistor R 4 , and a second capacitor C 2 . The other input terminal ( inverting input terminal) is connected between the second resistor R2 and the third resistor R3.
a first operational amplifier A1 whose output terminal is connected between the third resistor R3 and the fourth resistor R4 , and one input terminal (non-inverting input terminal).
is connected between the fourth resistor R4 and the second capacitor C2 , and the other input terminal (inverting input terminal) is connected between the second resistor R2 and the third resistor R3 . ,
The output terminals are the first capacitor C 1 and the second resistor R 2
A frequency dependent negative resistance circuit, that is, a FDNR circuit 2a , consisting of a second operational amplifier A2 connected between
Further, between the input terminal 3 and the output terminal 4, fifth, sixth, seventh, eighth, ninth, and tenth resistors R 5 , R 6 , R 7 , R 8 , R 9 , R 10 , 3rd and 4th
capacitors C 3 and C 4 and a third operational amplifier A 3 . In addition, the third capacitor connected in parallel with each other
C 3 and the fifth resistor R 5 are connected in series to line 1, and the sixth and seventh resistors R 6 and R 7 are also connected to line 1.
connected in series. On the other hand, a fourth capacitor C 4 and an eighth resistor R 8 are connected in parallel between line 1 and ground. The non-inverting input terminal of the third operational amplifier A 3 is connected to the signal transmission line 1, the inverting input terminal is grounded via the tenth resistor R 10 , and the ninth A resistor R 9 is connected.

各素子の値を例示すると次の通りである。R1
は419Ω、R2及びR3は4000Ω、R4は3434Ω、R5
は200kΩ、R6及びR7は2302Ω、R8は204.6kΩ、
R9は5000Ω、R10は10kΩ、C1〜C4は2200pFであ
る。また、第1〜第3の演算増幅器A1〜A3の正
電源ライン+Vは+15Vの電源に接続され、負の
電源ライン−Vは−15Vの電源に接続され、+V
とグランドとの間に100μFのコンデンサ(図示せ
ず)が接続され、−Vとグランドとの間にも
100μFのコンデンサ(図示せず)が接続されてい
る。
Examples of the values of each element are as follows. R 1
is 419Ω, R 2 and R 3 are 4000Ω, R 4 is 3434Ω, R 5
is 200kΩ, R 6 and R 7 are 2302Ω, R 8 is 204.6kΩ,
R9 is 5000Ω, R10 is 10kΩ, and C1 to C4 are 2200pF. Further, the positive power supply line +V of the first to third operational amplifiers A 1 to A 3 is connected to the +15V power supply, and the negative power supply line -V is connected to the -15V power supply, and the +V
A 100μF capacitor (not shown) is connected between and ground, and also between -V and ground.
A 100μF capacitor (not shown) is connected.

第1図に示すように構成されたフイルタは、
18kHzを遮断周波数とする3次の連立チエビシエ
フ特性のローパスフイルタとして働き、第2図に
示すような周波数−振幅特性が得られる。
The filter configured as shown in FIG.
It functions as a low-pass filter with a third-order simultaneous Tiebishiev characteristic with a cutoff frequency of 18 kHz, and a frequency-amplitude characteristic as shown in FIG. 2 is obtained.

ところが、FDNR回路2aのコンデンサC1
C2のQが低下すると、遮断周波数近傍の通過周
波数帯で入力信号の振幅のレベルダウンが生じ、
これを補正する適当な方法がなかつた。
However, the capacitor C 1 of the FDNR circuit 2a,
When the Q of C 2 decreases, the level of the input signal amplitude decreases in the pass frequency band near the cutoff frequency,
There was no suitable way to correct this.

従来のFDNR回路を含む9次の連立チエビシ
エフ型ローパスフイルタは、第3図に示す如く、
第1図の回路に、3つのFDNR回路2b,2c,
2dを追加し、更に3つの抵抗R15,R16,R17
追加した構成になつている。第3図の回路に於い
て、符号1,2a,3,4,R1〜R10,C1〜C4
A1〜A3で示す部分は第1図で同一付号で示す部
分と実質的に同一であるので、その説明を省略
し、追加した部分について更に説明すると、抵抗
R15,R16,R17は信号ライン1に順次に直列接続
され、第2、第3、及び第4のFDNR回路2b,
2c,2dは抵抗R15,R16,R17の夫々の後段に
てライン1に並列接続されている。第2、第3、
及び第4のFDNR回路2b,2c,2dは第1
のFDNR回路2aと同一回路構成である。第3
図の各FDNR回路2a,2b,2c,2dに於
いて、コンデンサC1,C2,C11,C12,C21,C22
C31,C32は同一の2200pFに夫々設定され、抵抗
R2,R12,R22,R32,R3,R13,R23,R33は同一
の4500Ωに夫々設定され、また抵抗R1は445Ω、
抵抗R11は2700Ω、抵抗R21は3610Ω、抵抗R31
1655Ω、抵抗R4は5880Ω、抵抗R14は4405Ω、抵
抗R24は3830Ω、抵抗R34は4710Ωに夫々設定さ
れている。FDNR回路2a,2b,2c,2d
以外に於けるコンデンサC3,C4は2200pF、抵抗
R5は300kΩ、抵抗R6は5720Ω、抵抗R7は4740
Ω、抵抗R8は325.6kΩ、R9は5kΩ、R10は10kΩ、
R15は7755Ω、R16は6280Ω、R17は6790Ωに夫々
設定されている。また第3図の+Vの電源ライン
は並列コンデンサを介さずに+15Vの電源に接続
され、−Vの電源ラインは並列コンデンサを介さ
ずに−15Vの電源に接続されている。
A 9-order simultaneous Tievishev-type low-pass filter including a conventional FDNR circuit is as shown in Figure 3.
In the circuit of Fig. 1, three FDNR circuits 2b, 2c,
2d and three resistors R 15 , R 16 , and R 17 are added. In the circuit of FIG. 3, the symbols 1, 2a, 3, 4, R 1 to R 10 , C 1 to C 4 ,
The parts indicated by A 1 to A 3 are substantially the same as the parts indicated by the same numbers in Fig. 1, so their explanation will be omitted, and the added parts will be further explained.
R 15 , R 16 , and R 17 are sequentially connected in series to the signal line 1, and the second, third, and fourth FDNR circuits 2b,
2c and 2d are connected in parallel to line 1 after the resistors R 15 , R 16 and R 17 , respectively. 2nd, 3rd,
and the fourth FDNR circuits 2b, 2c, 2d are the first
It has the same circuit configuration as the FDNR circuit 2a. Third
In each FDNR circuit 2a, 2b, 2c, 2d shown in the figure, capacitors C 1 , C 2 , C 11 , C 12 , C 21 , C 22 ,
C 31 and C 32 are set to the same value of 2200 pF, and the resistors
R 2 , R 12 , R 22 , R 32 , R 3 , R 13 , R 23 , and R 33 are each set to the same value of 4500Ω, and the resistor R 1 is set to 445Ω,
Resistor R 11 is 2700Ω, resistor R 21 is 3610Ω, resistor R 31 is
The resistance R 4 is set to 1655Ω, the resistance R 4 is set to 5880Ω, the resistance R 14 is set to 4405Ω, the resistance R 24 is set to 3830Ω, and the resistance R 34 is set to 4710Ω. FDNR circuit 2a, 2b, 2c, 2d
Other capacitors C 3 and C 4 are 2200pF and resistance
R 5 is 300 kΩ, resistor R 6 is 5720 Ω, resistor R 7 is 4740
Ω, resistor R 8 is 325.6kΩ, R 9 is 5kΩ, R 10 is 10kΩ,
R15 is set to 7755Ω, R16 is set to 6280Ω, and R17 is set to 6790Ω. Further, the +V power supply line in FIG. 3 is connected to the +15V power supply without using a parallel capacitor, and the -V power supply line is connected to the -15V power supply without using a parallel capacitor.

第3図に示すように構成された回路は15.84kHz
を遮断周波数とする9次の連立チエビシエフ型ロ
ーパスフイルタとして働き、第4図に示すような
周波数一振幅特性が得られる。ところが、遮断周
波数に於いて0.41dBのレベルダウンが生じ、こ
れを補正する適当な手段がなかつた。
The circuit configured as shown in Figure 3 is 15.84kHz.
It functions as a 9th-order simultaneous Thievishev-type low-pass filter with a cutoff frequency of , and a frequency-amplitude characteristic as shown in FIG. 4 is obtained. However, a level drop of 0.41 dB occurred at the cut-off frequency, and there was no appropriate means to correct this.

発明の目的 そこで、本発明の目的は、遮断周波数近傍の通
過周波数帯のレベルアツプを自在に行うことが可
能なFDNR回路を含むローパスフイルタを提供
することにある。
OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a low-pass filter including an FDNR circuit that can freely increase the level of a pass frequency band near the cutoff frequency.

発明の構成 上記目的を達成するための本発明は、理解を容
易にするために第1の実施例を示す第5図、第7
図、及び第9図の符号を参照して説明すると、信
号伝送ライン1と共通ラインとの間に順次に接続
された第1の抵抗R1と第1のコンデンサC1と第
2の抵抗R2と第3の抵抗R3と第4の抵抗R4と第
2のコンデンサC2とから成る直列回路と、一方
の入力端子が前記第1の抵抗R1と前記第1のコ
ンデンサC1との間に接続され、他方の入力端子
が前記第2の抵抗R2と前記第3の抵抗R3との間
に接続され、出力端子が前記第3の抵抗R3と前
記第4の抵抗R4との間に接続された第1の演算
増幅器A1と、一方の入力端子が前記第4の抵抗
R4と前記第2のコンデンサC2との間に接続され、
他方の入力端子が前記第2の抵抗R2と前記第3
の抵抗R3との間に接続され、出力端子が前記第
1のコンデンサC1と前記第2の抵抗R2との間に
接続された第2の演算増幅器A2と、前記第2の
演算増幅器A2の前記他方入力端子と前記第1の
演算増幅器A1の前記出力端子との間に接続され
たレベル調整用コンデンサCと、から成る周波数
依存負性抵抗回路を含むローパスフイルタに係わ
るものである。
Structure of the Invention The present invention to achieve the above object is as shown in FIGS. 5 and 7 which show a first embodiment for easy understanding.
To explain with reference to the symbols in FIG . 2 , a third resistor R3 , a fourth resistor R4 , and a second capacitor C2 ; one input terminal is connected to the first resistor R1 and the first capacitor C1 ; The other input terminal is connected between the second resistor R2 and the third resistor R3, and the output terminal is connected between the third resistor R3 and the fourth resistor R3. A first operational amplifier A1 connected between the fourth resistor and the fourth resistor
connected between R 4 and the second capacitor C 2 ;
The other input terminal is connected to the second resistor R2 and the third resistor R2 .
a second operational amplifier A 2 whose output terminal is connected between the first capacitor C 1 and the second resistor R 2 ; A low-pass filter including a frequency-dependent negative resistance circuit comprising a level adjustment capacitor C connected between the other input terminal of the amplifier A2 and the output terminal of the first operational amplifier A1 . It is.

作用効果 上記本発明によれば、新たに付加したレベル調
整用コンデンサCが遮断周波数近傍の通過周波数
帯のレベルを上昇させることに寄与し、所望のレ
ベルを得ることが可能になる。従つて特性の良い
フイルタ容易に得ることが可能になる。
Effects According to the present invention, the newly added level adjustment capacitor C contributes to raising the level of the pass frequency band near the cutoff frequency, making it possible to obtain the desired level. Therefore, it becomes possible to easily obtain a filter with good characteristics.

実施例 次に第5図〜第16図を参照して本発明の実施
例について述べる。但し、第5図〜第16図に於
いて第1図〜第4図と共通する部分には同一の符
号を付してその説明を省略する。
Embodiments Next, embodiments of the present invention will be described with reference to FIGS. 5 to 16. However, in FIGS. 5 to 16, parts common to those in FIGS. 1 to 4 are designated by the same reference numerals, and their explanations will be omitted.

第1の実施例(第5図及び第6図) 第5図に示す第1の実施例の3次のローパスフ
イルタは、第1図の回路にレベル調整用コンデン
サCを付加した構成になつている。即ち第1の演
算増幅器A1の出力端子と第2の演算増幅器A2
反転入力端子即ち第2の抵抗R2の下端との間に
コンデンサCを接続した回路構成になつている。
このコンデンサC以外の各回路素子の定数を第1
図と同一とし、コンデンサCの値を12pF、24pF、
47pFに設定すると、第6図(A)(B)(C)に示すような
周波数−振幅特性を得ることが出来る。即ち、遮
断周波数(18kHz)近傍の通過帯域のレベルを上
げることが出来る。尚コンデンサCの容量の増大
につれてレベルが上昇する。
First Embodiment (Figures 5 and 6) The third-order low-pass filter of the first embodiment shown in Figure 5 has a configuration in which a level adjustment capacitor C is added to the circuit in Figure 1. There is. That is, the circuit configuration is such that a capacitor C is connected between the output terminal of the first operational amplifier A1 and the inverting input terminal of the second operational amplifier A2 , that is, the lower end of the second resistor R2 .
The constants of each circuit element other than this capacitor C are
As shown in the figure, the value of capacitor C is 12pF, 24pF,
When set to 47 pF, frequency-amplitude characteristics as shown in FIGS. 6(A), (B), and (C) can be obtained. That is, it is possible to raise the level of the passband near the cutoff frequency (18kHz). Note that as the capacitance of capacitor C increases, the level increases.

第2の実施例(第7図及び第8図) 第7図に示す第2の実施例のローパスフイルタ
は、第1図の回路の第2の演算増幅器A2の反転
入力端子とグランドとの間にレベル調整用抵抗R
を接続し、且つ第1の演算増幅器A1の出力端子
と第2の演算増幅器A2の反転入力端子との間に
レベル調整用コンデンサCを接続した構成になつ
ている。
Second Embodiment (FIGS. 7 and 8) The low-pass filter of the second embodiment shown in FIG. 7 connects the inverting input terminal of the second operational amplifier A2 of the circuit of FIG. Level adjustment resistor R between
and a level adjustment capacitor C is connected between the output terminal of the first operational amplifier A1 and the inverting input terminal of the second operational amplifier A2.

第7図の回路のCとR以外の回路定数を第1図
と同一とし、Cを27pF、Rを330kΩに設定する
と、第8図Aの周波数−振幅特性が得られ、また
Cを47pF、Rを200kΩに設定すると、第8図B
の周波数−振幅特性が得られる。即ち、遮断周波
数近傍のレベルを上昇させることが可能になる。
If the circuit constants other than C and R of the circuit in Fig. 7 are the same as in Fig. 1, and C is set to 27 pF and R to 330 kΩ, the frequency-amplitude characteristic shown in Fig. 8 A is obtained, and C is set to 47 pF, and R to 330 kΩ. When R is set to 200kΩ, Figure 8B
A frequency-amplitude characteristic of is obtained. That is, it becomes possible to increase the level near the cutoff frequency.

第3の実施例(第9図及び第10図) 第9図に示す第3の実施例のローパスフイルタ
は、第3図の回路の第2段目のFDNR回路2b
の第1の演算増幅器A11の出力端子と第2の演算
増幅器A12の反転入力端子との間にコンデンサC
を付加接続した構成になつている。第9図の回路
でCを17pFに設定し、他の回路定数を第3図と
同一に設定すれば、第10図に示す周波数−振幅
特性が得られる。即ち、遮断周波数に於けるレベ
ルダウンを0.15dBに抑えることが出来る。
Third Embodiment (FIGS. 9 and 10) The low-pass filter of the third embodiment shown in FIG. 9 is the second stage FDNR circuit 2b of the circuit in FIG.
A capacitor C is connected between the output terminal of the first operational amplifier A11 and the inverting input terminal of the second operational amplifier A12 .
It has a configuration in which it is additionally connected. In the circuit of FIG. 9, if C is set to 17 pF and other circuit constants are set to be the same as in FIG. 3, the frequency-amplitude characteristics shown in FIG. 10 can be obtained. In other words, the level reduction at the cut-off frequency can be suppressed to 0.15 dB.

第4の実施例(第11図及び第12図) 第11図に示す第4の実施例のローパスフイル
タは、第3図の回路の第2段目のFDNR回路2
bの第2の演算増幅器A12の反転入力端子とグラ
ンドとの間に抵抗Rを付加接続し、更に第1の演
算増幅器A11の出力端子と第2の演算増幅器A12
の反転入力端子との間にコンデンサCを付加接続
した構成になつている。この第11図の回路で抵
抗Rを530kΩ、コンデンサCを12pFに設定し、
他の回路定数を第3図と同一に設定すれば、第1
2図に示す周波数−振幅特性が得られ、遮断周波
数に於けるレベルダウンを0.15dBにすることが
出来る。
Fourth embodiment (FIGS. 11 and 12) The low-pass filter of the fourth embodiment shown in FIG. 11 is the second stage FDNR circuit 2 of the circuit in FIG.
A resistor R is additionally connected between the inverting input terminal of the second operational amplifier A 12 in b and the ground, and the output terminal of the first operational amplifier A 11 and the second operational amplifier A 12 are further connected.
The configuration is such that a capacitor C is additionally connected between the inverting input terminal and the inverting input terminal of the inverter. In the circuit shown in Figure 11, the resistor R is set to 530kΩ, the capacitor C is set to 12pF,
If the other circuit constants are set the same as in Figure 3, the first
The frequency-amplitude characteristics shown in Figure 2 are obtained, and the level down at the cut-off frequency can be reduced to 0.15 dB.

変形例 以上本発明は実施例について述べたが、本発明
はこれに限定されるものではなく、更に変形可能
なものである。例えば、3次又は9次以外のロー
パスフイルタにも勿論適用可能である。複数の
FDNR回路2a,2b,2c,2dを有する場
合には、第2段の回路2b以外の回路にコンデン
サCを付加接続してもよいし、複数段のFDNR
回路にコンデンサCを接続してもよい。
Modifications Although the present invention has been described in terms of embodiments, the present invention is not limited to these examples and can be further modified. For example, it is of course applicable to low-pass filters other than 3rd order or 9th order. plural
In the case of having FDNR circuits 2a, 2b, 2c, and 2d, a capacitor C may be additionally connected to a circuit other than the second stage circuit 2b, or a plurality of FDNR circuits may be connected.
A capacitor C may be connected to the circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のFDNR回路を含むローパスフ
イルタを示す回路図、第2図は第1図の回路の周
波数−振幅特性図、第3図は従来の9次のローパ
スフイルタを示す回路図、第4図は第3図の回路
の周波数−振幅特性図、第5図は本発明の第1の
実施例のローパスフイルタを示す回路図、第6図
は第5図の回路の周波数−振幅特性図、第7図は
本発明の第2の実施例のローパスフイルタを示す
回路図、第8図は第7図の回路の周波数−振幅特
性図、第9図は本発明の第3の実施例のローパス
フイルタを示す回路図、第10図は第9図の回路
の周波数−振幅特性図、第11図は本発明の第4
の実施例のローパスフイルタを示す回路図、第1
2図は第11図の回路の周波数−振幅特性図であ
る。 1……ライン、2a,2b,2c,2d……
FDNR回路、R1〜R10……抵抗、C1〜C4……コン
デンサ、A1〜A3……演算増幅器、R……レベル
調整用抵抗、C……レベル調整用コンデンサ。
Fig. 1 is a circuit diagram showing a conventional low-pass filter including an FDNR circuit, Fig. 2 is a frequency-amplitude characteristic diagram of the circuit in Fig. 1, Fig. 3 is a circuit diagram showing a conventional 9th-order low-pass filter, 4 is a frequency-amplitude characteristic diagram of the circuit in FIG. 3, FIG. 5 is a circuit diagram showing the low-pass filter of the first embodiment of the present invention, and FIG. 6 is a frequency-amplitude characteristic diagram of the circuit in FIG. 5. , FIG. 7 is a circuit diagram showing a low-pass filter according to a second embodiment of the present invention, FIG. 8 is a frequency-amplitude characteristic diagram of the circuit of FIG. 7, and FIG. 9 is a diagram showing a low-pass filter according to a third embodiment of the present invention. A circuit diagram showing a low-pass filter, FIG. 10 is a frequency-amplitude characteristic diagram of the circuit of FIG. 9, and FIG. 11 is a diagram of the fourth circuit of the present invention.
A circuit diagram showing a low-pass filter according to an embodiment of
FIG. 2 is a frequency-amplitude characteristic diagram of the circuit of FIG. 11. 1... line, 2a, 2b, 2c, 2d...
FDNR circuit, R1 to R10 ...resistor, C1 to C4 ...capacitor, A1 to A3 ...operational amplifier, R...level adjustment resistor, C...level adjustment capacitor.

Claims (1)

【特許請求の範囲】 1 信号伝送ライン1と共通ラインとの間に順次
に接続された第1の抵抗R1と第1のコンデンサ
C1と第2の抵抗R2と第3の抵抗R3と第4の抵抗
R4と第2コンデンサC2とから成る直列回路と、 一方の入力端子が前記第1の抵抗R1と前記第
1のコンデンサC1との間に接続され、他方の入
力端子が前記第2の抵抗R2と前記第3の抵抗R3
との間に接続され、出力端子が前記第3の抵抗
R3と前記第4の抵抗R4との間に接続された第1
の演算増幅器A1と、 一方の入力端子が前記第4の抵抗R4と前記第
2のコンデンサC2との間に接続され、他方の入
力端子が前記第2の抵抗R2と前記第3の抵抗R3
との間に接続され、出力端子が前記第1のコンデ
ンサC1と前記第2の抵抗R2との間に接続された
第2の演算増幅器A2と、 前記第2の演算増幅器A2の前記他方入力端子
と前記第1の演算増幅器A1の前記出力端子との
間に接続されたレベル調整用コンデンサCと、 から成る周波数依存負性抵抗回路を含むローパス
フイルタ。
[Claims] 1. A first resistor R 1 and a first capacitor connected in sequence between the signal transmission line 1 and the common line.
C 1 and the second resistor R 2 and the third resistor R 3 and the fourth resistor
R4 and a second capacitor C2 , one input terminal is connected between the first resistor R1 and the first capacitor C1 , and the other input terminal is connected to the second capacitor C2. resistance R 2 and said third resistance R 3
is connected between the third resistor and the output terminal is connected between the third resistor and
A first resistor connected between R 3 and the fourth resistor R 4
operational amplifier A1 , one input terminal connected between the fourth resistor R4 and the second capacitor C2 , and the other input terminal connected between the second resistor R2 and the third capacitor C2 ; Resistance of R 3
a second operational amplifier A2 whose output terminal is connected between the first capacitor C1 and the second resistor R2 ; a level adjustment capacitor C connected between the other input terminal and the output terminal of the first operational amplifier A1 ; and a low-pass filter including a frequency-dependent negative resistance circuit.
JP20232582A 1982-11-18 1982-11-18 Frequency dependant negative resistance type low pass filter Granted JPS5991720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20232582A JPS5991720A (en) 1982-11-18 1982-11-18 Frequency dependant negative resistance type low pass filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20232582A JPS5991720A (en) 1982-11-18 1982-11-18 Frequency dependant negative resistance type low pass filter

Publications (2)

Publication Number Publication Date
JPS5991720A JPS5991720A (en) 1984-05-26
JPH0129323B2 true JPH0129323B2 (en) 1989-06-09

Family

ID=16455677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20232582A Granted JPS5991720A (en) 1982-11-18 1982-11-18 Frequency dependant negative resistance type low pass filter

Country Status (1)

Country Link
JP (1) JPS5991720A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56119521A (en) * 1980-02-25 1981-09-19 Murata Mfg Co Ltd Fdnr system low-pass filter

Also Published As

Publication number Publication date
JPS5991720A (en) 1984-05-26

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