JPH0129476B2 - - Google Patents

Description

Detailed Description of the Invention <Technical Field> The present invention relates to a defect compensation circuit for a solid-state image sensor.

<Prior Art> In a solid-state imaging device using a CCD or the like, it is difficult to manufacture a defect-free device, and a normal video signal may not be obtained locally due to crystal defects or the like. In order to deal with such inconveniences, attempts have been made to substantially increase the yield of solid-state imaging devices by electrically compensating for the defects at the expense of partially sacrificing resolution.

FIG. 1 is a block diagram showing a conventional solid-state imaging device in which defects associated with the solid-state imaging device are electrically compensated. In the figure, 1 is a solid-state image sensor, 2 is a video amplifier that amplifies the video signal from element 1, 3 is a defect compensation circuit, 4 is a vertical counter that counts horizontal scanning lines, and 5 counts the horizontal position of pixels. A horizontal counter, 6 a digital memory for storing position information of each pixel of the solid-state image sensor 1, and 7 a pulse generating circuit for supplying clock pulses to each of the above-mentioned circuits.

Here, the memory 6 stores information indicating the presence or absence of defects at addresses corresponding to each pixel of the solid-state image sensor 1 on a one-to-one basis, and each Address information corresponding to the pixel is read out and supplied to the defect compensation circuit 3 to compensate the video signal output from the amplifier 2. The video signals of neighboring pixels are used for compensation, and although the resolution is sacrificed to some extent, it is possible to obtain a video signal that compensates for defects, and even a solid-state image sensor with some defects can be used as a defect-free device. It can be used virtually unchanged.

However, if the memory 6 were to store defect information in one-to-one correspondence with each pixel, the memory 6 would have a huge capacity (for example, 400 pixels horizontally and 400 pixels vertically).
The disadvantage was that for a pixel count of 500, approximately 200k bits were required.

On the other hand, a defect correction circuit has also been proposed in which the memory capacity is reduced by storing only the positional information of the defective part in the memory without storing the positional information of the defective part. However, although this method can significantly reduce the memory capacity, it does not necessarily have the advantage of increasing the number of matching circuits for comparing addresses and complicating peripheral circuits.

<Object of the Invention> The present invention has been made in view of the problems of the conventional solid-state imaging device described above, and it allocates a memory for storing position information for each horizontal line. By storing fictitious position information, a defect compensation circuit with an appropriate memory capacity and simple peripheral circuitry is provided.

<Embodiment> FIG. 2 shows an embodiment of the present invention, and is a block diagram of a defect compensation circuit when a CCD is used as the solid-state image sensor.

In the figure, a video signal output from a solid-state image sensor 11 that may include a defective portion is amplified by a video amplifier 12, and then amplified by an analog switch 13.
given to the terminal. The output of the video amplifier 12 is also once input to an analog delay element 14 whose delay time is set to, for example, one horizontal period, and after being delayed, it is applied to the B terminal of the analog switch 13. The switch 13 switches either the A or B terminal to derive a video output. The solid-state image sensor 11 and delay element 14 are driven by a clock φ output from a timing generation circuit 15, which generates various pulse signals FI, VD, HD, which will be described later. The operations of the counter 16, second counter 17, memory 18, and matching circuit 19 are controlled. That is, VD and HD outputted from the timing generation circuit 15 are vertical and horizontal synchronizing pulses, respectively, and FI is a signal that distinguishes fields (for example, logic "1" in odd-numbered fields).
Logic "0" signal in even field). The FI signal and VD signal are applied to the clear terminal of the first counter 16 via the AND gate 20,
The HD signal is sent to the first counter 16 and the second counter 1
7 is given. Therefore, the counter 16 is 1
It is cleared by the VD signal only once per frame, and is counted up sequentially by the HD signal.
The output of the counter 16 is position information (vertical address) indicating which horizontal line is currently being output.
shows. The number of stages of this first counter 16 is NTSC
When handling standard video signals, 10 bits (1024 bits) is sufficient. On the other hand, the second counter 17
is cleared by the HD signal, and is sequentially counted up by the CCD transfer clock φ until the next HD signal. Therefore, the output of the second counter 17 indicates positional information (horizontal address) indicating which pixel signal is currently being output in a certain horizontal line. The number of stages required for this second counter 17 is determined by the horizontal resolution of the CCD, and is usually 9 bits (512 pixels).
Good to have.

Now, the address of the memory 18 is the first counter 16.
A different address is given to each horizontal line of the CCD solid-state image sensor 11 to be accessed. In this way, the positional information (horizontal direction address) where a defect exists in the corresponding horizontal line of the image sensor 11 is stored in the address given for each horizontal line. Since the address is set for each horizontal line in the memory 18 as described above, it is possible to deal with cases where there is no defect in the horizontal line or cases where there is a defect at one location.

However, in an actual CCD image sensor, it is rare for a horizontal line to contain defects in two or more places, and as in this embodiment, the memory 18 stores information about a maximum of one defect in each horizontal line in the horizontal direction of that pixel. If the position information of the device can be stored, defects can be compensated for and the device can be put to practical use.

The memory 18 sequentially reads the positional information of defects on each horizontal line in response to the address signal, and provides the information to the matching circuit 19. The other input terminal of the coincidence circuit 19 is supplied with the count value of a second counter 17 that sequentially counts the pixel positions in the horizontal line by the clock φ, and is compared with the position information read out from the memory 18. is executed, and a control signal is given to the analog switch 13 with the output signal DD of the coincidence circuit 19 becoming active.

In this embodiment, only when the DD signal is active, the analog switch 13 is switched from the A side to the B side to switch to the video signal that has passed through the analog delay element 14 and output it. Here, the analog delay element 14 is, for example, 1H (in the case of a monochrome solid-state image sensor) or 2H (in the case of a color solid-state image sensor).
This is a CCD delay line, and the video signal is replaced using output signals from surrounding pixels that have a high correlation with the defective pixel. Incidentally, for a horizontal line in which no defective pixel exists, a non-existent imaginary horizontal direction address is stored in the corresponding memory. For example, when there are 400 pixels in the horizontal direction, 1 to 190H of the 9-bit (φ to _1FFH ) addresses are taken to correspond to real pixels, and _{1FFH is} taken to be a fictitious address. By choosing the address above,
In horizontal lines where no defects exist, the output of the memory 18 and the output of the counter 17 will never match, and therefore the output of the matching circuit 19 will never become active, so no defect compensation is performed.

For example, the above embodiment shows a case where 9 bits are required as the output line from the memory 18, so 8 x 2 k bits or 8 x
If configured using EPROM with a capacity of 4k bits, multiple memories will be required. Therefore, an embodiment that can be constructed using one 8-bit wide memory will be described with reference to FIG. That is, a 2-byte memory is used to store one horizontal address of a defective pixel, and instead of the first counter 16 and memory 18 in the embodiment shown in FIG. 2, a memory as shown in FIG. 3 is used. 3-stage mono multi circuit 21, 22, 23,
A circuit configured using a counter 24, a memory 25, a latch 26, etc. is inserted, and the outputs of the memory 25 and latch 26 are connected to the coincidence circuit 1 in the same manner as in the previous embodiment.
Configure by entering one of 9. FIG. 4 is a time chart for explaining the operation of the circuit.

In FIGS. 3 and 4, a signal HD2 having two pulse trains is formed using three stages of mono multi-circuits 21, 22, and 23 with the HD signal as a reference. This signal HD2 causes the counter 24 to
One pulse counts up twice. signal
The contents of memory 25 corresponding to the counter output changed by the first pulse of HD2 are held in latch 26. Therefore, the number of counter stages required is 11.
The memory capacity may be 8 x 2 ¹¹ bits, that is, 8 x 2k bits. Furthermore, since the output of the memory only needs to be determined within the horizontal retrace period, a low-speed memory element can be used. Although this embodiment shows a method of comparing the memory output and the counter output using a matching circuit, it is of course also possible to preset the memory output in the counter and perform defect compensation using the counter's carry output. .

<Effects> As described above, according to the present invention, memory is allocated for each horizontal line to store horizontal position information of defective pixels or non-existent imaginary position information for horizontal lines where no defects exist. By storing the following, it is possible to provide an economical defect compensation circuit for a solid-state image sensor, which can be constructed with only one easily available and inexpensive memory element and a simple peripheral circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional defect compensation circuit for a solid-state image sensor, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a main part block diagram showing another embodiment of the present invention. , FIG. 4 is a time chart for explaining the operation of the other embodiment shown in FIG. 11: CCD image sensor, 13: analog switch, 14: analog delay element, 15: timing generation circuit, 16, 17: counter, 18: memory, 19: coincidence circuit.

Claims (1)

[Scope of Claims] 1. A solid-state image sensing device having a plurality of image sensing pixels arranged in an array, and a memory for storing positional information indicating a defective location of the solid-state image sensing device; A defect compensation circuit that replaces a signal of a defective pixel of the solid-state image sensor with a signal of another pixel that has a high correlation with the defective pixel based on the above-mentioned structure includes a circuit that forms a memory address signal in units of horizontal lines; a memory for storing encoded horizontal position information regarding defective pixels included in a horizontal line at an address set by the memory address signal forming circuit; A defect compensation circuit for a solid-state image sensor, characterized in that a specific code not included in position information is stored.