JPH0131705B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention provides a gate region having a divided structure.
It relates to a MOS type integrated circuit including a MOS type transistor.

[Prior art]

In a MOS type integrated circuit, the current I _DS flowing between the drain and the source is proportional to the value obtained by dividing the gate width by the gate length if the gate voltage V _GS and the drain-source voltage V _DS are constant.

Conventionally, when considering the accuracy of the relative ratio between transistors with the same gate length and different gate widths, the structure of the gate region of a MOS type integrated circuit is a single transistor with the required gate length and gate width. It consists of one gate area.

As an example, FIG. 1 shows a plan view of a mask pattern showing the structure of a gate region of a conventional MOS integrated circuit including three MOS transistors.

Here, in FIG. 1, the gate regions 4, 5, and 6 of each transistor have the same gate length and gate widths of 10 μm, 15 μm, and 25 μm, respectively.
The configuration is such that a _current having a relative ratio of 1:1.5:2.5, that is, an integer ratio of 2:3:5, flows through the drain output wirings 1, 2, and 3 due to a certain arbitrary gate voltage VGS. In addition, in Figure 1, 7
8 is a source power supply wiring, 8 is a source region, 9 is a drain region, and 10 is an electrode lead-out portion.

However, in this structure, when the oxide film on the top surface of the semiconductor substrate is selectively removed in the gate oxidation process, when the gate width is reduced by, for example, 1 μm due to variations in the etching of the oxide film, the effective gate width is 9 μm. , 14 μm, and 24 μm, and the relative ratio between the transistors becomes 1:1.6:2.7, which has the disadvantage that the initial relative ratio of 1:1.5:2.5 changes.

This is one obstacle in realizing a MOS type integrated circuit having analog characteristics that often handles proportional current.

[Purpose of the invention]

An object of the present invention is to combine transistors having gate regions formed by arranging and connecting MOS transistors in parallel in accordance with a predetermined integer ratio, each having a reference gate region having a constant gate length and a reference gate width. Therefore, it is an object of the present invention to provide a MOS type integrated circuit which can eliminate the above-mentioned drawbacks and improve the accuracy of the relative ratio between transistors having different gate widths.

[Structure of the invention]

The MOS integrated circuit of the present invention includes a plurality of MOS devices having the same gate length and gate widths in an integer ratio relationship.
In MOS type integrated circuits including type transistors,
Each of the plurality of MOS type transistors has a gate region formed by arranging and connecting reference gate regions in parallel, each having a gate width divided by an integer corresponding to the integer ratio relationship.

[Description of Examples]

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 2 shows a plan view of a mask pattern according to an embodiment of the present invention. This embodiment is made in correspondence with the conventional example shown in FIG. 1, and consists of three MOS type transistors. The gate regions 14, 15, and 16 of each transistor have the same gate length and gate width of 2:1, similar to that shown in FIG.
10μm, 15μm, 25μm with an integer ratio of 3:5
It is becoming.

However, each gate region in this embodiment has a reference gate region 21 whose gate width is 5 μm, which is an integer fraction corresponding to the above-mentioned integer ratio relationship, and the gate region 14 is a reference gate region 21.
1 is two, and the gate region 15 is the reference gate region 2.
1 and 3, the gate region section 16 has five reference gate regions 21 arranged in parallel while maintaining the distance between the gate regions and connected by a gate wiring 22, and each drain current is connected to the drain output wiring 11,
12 and 13. In addition, in FIG. 2, 17 is the source power supply wiring, 1
8 is a source region, 19 is a drain region, and 20 is an electrode extraction portion.

In this example, if the gate width is reduced by 1 μm due to variations in the etching of the oxide film, the effective gate width of the gate region of each transistor is 8 μm (4 μm × 2), 12 μm (4 μm × 3),
20 μm (4 μm x 5), and the relative ratio between transistors of 1:1.5:2.5 remains unchanged, so the drain - flowing to drain output wiring 11, 12, 13
The current ratio between the respective transistors of the source-to-source current _IDS can also sufficiently obtain a value of 1:1.5:2.5.

Note that although the explanation so far has been made for the case of three transistors with an integer ratio of gate regions of 2:3:5 (relative ratio of 1:1.5:2.5),
It goes without saying that the present invention is not limited to this, and can be applied to any integer ratio relationship.

Furthermore, although the transistors are of MOS type, it goes without saying that more generally insulated gate type (MIS type) transistors may be used.

〔Effect of the invention〕

As explained in detail above, the MOS integrated circuit of the present invention has a configuration in which the gate regions of each transistor are connected in parallel in a number corresponding to a predetermined integer ratio, with reference gate regions each having a constant gate length and a reference gate width. Therefore, unlike the conventional etching process, the relative ratio of drain currents between transistors does not change, which has the effect of improving the accuracy of the relative ratio between transistors.
It is particularly suitable for linear circuits.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a mask pattern of an example of a conventional MOS type integrated circuit, and FIG. 2 is a plan view showing a mask pattern of an embodiment of the present invention. 1, 2, 3, 11, 12, 13...Drain output wiring, 4, 5, 6, 14, 15, 16...Gate region, 7, 17...Source power supply wiring, 8, 18
...Source region, 9, 19...Drain region, 1
0, 20... Electrode extraction portion, 21... Reference gate region, 22... Gate wiring.

Claims (1)

[Claims] 1. In a MOS integrated circuit including a plurality of MOS transistors having the same gate length and gate widths in an integer ratio relationship, each of the MOS transistors has a gate width that is an integer fraction corresponding to the integer ratio relationship. 1. A MOS integrated circuit characterized by having a gate region formed by connecting reference gate regions arranged in parallel.