JPH0131751B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a charge transfer device and a method for driving the same, and more particularly to a charge transfer device used in a sensor such as a facsimile device and a method for driving the same. Charge transfer devices such as CCDs (Charge Coupled Devices) are being rapidly developed as sensors for solid-state imaging devices or facsimile devices as miniaturization technology advances. An important issue in such devices is how to increase the resolution of the captured images. In order to increase this resolution, it is important to make the area occupied by each picture element as small as possible, and to transfer the charges accumulated in the photoelectric conversion part that forms the picture element to the output terminal as efficiently as possible. So far, we have not necessarily achieved sufficient results. Conventionally, a typical charge transfer device of this type uses a two-phase CCD and has a configuration as shown in the block diagram shown in FIG. For convenience of explanation, the figure shows a case where there are six photoelectric conversion units, and details of input/output units, power supplies, etc. are omitted. Q ₁ to Q ₆ are photoelectric conversion units, and on both sides there are first shift registers 1 each consisting of six charge storage units S ₁₁ to S ₁₆ .
A pair of shift registers of the second shift register 2 consisting of S ₂₁ to _{S 26} are arranged, and six transfer gates G ₁ to _{G 6} are connected to the first shift register 1 between the photoelectric conversion section and the charge storage section. and the second shift register 2, and are supplied with clock signal voltages φ ₁ , φ ₂ and transfer gate voltage φ _G as shown in the figure. The voltages φ ₁ , φ ₂ , and φ _G are (+) pulse voltages that are applied to each part according to the time chart shown in FIG. 2. (The figure shows the case where the semiconductor substrate is P type.) As a result, the charges accumulated in each photoelectric conversion unit Q ₁ to Q ₆ between t ₁ and _{t 2} are transferred to each transfer gate G ₁ to G ₆ , and are transferred and accumulated to charge storage units S ₁₁ , S ₂₂ , S ₁₃ , S ₂₄ , S ₁₅ , and S ₂₆ , respectively. Next, between _t2 and _t3 , the charges accumulated in the charge accumulation sections are transferred to the respective adjacent charge accumulation sections. As a result of sequentially repeating this process, the charges accumulated in Q ₁ to Q ₆ can be taken out alternately from the output section 3 of the first shift register and the output section 4 of the second shift register. In this conventional charge transfer device, as described above, one photoconversion section is necessarily arranged in correspondence with one charge storage section, and transfer gates must be provided alternately for both registers. Therefore, arranging these on one semiconductor substrate requires a large area. FIG. 3 shows a partial plan view of the charge transfer device of FIG. 1 in order to explain the situation during this period. The figure mainly shows the symmetrical lower half centered on the AA′ cutting line shown in the figure. In the figure, 5 is a semiconductor substrate, 6 is a transfer gate electrode line, 7 is a clock signal voltage φ ₁ drive line, 8 is a clock signal voltage φ ₂ drive line, 9 is a polysilicon electrode forming a part of the charge storage section, 10 is a field silicon oxide film. As you can see, in conventional charge transfer devices, the photoelectric conversion section and the charge storage section must be made small by pairing them, so even if the photoelectric conversion section is made small, it is limited by the size of the charge storage section. Therefore, it has the disadvantage that it is very difficult to reduce the area occupied by each photoelectric conversion section. The present applicant has separately proposed a charge transfer device and a method for driving the same that solves these drawbacks and achieves high resolution by reducing the area occupied by each photoelectric conversion section. The proposed charge transfer device consists of 2m units (m1) provided on a semiconductor substrate, and includes a photoelectric conversion section that accumulates charges generated by photoelectric conversion, which are arranged in a row and separated from each other, and a charge transfer device that stores charges accumulated in the photoelectric conversion section. A plurality of consecutive charge storage sections are arranged separately from each other such that one charge storage section corresponds to two adjacent photoelectric conversion sections on both sides of the row of photoelectric conversion sections for transferring the photoelectric conversion sections. a pair of shift registers; and a plurality of transfer gates arranged alternately and separated from each other between the photoelectric conversion section and the charge accumulation section for transferring the charges accumulated in the photoelectric conversion section to the charge accumulation section. and two transfer gate voltage application terminals, one for each of the charge storage sections and two transfer gate voltage application terminals connected in common to the transfer gates for applying the transfer gate voltage. Further, the proposed method for driving the device is to selectively apply two gate voltages to the two gate voltage application terminals in synchronization with two clock signals for driving the shift register. This consists in driving a charge transfer device. FIG. 4 is a block diagram showing the main parts of a charge transfer device which is an example of the proposed device, and FIG. 5 is a partial sectional view thereof. This device shows a case in which this proposal is applied to the conventional example consisting of six photoelectric converters, and the figures are drawn corresponding to FIGS. 1 and 3, respectively, showing the conventional example. The same reference symbols are used for the same items. The device of this example has Q ₁₁ to _{Q 22} on the semiconductor substrate 5.
Twelve photoelectric conversion units are arranged separately from each other in a row, and photoelectric conversion units Q ₁₁ and Q ₁₂ are arranged on both sides of the row of photoelectric conversion units to transfer the charges accumulated in the photoelectric conversion units. S ₁₁ to S 16 and _{S 21} to which are arranged separately from each other so that one charge storage part for every two photoelectric conversion parts corresponds to the storage part S ₁₁ .
A pair of shift registers, the first shift register 1 and the second shift register 2 each consisting of six charge storage sections _S26 , and the photoelectric conversion sections _Q11 to _Q22 are transferred to the charge storage section _S11 . 〜S ₁₆ and S ₂₁ 〜S ₂₆ A transfer gate is installed between the photoelectric conversion section and the charge storage section, and G ₁₁ is connected between Q ₁₁ and S ₁₁ , and G ₂₁ is connected between Q ₁₂ and S ₂₁ .
Twelve gates G ₁₁ to _{G 16} and G ₂₁ to _{G 26} are arranged alternately and separated from each other as shown in FIG.
G ₁₁ to _{G 16} are commonly wired with the first transfer gate electrode line 11 and a first transfer gate voltage application terminal 13 is provided, and similarly, the transfer gates G ₂₁ to _{G 26} are commonly wired with the second transfer gate electrode line 12. A second transfer gate voltage application terminal 14 is provided. Next, FIG. 6 shows a time chart of clock signal voltage and gate voltage application as an example of a method for driving this device. A clock signal voltage φ ₁ is applied to the charge storage units S ₁₁ , S ₁₃ , S ₁₅ , S ₂₂ , S ₂₄ and S ₂₆ , and a clock signal voltage φ ₂ which is the same as φ ₁ but lags φ ₁ by half a cycle is applied. Charge storage section S ₁₂ , S ₁₄ ,
It is given to S ₁₆ , S ₂₁ , S ₂₂ , and S ₂₅ . As shown in FIG. 6, transfer gate voltages φ _G1 and φ _G2 are first applied simultaneously during time t ₁₁ to t ₁₂ in synchronization with the first pulse voltage of clock signal φ ₁ .
By doing this, the photoelectric conversion parts Q ₁₁ , Q ₁₄ , Q ₁₅ ,
The charges accumulated in Q ₁₈ , Q ₁₉ , and Q ₂₂ pass through transfer gates G ₁₁ , G ₂₂ , G ₁₃ , G 24 , G ₁₅ , and G _{26 ,} respectively, and charge accumulation parts S ₁₁ , S ₂₂ , S ₁₃ , and S , respectively. ₂₄ , _S15 , _S26
will be forwarded to. The transferred charges are sequentially transferred to the right in accordance with the repetition of the subsequent clock signals φ ₁ and φ ₂ and read out to the first shift register output section 3 and the second shift register output section 4, respectively. . Next, gate voltages φ _G1 and φ _G2 are simultaneously applied during the time period t ₂₁ to _{t 22} in synchronization with the clock signal φ ₂ as shown in FIG. By doing this, the photoelectric conversion parts Q ₁₂ , Q ₁₃ , Q ₁₆ , Q ₁₇ ,
Charges accumulated in Q ₂₀ and Q ₂₁ pass through transfer gates G ₂₁ , G ₁₂ , G ₂₃ , G 14 , G ₂₅ , and G ₁₆ , respectively, and charge accumulation parts S ₂₁ , S ₁₂ , _{S 23 ,} S 14 , and S ₁₆ , respectively. ₂₅ , forwarded to S ₁₆ . The transferred charges are then sequentially transferred to the right in accordance with the repetition of the clock signals φ ₁ and φ ₂ and read out to the first shift register output section 3 and the second shift register section 4, respectively, so that they are converted into photoelectrons. This means that all the charges accumulated in the conversion section have been read out. Note that the read charges are not arranged in the order of the photoelectric conversion units, but in the case of this embodiment, Q ₁₁ , Q ₁₄ , Q ₁₅ , Q ₁₈ , Q ₁₉ , Q ₂₂ , Q ₁₂ , Q ₁₃ ,
Since they are arranged like Q ₁₆ , Q ₁₇ , Q ₂₀ , and Q ₂₁ , the read charges must be rearranged in the order of the photoelectric conversion unit by a signal from the logic control unit that has been programmed in advance. become. According to the above-mentioned explanation, the separately proposed device and its driving method show that the photoelectric The area occupied by each conversion unit is reduced to approximately 1/2 of that of the conventional example, and the resolution is approximately doubled, eliminating the drawback of the conventional technology that it is difficult to increase the resolution. I understand. However, according to this proposed device and its driving method, since the photoelectric conversion units are not lined up in the order in which they are read out from the photoelectric conversion units as described above, the read charges are transferred to the previously programmed logic control unit. It is necessary to rearrange the photoelectric conversion units in the order of the signals from the photoelectric conversion units. This requires the provision of the logic control section separately outside the charge transfer device, and furthermore, there is a concern that the time required for this process will reduce the charge transfer efficiency, so it is even more desirable that this is no longer necessary. Become. An object of the present invention is to provide a charge transfer device and a method for driving the same that satisfy such demands. According to the present invention, a plurality of photoelectric conversion sections are formed in a row on a semiconductor substrate, and a first charge transfer shift register is provided on one side of the row of photoelectric conversion sections in parallel with the row. and a second charge transfer shift register provided in parallel with the column of the photoelectric conversion units on the opposite side of the column of the photoelectric conversion units of the first charge transfer shift register, and in parallel with the column of the photoelectric conversion units. a third charge transfer shift register provided, and a fourth charge transfer shift register provided in parallel to the column on the opposite side of the column of photoelectric conversion units of the third charge transfer shift register. having said first
Each of the fourth charge transfer shift registers has a plurality of charge storage sections arranged in a row so that charges are sequentially transferred, and each charge storage section is connected to each of the two adjacent photoelectric conversion sections. first transfer gates provided correspondingly, and further arranged between every other photoelectric conversion section and the charge storage section of the first charge transfer shift register corresponding thereto; , said first
a second transfer gate provided between every other charge storage section in the charge transfer shift register and a corresponding every other charge storage section in the second charge transfer shift register; , a third transfer gate disposed between every other photoelectric conversion unit and the corresponding charge storage unit of the third charge transfer shift register;
A fourth charge storage section provided between every other charge storage section in the third charge transfer shift register and every other corresponding charge storage section in the fourth charge transfer shift register. A charge transfer device including a transfer gate is obtained. Furthermore, according to the present invention, a plurality of photoelectric conversion sections are formed in a row on a semiconductor substrate, and a first charge transfer section is provided on one side of the row of photoelectric conversion sections in parallel with the row. a shift register; a second charge transfer shift register provided in parallel with the column of photoelectric conversion units on the opposite side of the column of the photoelectric conversion units of the first charge transfer shift register; and a fourth charge transfer shift register provided in parallel with the column of photoelectric conversion units on the opposite side of the column of the photoelectric conversion units of the third charge transfer shift register. and has
Each of the first to fourth charge transfer shift registers has a plurality of charge storage sections arranged in a row so that charges are sequentially transferred, and each charge storage section is connected to two adjacent photoelectric conversion units. 1.
a first transfer gate disposed between each of the two photoelectric conversion units and the corresponding charge storage unit of the first charge transfer shift register; a second transfer gate provided between every other charge storage section and a corresponding every other charge storage section in the second charge transfer shift register; a third transfer gate disposed between the photoelectric conversion section and the corresponding charge storage section of the third charge transfer shift register; and every other gate in the third charge transfer shift register. A method for driving a charge transfer device, the method comprising: a fourth transfer gate provided between each of the charge storage units in the fourth charge transfer shift register and every other corresponding charge storage unit in the fourth charge transfer shift register; the every other charge storage section through the first and third transfer gates between the every other charge storage section and the photoelectric conversion section in the first and third charge transfer shift registers; After transferring the charges to the second and fourth transfer gates, the transferred charges are transferred to the second and fourth transfer gates through the second and fourth transfer gates.
, and then transfers the charge to the first and third charge transfer shift registers through the remaining first and third transfer gates, respectively, and then transfers the transferred charge to the first and third charge transfer shift registers, respectively. A method for driving a charge transfer device that transfers charges in each of the first to fourth charge transfer shift registers is obtained. The present invention will be explained in detail below using the drawings. FIG. 7 is a block diagram showing the main parts of a charge transfer device according to a first embodiment of the present invention. In the device of this embodiment, 12 of Q ₁₁ to _{Q 12} are formed from N-type diffusion regions on a P-type semiconductor substrate, for example.
A voltage is applied through an insulating thin layer such as silicon oxide to transfer the charges accumulated in the photoelectric conversion parts _Q11 to _Q12 , which are arranged in a row and separated from each other. A charge storage section _S11 that stores and transfers charges within the semiconductor substrate by
~S ₁₆ , S ₂₁ ~ _{S 26} , S ₃₁ ~S ₃₆ and S ₄₁ ~S ₄₆ are arranged per two photoelectric conversion units so that photoelectric conversion units Q ₁₁ and Q ₁₂ correspond to charge storage unit S ₁₁ . Two shift registers each consisting of six charge storage units arranged separately from each other so that each charge storage unit corresponds to each other are arranged on both sides of the column via the column of photoelectric conversion units.
The first shift register 21 (S ₁₁ to
S ₁₆ ), the third shift register 23 (S ₃₁ to _{S 36} ), the second shift register 22 (S ₂₁ to _{S 26} ), and the fourth shift register 24 (S ₄₁ to _{S 46} ), (in this case)
S ₁₀ , S ₂₀ , S ₃₀ and S ₄₀ are respective register outputs. ) The charges accumulated in the photoelectric conversion section are
Photoelectric conversion units Q ₁₁ to _{Q 16} and charge storage units S ₁₁ to _{S 16} , S ₂₁ for transferring to the second shift registers 21 and 22
Between _Q11 and _S26 , a transfer gate that forms a charge transfer region in the semiconductor substrate by applying a voltage through an insulating thin layer in the same manner as the charge storage section is installed.
First transfer gates G ₁₁ to G ₁₆ and second transfer gates G _{21 to 6 are arranged alternately and separately, such as G 11 between} S ₁₁ and _{G 21 between} Q 21 and S ₂₁ . _G26
and a first transfer gate voltage application terminal 25 and a second transfer gate voltage application terminal 26, which are formed by connecting the respective gates in common in order to apply voltage to these gates, and the voltage transferred to the first shift register 21. In order to transfer a part of the charge to the third shift register 23 and a part of the charge transferred to the second shift register 22 to the fourth shift register 24, G ₃₁ is connected between the charge storage parts S ₁₁ and S ₃₁ . , between S ₁₃ and S ₃₃
G ₃₂ , G ₃₃ between S ₁₅ and S ₃₅ , G ₄₁ between S ₂₂ and S ₄₂ , S ₂₄ and
G ₄₂ between S ₄₄ and G ₂₆ between S ₂₆ and S ₄₆ , and between the first shift register 21 and the third shift register 23, there is a second shift register 22 between each odd-numbered charge storage section. Between the fourth shift registers, third transfer gates G ₃₁ to G ₃₃ and fourth transfer gates G ₄₁ to _{G 43} each consist of three gates for each even-numbered charge storage section.
and a third transfer gate voltage application terminal 27 and a fourth transfer gate voltage application terminal 28, each of which is connected in common to apply a voltage to these gates.
It is completed by providing other necessary input/output parts, power supply parts, wiring, etc. The transfer gates are arranged in such a way that charges are not transferred to adjacent charge storage sections constituting the same shift register at the same time. Although the plan view of this embodiment is not particularly shown, in the plan view of another proposed device shown in FIG. shift register and second
The shape is almost the same as that of the transfer gate, and the area occupied by each photoelectric conversion section is approximately 1/2 that of the conventional example.
The resolution will be approximately doubled. Next, a method for driving the charge transfer device according to the first embodiment of the present invention will be described. As shown in FIG. 7, the first shift register 21
and the second shift register 22 are two-phase driven by clock signal voltages φ ₁ and φ ₂ , and φ ₁ is the odd-numbered charge storage section S ₁₁ , S ₁₃ , S ₁₅ of the first shift register and the second shift register 22 is applied to the even-numbered charge storage parts S ₂₂ , S ₂₄ , and S ₂₆ , and φ ₂ is applied to this.
It is applied to S ₁₂ , S ₁₄ , S ₁₆ and S ₂₁ , S ₂₃ , S ₂₅ . Further, the third shift register 23 and the fourth shift register 24 are driven in two phases by clock signal voltages φ ₃ and φ ₄ , and φ ₃ is driven by charge storage portions S ₃₁ and S ₃₃ as in the case of φ ₁ and φ ₂ . , S ₃₅ and S ₄₂ , S ₄₄ ,
In S ₄₆ , φ ₄ is applied to S ₃₂ , S ₃₄ , S ₃₆ and S ₄₁ , S ₄₃ , S ₄₅ . On the other hand, the first transfer gates G ₁₁ to G ₁₆ and the second transfer gates G ₂₁ to _{G 26} have respective voltage application terminals 25,
A gate voltage of φ _G1 is applied to both the third transfer gates G ₃₁ to G 33 and a gate voltage of φ G2 to the third transfer gates G 31 to _{G 33} and a fourth transfer gate G ₄₁ to _{G 43} via voltage application terminals ₂₇ and 28, respectively. applied. These clock signal voltages and gate voltages are both approximately (+)
The pulse voltage has a magnitude of 12V and a pulse width of about 1 μsec, and its temporal arrangement is determined by the time chart shown in FIG. First, when φ _G1 is applied in synchronization with φ ₁ between t ₃₁ and t ₃₂ , the charge in the photoelectric conversion unit Q ₁₁ is transferred to the transfer gate.
The charges are transferred to the charge storage section S ₁₁ via G ₁₁ and similarly Q ₁₄ →S ₂₂ , Q ₁₅ →S ₁₃ , Q ₁₈ →S ₂₄ , Q ₁₉ →S ₁₅ ,
Transferred to Q ₂₂ →S ₂₆ . Next, when φ _G2 is applied in synchronization with φ ₃ between t ₃₂ and _{t 33} , the charges transferred to S ₁₁ , S ₁₃ , and S ₁₅ are transferred via the third transfer gates G ₃₁ to _{G 33} .
Transferred to S ₃₁ , S ₃₃ , S ₃₅ and similarly S ₂₂ → S ₄₂ ,
Transferred to S ₂₄ → S ₄₄ and S ₂₆ → S ₄₆ . then t ₃₃ ~ _{t 34}
When φ _G1 is applied again in synchronization with φ ₂ during the period, Q ₁₂ →S ₂₁ , Q ₁₃ →S ₁₂ , Q ₁₆ →
All the charges remaining in the photoelectric conversion section are transferred to the charge storage section as shown in S _{23 ,} Q ₁₇ →S ₁₄ , Q 20 →S ₂₅ , and Q ₂₁ →S ₁₆ . Table 1 shows the positions of the charges transferred in this way. The times in the first column indicate the number of times the clock signal voltage is applied, the second column indicates the type of applied voltage, and the numbers in the table indicate the charges. The location is indicated by the number of the storage section. If we look at the second and third rows in Table 1 horizontally, we see that, for example, the first shift register 2
1, S ₁₂ , S ₁₄ , S ₁₆ , third shift register 23
In this case, charges are transferred to every other charge storage section such as S ₃₁ , S ₃₃ , and S ₃₅ constituting the same shift register, and charges are not transferred adjacent to each other at the same time.

[Table] Now, once all the charges are transferred to the charge storage section in this way, the clock signal voltages φ ₁ to φ are adjusted so that the charges are transferred to the output section of each shift register in the order of the photoelectric conversion sections. I'm going to apply ₄ . In this case, as shown in Table 1, by applying φ ₄ , the charge of Q ₁₁ is transferred to the output of the third shift register 23.
By repeatedly applying φ ₁ , φ ₂ , φ ₃ , and φ ₄ in the order of S ₃₀ , all charges are transferred to the output section of the shift register in the order of the photoelectric conversion section and read out as an image. It will be assembled. FIG. 9 is a block diagram showing the main parts of an apparatus according to a second embodiment of the present invention. As is clear from this figure, in this embodiment, the installation locations of the third transfer gates G ₃₁ to _{G 33} and the fourth transfer gates G ₄₁ to G ₄₃ of the first embodiment shown in FIG. 7 are switched. It's summery. One embodiment of the method for driving the device of the second embodiment is as shown in FIG. 9, in which φ ₁ ,
The arrangement of φ ₂ , φ ₃ , and φ ₄ is the same as in the first embodiment, but the order of application is different as shown in Table 2. Here, Table 2 shows the charge transfer positions in the same way as Table 1.

[Table] First, gate voltage φ _G1 is applied in synchronization with clock signal φ ₂ , then φ _G2 is applied in synchronization with φ ₄ , and then φ _G1 is applied again in synchronization with φ ₁ . .
Thus, as shown in Table 2, the charges accumulated in the photoelectric conversion section are Q ₁₁ →S ₁₁ , Q ₁₂ →S ₄₁ , Q ₁₃ →S ₃₂ ,
Q ₁₄ →S ₂₂ , Q ₁₅ →S ₁₃ , Q ₁₆ →S ₄₃ , Q ₁₇ →S ₃₄ , Q ₁₈
→S ₂₄ , Q ₁₉ →S ₁₅ , Q ₂₀ →S ₄₅ , Q ₂₁ →S ₃₆ , Q ₂₂ →S ₂₆
All the charges are sequentially transferred and accumulated in every other charge storage section constituting each register as shown in FIG. After that, by applying a clock signal so that the charges are transferred to the output part of the shift register in the order of the photoelectric conversion part, that is, φ ₂ ,
By applying φ ₃ , φ ₄ , φ ₁ , φ 2 , ... in the order of φ 3 , φ 4 , φ 1 , φ ₂ , ......, all charges are transferred to the output section of any shift register in the order of the photoelectric conversion section as shown in Table 2, and assembled as an image. It will be done. As is clear from the above description, the method for driving the charge transfer device of the first embodiment and the charge transfer device of the second embodiment is based on the separately proposed device further comprising a third shift register 23 and a fourth shift register 24. A pair of shift registers is added, and transfer gates are provided in adjacent charge storage sections of the same shift register so that charges are not transferred at the same time, and the gates are selectively gated in synchronization with the clock signal voltage of the shift register. Since the voltage is applied and the clock signal voltage is applied so that the charges are transferred to the output part of the shift register in the order in which the photoelectric conversion units Q ₁₁ to _{Q 22} are lined up,
By reducing the area occupied by each photoelectric conversion unit to about 1/2, which was a problem with conventional devices, the resolution has been improved by about twice. The output section of the shift register has a photoelectric conversion section _Q11 , which was considered a problem.
Since the charges are not transferred in the order in which the columns of ~Q ₂₂ are arranged, it is also possible to solve the problem that it is necessary to provide a separate pre-programmed logic control circuit to rearrange the charges. . Next, a charge transfer device and a driving method thereof according to a third embodiment of the present invention will be described with reference to FIG. The charge transfer device according to the third embodiment is a charge transfer device according to the first embodiment shown in FIGS. ₇ and ₉ , in addition to the charge transfer device according to the first embodiment shown in FIGS. It consists of a shift register arranged on either side of the registers, in addition to the charge storage, on its output side a further charge storage is added. In the device of the third embodiment shown in FIG. 10, the second shift register 22 and the fourth shift register 24 each have a charge storage section.
S ₂₁ ′ and S ₄₁ ′ are inserted between S ₂₁ and S ₂₀ and between S ₄₁ and S ₄₀ . Further, in this device, the third transfer gate and the fourth transfer gate are arranged between odd-numbered charge storage portions corresponding to each phase, and the first and second transfer gates are the same as the charge transfer device of the first embodiment. It is an array. Next, an example of a method for driving this example device is as follows.
As shown in FIG. 9, the arrangement of the clock signal voltages φ ₁ , φ ₂ and φ ₃ , φ ₄ applied to each charge storage section is such that φ ₁ and φ 3 are applied to the odd-numbered charge storage sections, and φ ₃ is applied to the even-numbered charge storage sections. ₂ ,
φ ₄ is given, and the transfer gate voltages φ _G1 and φ _G2 are selectively applied in synchronization with the clock signal voltage as shown in Table 3, and then the clock signal voltage is applied so that the charge is transferred to the photoelectric conversion section in this order. It consists of applying as follows.

[Table] First, gate voltage φ _G1 is applied to the first and second transfer gates in synchronization with clock signal voltage φ ₁ ,
Next, gate voltage _{φ G2 is} applied to the third and fourth transfer gates in synchronization with clock signal voltage φ 3 , and then gate voltage φ _G1 is applied to the first transfer gate in synchronization with clock signal voltage φ ₂ . In this way, all the charges accumulated in the photoelectric conversion section are transferred to the charge storage section,
As shown in Table 3, these charges are accumulated in every other charge storage section within the same shift register. Next, φ ₁ and φ ₄ are applied simultaneously once, and then the clock signals are applied in the order of φ ₃ , φ ₂ , φ ₁ , φ ₄ , φ ₃ , φ ₂ , φ _{1 ,} etc., so that the total charge is reduced. are transferred and read out to the output section of one of the shift registers in the order of the photoelectric conversion section (Q ₁₁ , Q ₁₂ , . . . ) and assembled as an image. FIG. 11 is a block diagram showing the main parts of a charge transfer device according to a fourth embodiment of the present invention. As is clear from this figure, the charge transfer device of this embodiment has the third transfer gates G ₃₁ to _{G 33} of the third embodiment shown in FIG.
The arrangement of the fourth transfer gates G ₄₁ to _{G 43} is changed from between the odd-numbered charge storage sections to between the even-numbered charge storage sections. In one embodiment of the method for driving the charge _transfer device of _the fourth embodiment, as _shown in _FIG . This is the same as the first embodiment shown in FIG. 10, and consists of selectively applying the transfer gate voltage and the clock signal voltage as shown in Table 4.

[Table] First, by applying gate voltage φ _G1 in synchronization with clock signal voltage φ ₂ , then φ _G2 in synchronization with φ ₄ , and then φ _G1 in synchronization with φ ₁ , photoelectric All of the charges accumulated in the conversion section are transferred to the charge accumulation section, and these charges are accumulated in every other charge accumulation section within the same shift register, as shown in Table 4. Next, by applying φ ₂ and φ ₃ simultaneously once, and then applying the clock signals in the order of φ ₁ , φ ₄ , φ ₃ , φ ₂ , φ ₁ , etc., the entire load is applied to the photoelectric conversion section. They are transferred and read out to the output section of the shift register in accordance with the order. FIG. 12 is a block diagram showing the main parts of a charge transfer device according to a fifth embodiment of the present invention. The device of this embodiment corresponds to a special case in which the third transfer gate G ₃₁ and the fourth transfer gate G ₄₁ are omitted from the charge transfer device of the third embodiment shown in FIG. The method of driving the device shown in FIG. 12 is to apply clock signal voltages φ ₁ ,
The division of application of φ ₂ , φ ₃ , and φ ₄ is the same as in the third embodiment shown in FIG. 10, and the transfer gate voltage and clock signal voltage are selectively applied as shown in Table 5. It is completed.

[Table] First, the total charge is reduced by applying gate voltage φ _G1 in synchronization with clock signal voltage φ ₁ , then φ _G2 in synchronization with φ ₃ , and then φ _G2 in synchronization with φ ₂ . As shown in Table 5, in the same shift register, every other charge is transferred and stored in the charge storage section. However, at this stage, the charge of _Q11 is transferred to the first shift register 2.
1 output section _S10 . Next, φ ₁ and φ ₄ are applied simultaneously, then φ ₂ and φ ₃ are applied simultaneously, and thereafter, the clock signals are applied in the order of φ ₁ , φ ₄ , φ 3 , _{φ 2 ,} φ ₁ , etc. By applying this, all charges are transferred and read out to the output section of the shift register in the order of the photoelectric conversion sections. As can be seen from Table 5, this case has the characteristic that the number of times the clock signal is applied is 14 times, which is one less than the 15 times in the previous embodiments. As is clear from the above description, the charge transfer devices of the third to fifth embodiments and the method of driving the device are the same as those of the first to fifth embodiments.
Similar to the charge transfer device and its driving method in the second embodiment, the entire charge is transferred to the photoelectric converter while maintaining a state in which the resolution is approximately doubled by reducing the area occupied by the photoelectric converter to approximately 1/2. Since the data can be transferred to the output section of the shift register in the order of the conversion section, there is an advantage that the rearrangement of the transfer data, which was required in the previously proposed device and its driving method, is no longer necessary. In the above description, the case where the semiconductor substrate is P type has been explained, but it goes without saying that the present invention can be similarly applied to the case where the semiconductor substrate is N type. Furthermore, detailed explanations of the method of manufacturing the charge transfer device, the driving signal power source, etc. are omitted, but these can all be easily achieved using conventional techniques. As is clear from the detailed explanation so far, according to the present invention, the area occupied by the photoelectric conversion section corresponding to one charge storage section is reduced to 1/2 of that of the conventional one, and the resolution is thereby improved by twice. Even in this state, the accumulated charges can be transferred and read out to the output section of the shift register in the order in which the photoelectric conversion sections are lined up, which is not necessary in the other proposed charge transfer device and its driving method. This eliminates the need for a means to rearrange the order of transferred charges, and the problems of installing a logic control unit as a rearranging means and reducing transfer efficiency due to the time required for this processing are automatically resolved. Therefore, it is possible to provide an easy-to-use charge transfer device with greatly improved resolution and a method for driving the same, and the effects thereof are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of a conventional charge transfer device, FIG. 2 is a time chart showing the order of applying clock signal voltages and transfer gate voltages, and FIG. 3 is a partial plan view thereof. FIG. 4 is a block diagram showing the essential parts of an example of a charge transfer device previously proposed by the applicant, FIG. 5 is a partial plan view thereof, and FIG. 6 shows the order of applying the clock signal voltage and transfer gate voltage. It is a time chart diagram shown. FIG. 7 is a block diagram showing the main parts of the charge transfer device according to the first embodiment of the present invention, FIG. 8 is a time chart showing the clock signal and transfer gate voltage application order, and FIG.
The figure is a block diagram showing the main parts of the apparatus according to the second embodiment of the present invention, and FIGS. 10, 11, and 12 are the main parts of the apparatus according to the third, fourth, and fifth embodiments of the present invention, respectively. FIG. In the figure, 1, 21...first shift register, 2, 22...second shift register, 3, 4...
...Output section, 5...Semiconductor substrate, 6...Transfer gate electrode line, 7...Clock signal voltage _φ1 drive line, 8
...Clock signal voltage _φ2 drive line, 9...Polysilicon electrode, 10...Field oxide film, 11...
...First transfer gate electrode line, 12...Second transfer gate electrode line, 13, 25...First transfer gate voltage application terminal, 14,26...Second transfer gate voltage application terminal, 23...Third shift Register, 24...Fourth shift register, 27...Third transfer gate voltage application terminal, 28...Fourth transfer gate voltage application terminal, _Q1 to _Q6 , _Q11 to _Q22 ...Photoelectric conversion unit, S ₁₁ ~
S ₁₆ , S ₂₁ to S ₂₆ , S ₃₁ to _{S 36} , S ₄₁ to _{S 46} ... Charge storage section, S ₁₀ , S ₂₀ , S ₃₀ , S ₄₀ ... Output section, φ ₁ , φ ₂ ,
_φ3 , _φ4 ...Clock signal voltage, _φG , _φG1 , _φG2 ...
...is the transfer gate voltage.

Claims (1)

[Scope of Claims] 1. A plurality of photoelectric conversion sections formed in a row on a semiconductor substrate, and a first charge transfer shift provided on one side of the row of photoelectric conversion sections in parallel with the row. a second charge transfer shift register provided parallel to the column of the photoelectric conversion sections on the opposite side of the column of the photoelectric conversion sections of the first charge transfer shift register; and a fourth charge transfer shift register provided in parallel to the column on the opposite side of the column of photoelectric conversion units of the third charge transfer shift register. Each of the first to fourth charge transfer shift registers has a plurality of charge storage sections arranged in a row so that charges are sequentially transferred, and each charge storage section has two adjacent charge storage sections. The photoelectric conversion sections are provided corresponding to the two photoelectric conversion sections, respectively, and are further arranged between every other photoelectric conversion section and the charge storage section of the first charge transfer shift register corresponding thereto. between the first transfer gate and the corresponding every other charge storage section in the first charge transfer shift register and the corresponding every other charge storage section in the second charge transfer shift register; and a third charge storage section disposed between every other photoelectric conversion section and the corresponding charge storage section of the third charge transfer shift register. and a corresponding one of every other charge storage sections in the third charge transfer shift register and a corresponding one of every other charge storage sections in the fourth charge transfer shift register, respectively. A charge transfer device comprising a fourth transfer gate. 2 a plurality of photoelectric conversion sections formed in a row on a semiconductor substrate; a first charge transfer shift register provided on one side of the row of photoelectric conversion sections in parallel with the row; A second charge transfer shift register provided in parallel with the column of photoelectric conversion units on the opposite side to the column of photoelectric conversion units of the charge transfer shift register, and a third charge transfer shift register provided in parallel with the column of photoelectric conversion units. and a fourth charge transfer shift register provided in parallel with the column of photoelectric conversion units on the opposite side of the column of photoelectric conversion units of the third charge transfer shift register, Each of the first to fourth charge transfer shift registers has a plurality of charge storage sections arranged in a row so that charges are sequentially transferred, and each charge storage section is connected to two adjacent photoelectric conversion sections. first transfer gates provided correspondingly to each other, and further arranged between every other photoelectric conversion section and the charge storage section of the first charge transfer shift register corresponding thereto; and a second charge storage section provided between every other charge storage section in the first charge transfer shift register and every other corresponding charge storage section in the second charge transfer shift register. a third transfer gate disposed between the second transfer gate, every other photoelectric conversion section and the corresponding charge storage section of the third charge transfer shift register; fourth transfers provided between every other charge storage section in the third charge transfer shift register and corresponding every other charge storage section in the fourth charge transfer shift register; In the method for driving a charge transfer device, the first and third transfers between every other charge storage section in the first and third charge transfer shift registers and the photoelectric conversion section include: After each charge is transferred to the every other charge storage section through the gate, the transferred charge is transferred to the second and fourth charge transfer shift registers via the second and fourth transfer gates. After that, the charges are transferred to the first and third charge transfer shift registers through the remaining first and third transfer gates, respectively, and then the transferred charges are transferred to the first to fourth charge transfer shift registers. 1. A method for driving a charge transfer device, characterized in that charges are transferred in each of the charge transfer shift registers.