JPH0131819B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to clock signal phase synchronization in digital signal transmission.

In high-efficiency digital signal transmission, code transmission is performed using pulses shaped into a small roll-off waveform, so a sample timing shift on the receiving side will rapidly deteriorate the characteristics. Traditionally, sample timing, or clock signal extraction, involves rectifying an input signal to generate a clock component, which is then passed through a narrow band pass waver to extract the clock.

In recent years, receivers have become increasingly digital, and the need for digital processing for clock signal extraction has increased. For digitizing receivers, direct control of sample timing is preferred rather than extraction of the clock signal.

An object of the present invention is to provide a simple sample timing control circuit suitable for digital processing. The present invention includes a first sampler that samples a complex input signal at zero phase of a clock signal, a second sampler that samples the complex input signal at a π phase of the clock signal, and a plurality of symbols of the output of the first sampler. A discriminator that identifies, a change detector that detects a change between the value of the output of the discriminator one cycle before and the current value, and only when the change detector detects a change in the discrimination value of both the real and imaginary parts. a multiplier that obtains the product of at least one of the difference between the discriminator output or the value of the discriminator output one cycle before and the current value, and the real part and imaginary part of the second sampler output. death,
The clock phase control circuit is characterized in that the phase of the clock signal is changed according to the output of the multiplier, and the complex input signal is controlled so that it is sampled by a first sampler at an optimal sampling phase.

Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 a is a binary digital signal of +1 and -1,
Alternatively, it shows the eye pattern of the real part or imaginary part of the demodulated signal of the quadrature phase modulated wave. Figure b shows the sample timing, and the time every T seconds indicated by the arrow corresponds to the widest eye opening time of the eye pattern. Figure c shows a timing signal that is shifted by a π phase (180°) from the previous one. At this timing, the previous a
When a waveform is sampled, it takes approximately three values: a value of ±1 when the transmission code does not change before and after that, and a value near zero when it changes conversely. Although the waveform in Figure 1a depends on the roll-off rate of the transmitted pulse and the bit pattern, it is approximately the same as the second waveform.
Even if it is simplified as shown in Figure a, there is no problem on average. Therefore, as shown in Figure 2b, the sample
Consider the case where the timing is delayed by Te seconds. As a result, the eye opening narrows from W ₀ to W ₁ , and the value sampled from the input signal at the timing shown in FIG. 2c also changes from a value near zero to a larger value. Except when the transmission code does not change before and after the arrow in c, if it changes from -1 to +1, the sample value at c will take a positive value e _(-+) , and conversely, it will take +1. When it changes from to -1, it takes a negative value e _(+-) . As a result, by knowing the transmission code before and after the timing of the sample c.
Timing deviations can be detected. Therefore, from now on, the timings shown in FIGS. 1 and 2 b will be referred to as data sample timings, and c will also be referred to as zero-cross detection timings.

The above explanation can be summarized as follows. First, if the data before and after the zero-cross detection timing remains unchanged, timing shift information cannot be obtained from the input waveform sample value at the zero-cross detection timing. Second, when the data changes from -1 to +1, the timing shift information is proportional to the input waveform sample value at the zero cross detection timing. Thirdly, when the data changes from +1 to -1, the timing shift information is proportional to the value of the opposite polarity of the input waveform sample value at the zero cross detection timing.

FIG. 3 shows a concrete example of the principle of timing deviation information detection described above.

In the figure, 1 is the first sampler that samples the input signal at the data sample timing, 2 is the second sampler that samples the input signal at the zero cross detection timing, and 3 is the sign identification of the output of the first sampler. 1 is a discriminator that outputs 1, 4 is a differentiator that works as a change detector to detect changes in data as explained above, -bit delay circuit 40 and subtracter 41
It consists of. 5 is a multiplier that takes the product of the differentiator output and the second sampler output. Among the inputs of the multiplier, the differentiator output outputs the difference between the value of the discriminator output one cycle before and the current value as defined in the claims, but instead of this input, the discriminator output If you input the output as is, it will behave exactly the same. In other words, in the case of 4PSK, when the differentiator output is positive,
This is because the current value of the discriminator output is also positive. Similarly, if the change detector detects a signal change,
Since the identification value from one cycle before always has the opposite polarity to the current identification value, the identification value from one cycle before may be used with the polarity reversed instead of the current identification value. In addition,
In addition to a differentiator like the one in this example, this change detector has a structure in which, for example, the positive and negative of the demodulated signal correspond to the high and low levels of the logic level, and the exclusive OR of the same signal and the same signal one cycle before. When the output is high level, it corresponds to a change in the signal. 6 is a clock signal generator, which includes a high-speed pulse oscillator 61 and a counter 60 that counts down the same pulses.The initial value of the counter is determined by the sum (N+) of a constant N and a control signal α.
.alpha.). When the counter counts down to zero, it outputs a sample pulse to the outside, sets the output value of the adder 62 as the next initial value, and starts counting down again. This shows that the control signal applied to input terminal 104 can control the output phase of the sample pulse from the clock signal generator. 7 is a T/2 delay circuit for generating zero cross detection timing from data sample timing.

Now, considering the output of the multiplier 5, if the data does not change, the output of the differentiator 4 is zero, so
Zero is output to the output terminal 101. -1 to +
When there is a data change to 1, the output of the differentiator 4 becomes 2, and 2.times.(zero cross sample value) appears at the output terminal 101. Conversely, when the data changes from +1 to -1, the output of the differentiator 4 is -2
Therefore, −2× (zero cross sample value) appears at the output terminal 101. This shows that timing shift information in the correct direction appears at the output terminal 101 for any data change.

FIG. 4 shows the relationship between the average output e of the output terminal 101 and the timing deviation Te. The reason why the characteristics are discontinuous at Te = ±T/2 in the same figure is because the data sample timing is near the zero cross timing of the waveform, which causes a sudden polarity reversal. do.

In the above explanation, the input signal has been treated as a real number, but there may be a case where two series of independent data exist in the real part and the imaginary part, such as in quadrature phase modulation. In this case, one of the real part and the imaginary part can be treated as a real number waveform and treated in the same way as before, but it is a problem to discard the other part that has valid information. On the other hand, in carrier band communication, synchronous detection is often used due to its excellent characteristics, but carrier phase synchronization is required at this time. In situations where this is not established, the phase modulation signal will be received tilted by the phase difference between the input signal carrier and the receiving side reference carrier, and if there is a frequency offset △f between the two, the phase modulation signal will be tilted according to △f. The received signal point rotates.
It goes without saying that it would be more convenient if clock phase control could be executed regardless of carrier phase synchronization. Since the explanation in FIG. 2 is for a baseband signal, the situation will be somewhat different in a situation where carrier synchronization in the carrier band is not achieved. However, even in this case, if the real part and imaginary part of the four-phase phase modulated wave change simultaneously, the signal point transition on the phase plane will pass near the origin at the π/2 phase of the clock. This situation is the same regardless of the carrier phase state. Therefore, by controlling the clock phase only in such a situation, it is possible to make it completely independent of the carrier phase synchronization state.

FIG. 5 shows an extension of the configuration of FIG. 3 to a complex signal. The first sampler 1, second sampler 2, discriminator 3, and differentiator 4 in FIG. 3 are assumed to be the same components that input and output complex numbers, respectively.
4', input terminal 100, output terminal 102,1
03 also has two sets of terminals 100, each corresponding to a complex number.
0,1001,1020,1021,1030,
100', 102', and 103' with 1031 are reconfigured to accommodate complex number inputs. Components not particularly described here are the same as those in FIG. 3. However, the multiplier of 5 is not shown here. 200 is a reference number throughout FIG.

FIG. 6 is a diagram showing a block diagram of one embodiment of the present invention. Block 200 is the same as in FIG. Block 5' is a multiplication circuit, and 50 in the block performs the same function as multiplier 5 in FIG. The other part is a detection part that detects simultaneous changes in the real part and imaginary part of the received modulated signal.
The presence or absence of a change in both is determined by the terminal 102, which is the differentiator output.
It is found by 0,1021. If both are unchanged, zero is output. 55 and 56 are absolute value circuits which output a constant positive value when the differentiator output is non-zero, and output zero when it is zero. Comparators 51 and 52 output a low level in response to a zero input, and a high level in response to an input of a value greater than a certain value. 53 is an AND circuit, and both comparator outputs are high.
Outputs high level only when the level is high. By setting the low level of the AND circuit to zero, the multiplier 54 multiplies the output of the multiplier 50 by the output of the AND circuit, thereby suppressing control when the real part and imaginary part of the received modulated signal do not change simultaneously. can do. In addition to this embodiment, various configurations of this detection section can be used, including a method of inputting the outputs of terminals 1020 and 1021 to a multiplier and using a comparator to determine whether the output is zero. Conceivable. Further, the inputs of the multiplier 50 are the real part of the second sampler output and the real part of the differentiator output, but the operation is exactly the same even if the discriminator output is input instead of the differentiator output.

That is, when the differentiator output is positive, the current value of the discriminator output is also positive. Similarly, the output of the discriminator one cycle before, whose polarity has been reversed, can be used instead. Also, as an input to the multiplier 50, the second
It goes without saying that the imaginary parts of the sampler and the differentiator or discriminator may be used instead of the real parts, and the sum of the results obtained from both of them may also be considered. A weighted sum according to the magnitude of the absolute value is also considered to be effective.

As described above, according to the present invention, a clock phase control circuit suitable for digital processing can be provided.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams for explaining the relationship between digital transmission waveforms and sample timing. Third
The figure shows a block diagram of a clock phase control circuit for real number signals. In the figure, 1 is a first sampler, 2 is a second sampler, 3 is a discriminator, 4 is a differentiator functioning as a differentiator change detector, and 5 is a multiplier. FIG. 4 is a diagram showing the relationship between the timing deviation Te and the timing deviation detection output. FIG. 5 is a block diagram when FIG. 3 is expanded to include complex number signals. FIG. 6 is a diagram showing a block diagram of an embodiment of the present invention. In the figure, 1' is a first sampler, 2' is a second sampler, 3' is a discriminator, 4' is a differentiator that functions as a change detector, and 5' is a multiplier.

Claims (1)

[Claims] 1. A first sampler that samples the complex input signal at the zero phase of the clock signal, a second sampler that samples the complex input signal at the π phase of the clock signal, and identifying the complex sign of the output of the first sampler. a discriminator, a change detector for detecting a change between the value of the output of the discriminator one cycle before and the current value; It comprises a multiplier that obtains the product of at least one of the difference between the discriminator output or the value of the discriminator output one cycle before and the current value, and the real part and the imaginary part of the second sampler output. , a clock phase control circuit that changes the phase of the clock signal in accordance with the output of the multiplier to control the complex input signal so that it is sampled by a first sampler at an optimal sampling phase.