JPH0132543B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiprocessor system that gives priority to a plurality of processors, allocates a common bus, and accesses the memory and channels connected to the bus. .

[Conventional technology]

Conventionally, a multiprocessor system is used in which a plurality of processors are given priorities and are made to occupy a common bus. FIG. 3 shows an example of this type of system. Processor (0)1 ₁ , (1)1
₂ , ...(n)1 _o are drivers 2 ₁ , 2 ₂ ..., respectively.
...2 _o are connected to the common bus 3 in parallel, and the common memory 5 is connected to the common bus 3 via the driver 4.
Channels (0) 7 ₁ , (1) 7 ₂ . . . are connected via drivers 6 ₁ , 6 ₂ . . . respectively. In order to control the occupation of the common bus 3 by these plurality of processors ₁₁ to _1o , a priority determination circuit 10 is provided in one of the processors, for example, processor (0) ₁₁ , as will be described in detail later. Permissions are granted according to predetermined priorities in response to bus requests from processors. In this way, any processor or any channel can occupy the common bus and make the necessary accesses.

The memory access procedure of this multiprocessor system is shown in FIGS. In other words, when controlled by the clock (CLK) in the figure, when there is a bus request in the figure from any processor, the priority determination circuit 10 of processor (0) ₁₁ determines, and the bus access permission in the figure is granted. returned. As a result, the request processor outputs the address shown in the figure, the memory access signal shown in the figure is set, and the data shown in the figure is read out.

[Problem that the invention seeks to solve]

The problem with the conventional procedure above is as shown in the figure.
The time T ₁ from the request processor's bus request to the memory access signal, shown by , is large. This is because it includes a procedure to ensure that addresses are sent reliably from the processor through the local bus through the common bus. And each processor is treated equally.

Therefore, the problem is that for a frequently used processor with a high priority level, tallying up this time becomes a considerable burden.

The present invention solves the above-mentioned problems and provides a multiprocessor bus allocation method that improves the utilization rate of a common bus by making the access of the highest priority processor, which is particularly highly used, more efficient. This is the purpose.

[Means and actions for solving problems]

In order to achieve the above object, the multiprocessor control method of the present invention gives priority to a plurality of processors, allocates a common bus, and accesses the memory and channels connected to the bus. The processor that is used most frequently is designated as the processor with the highest priority, and when no other processors are using the common bus, the common bus is always assigned to the processor with the highest priority. . By controlling in this way, the processor with the highest priority which is frequently used can always eliminate the time loss of _T1 time shown in FIG. 4 in the conventional example, except for the first one. When a processor or channel other than the one with the highest priority accesses the common bus, the procedure shown in FIG. 4 is followed, and after the procedure is completed, the bus is always allocated to the processor with the highest priority.

In this way, by allocating the common waiting time of all processors to the occupancy of the processor with the highest priority, when a request is actually made to that processor, the time required for the procedure to access this address is reduced to T. ₁ is omitted, which saves time, and its aggregation reduces the overhead of the heavily used highest priority processor, thus reducing the latency for other processors.

〔Example〕

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention,
FIGS. 2A and 2B are explanatory diagrams of the operation. Part 1 below
The explanation will be made according to the figures and with reference to FIGS.
The entire system is as shown in Figure 3, with processor (0) ₁ as the highest priority processor,
A priority determination circuit 10 is provided here. FIG. 1 shows a detailed configuration example of a portion including a processor (0) ₁₁ and a transceiver ₂₁ .

It is assumed that processor (0) 1 ₁ occupies the bus when no other device other than processor (0) 1 ₁ is accessing the bus.

Now, when a DMA request instructing channel 1 to directly transfer data from memory 5 is input to priority determination circuit 10, the command from processor (0) ₁₁ causes, for example, channel 1, channel 0, and processor 1 shown in the figure to be DMA according to priority
Allow DACK0, DACK1, DACK2 to output. In this case, on the condition that there is no DMA permission DACK3 for the request of processor (0) 1 ₁ itself, for example, the DMA permission signal DACK0 of processor (1) 1 ₂ is output, and in response, channel 1 performs the following data transfer. Initiate the sequence and control the transceiver control circuit shown at the bottom of FIG.

(i) Output address/data (Figure 2).

(ii) Bus skew and address decode time
A strobe signal DSV1 is output to guarantee T ₁ ' (Figure 2).

(iii) Response signal SRV0 from memory causes bus
End the sequence.

First, the DMA permission signal DACK0 is input to the flip-flop (FF2) 12 via the OR circuit 14 and set at the timing shown in FIG. The above-mentioned time T ₁ ' is guaranteed by the strobe DSV1 shown in _FIG . . On the other hand, through the AND circuit 15, the memory access signal A
is input into the AND circuit 15 along with the memory response SRV0 in FIG.
The transceiver 2 ₁ is driven through the memory access signal 3 and the memory access signal is sent to the common bus 3 . and memory response
With the rising edge of SRV0, processor (1) _1-2 finishes occupying the bus, and at the same time processor (0) _1-1 occupies the bus and outputs address/data.

When processor (0) 1 ₁ 's own DMA request occurs, flip-flop (FF1) 1 at the top of Fig.
DMA permission DACK3 is input and set to (FF1) 11 of the circuit consisting of flip-flop 1 and flip-flop (FF3) 13, and strobe signal DSV1 is output.
In this case, occupancy of processor (0) ₁₁ is determined and address/data can be output immediately, so bus skew and address decoding time are reduced.
There is no need to specifically guarantee T ₁ ′.

Therefore, as shown in Figure 2~, it outputs the address/data shown in the figure and also outputs its own address/data.
Flip-flop DMA permission DACK3 (FF1)
11, set at the timing shown in the same figure, and synchronized with the memory response SRV0 of the _same figure. The signal is sent to transceiver ₂₁ to drive and control it. Here, in the present invention, according to DSV1 in FIG.
(FF2) 12 in the same figure for setting T ₁ ' time
This means that the setting procedure is omitted, which saves time.

〔Effect of the invention〕

As explained above, according to the present invention, the processor with the highest priority is designated, and control is performed so that the common bus is always assigned to the processor with the highest priority when the other processors are not using the common bus. It is something. As a result, when assigning the common bus to a processor other than the processor with the highest priority, it is necessary to set the strobe time T ₁ ', but after the access is completed, the processor with the highest priority is always assigned to the common bus. , the time T ₁ ' required for the procedure of immediately outputting the address/data and guaranteeing the address can be omitted. Since the common bus is used a large number of times in a processor with a high priority, the accumulation of this time T ₁ ' becomes large, which is useful for reducing the overhead of the processor.

As a result, the waiting time of other processors can also be reduced.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the configuration of the embodiment of the present invention, Fig. 2 is an operational waveform diagram of the embodiment, Fig. 3 is an explanatory diagram of the system of the conventional example, and Fig. 4 is an explanatory diagram of problems in the conventional example. , In the figure, 1 ₁ is a processor (0), 2 ₁ is a transceiver, 3 is a common bus, 10 is a priority determination circuit, 1
1, 12, 13 are flip-flops, 14, 1
6 shows an OR circuit, and 15 shows an AND circuit.

Claims (1)

[Claims] 1. In a multiprocessor system in which a common bus is assigned with priority given to multiple processors, and the processors to which the bus is assigned perform access using the common bus, the processor that is most frequently used among the multiple processors is given the highest priority. A multiprocessor control method characterized in that a means for designating a processor as a priority processor is provided, and the common bus is always assigned to the highest priority processor when the other processors are not using the common bus.