Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0132659B2 - - Google Patents
[go: Go Back, main page]

JPH0132659B2 - - Google Patents

Info

Publication number
JPH0132659B2
JPH0132659B2 JP56084706A JP8470681A JPH0132659B2 JP H0132659 B2 JPH0132659 B2 JP H0132659B2 JP 56084706 A JP56084706 A JP 56084706A JP 8470681 A JP8470681 A JP 8470681A JP H0132659 B2 JPH0132659 B2 JP H0132659B2
Authority
JP
Japan
Prior art keywords
conductor layer
layer
capacitor
scf
rectangular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56084706A
Other languages
Japanese (ja)
Other versions
JPS57199249A (en
Inventor
Kazuhiro Ootani
Hirohei Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP56084706A priority Critical patent/JPS57199249A/en
Publication of JPS57199249A publication Critical patent/JPS57199249A/en
Publication of JPH0132659B2 publication Critical patent/JPH0132659B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/212Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置、特にMOS型半導体装置
の構成素子として用いるコンデンサの構成に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a capacitor used as a component of a semiconductor device, particularly a MOS type semiconductor device.

従来、半導体基板上に、MOS型トランジスタ
とともにコンデンサ素子を設ける場合には、例え
ば、第1図aに示すように、一導電形たとえばn
形シリコン基板1の表面層に(Pウエル)拡散層
よりなる導電体層2を形成した後、絶縁体層3を
介して、多結晶シリコン膜よりなる導電体層4を
形成し、然る後に、絶縁体層5で全面を覆つた
後、導電体層2および導電体層4上にコンタクト
窓を設け、この窓を通して導電体層2および導電
体層4へ一対の電極6と7を付設していた。そし
てこのとき、第1図bの平面図で示すように、導
電体層2と導電体層4のそれぞれを8および9の
電極取り出し部で電極6と7に繋ぎ電位を取つて
いた。第1図aは同bの−′線の断面に相当
するもので、導電体層4はその中央部をlだけ突
出させ、この突出部の取り出し部9で電極7と接
続されている。
Conventionally, when providing a capacitor element together with a MOS transistor on a semiconductor substrate, for example, as shown in FIG.
After forming a conductive layer 2 made of a (P-well) diffusion layer on the surface layer of a shaped silicon substrate 1, a conductive layer 4 made of a polycrystalline silicon film is formed via an insulating layer 3, and then After covering the entire surface with an insulator layer 5, a contact window is provided on the conductor layer 2 and the conductor layer 4, and a pair of electrodes 6 and 7 are attached to the conductor layer 2 and the conductor layer 4 through this window. was. At this time, as shown in the plan view of FIG. 1B, the conductive layer 2 and the conductive layer 4 were connected to the electrodes 6 and 7 at the electrode extraction portions 8 and 9, respectively, to obtain a potential. FIG. 1A corresponds to the cross section taken along the line -' in FIG.

しかしながら、コンデンサの容量値は、導電体
層4と導電体層2との重ね合せの面積に比例し、
絶縁体層3の厚さに反比例するため、このような
構成では導電体層4と導電体層2との合せずれが
生じるごとに重ね合せ部10(クロスハツチで示
す部分)の面積が変動し、容量値が変化すること
になる。一例として第1図bに示す導電体層4の
方形部のX方向の寸法x1を30μm、Y方向の寸法
y1を30μmとし、導電体層4の電位取り出し部用
突出部と導電体層2との重なり部10のX方向の
寸法をx28μm、Y方向の寸法y2を10μmとした
時、マスクガラス乾板およびマスク合せのズレで
導電体層4の導電体層2に対する相対的位置がX
方向に±1μmズレた場合には重ね合せ部10の
面積は〓1.02%変化し、したがつてコンデンサと
しての容量値も〓1.02%変化する。
However, the capacitance value of the capacitor is proportional to the overlapping area of the conductor layer 4 and the conductor layer 2,
Since it is inversely proportional to the thickness of the insulating layer 3, in such a configuration, the area of the overlapping portion 10 (portion shown by cross hatching) changes every time misalignment occurs between the conductive layer 4 and the conductive layer 2. The capacitance value will change. As an example, the dimension x 1 in the X direction of the rectangular part of the conductive layer 4 shown in Figure 1b is 30 μm, and the dimension in the Y direction
When y 1 is 30 μm, the dimension in the X direction of the overlapping portion 10 between the protrusion for the potential extraction portion of the conductor layer 4 and the conductor layer 2 is x 2 8 μm, and the dimension y 2 in the Y direction is 10 μm, the mask Due to misalignment of the glass dry plate and mask, the relative position of the conductor layer 4 to the conductor layer 2 may be
If there is a deviation of ±1 μm in the direction, the area of the overlapping portion 10 changes by 1.02%, and therefore the capacitance value as a capacitor also changes by 1.02%.

次にMOSFETとともに内蔵されたコンデンサ
を用いて回路が構成されるスイツチト・キヤパシ
タ・フイルタ(以下SCFと略す)を例にとつて述
べる。
Next, we will discuss a switched capacitor filter (hereinafter abbreviated as SCF), whose circuit is constructed using a MOSFET and a built-in capacitor.

SCFでは、高速でスイツチングされる小さな容
量で等価的にシユミレートされた抵抗を用いて等
価RCアクテイブ・フイルタを構成している。
In the SCF, an equivalent RC active filter is constructed using a resistor that is equivalently simulated with a small capacitance that is switched at high speed.

SCFの基本構成である積分器の例を第2図aに
示す。第2図aにおいてノード112の電位を
Vio、キヤパシタ114の容量値をC1とし、スイ
ツチ111のノード112とノード113との切
換周期を1/cとすると、ノード112とノード1 13の間には、平均してi=C1・Viocの電流
が流れる。したがつて、ノード112(Vio)と
ノード113(演算増幅器17の入力)の間に
は、Req=Vio/i=1/C1cの抵抗を有すること と同等であり、クロツク周波数cが通過周波数に
対して十分に高い場合には、第2図aの回路は第
2図bの回路で抵抗118の抵抗値をReqとした
回路と等価である。
An example of an integrator, which is the basic configuration of an SCF, is shown in Figure 2a. In FIG. 2a, the potential of node 112 is
V io , the capacitance value of the capacitor 114 is C 1 , and the switching period between nodes 112 and 113 of the switch 111 is 1/ c , then on average, i=C 1 between the nodes 112 and 113.・A current of V ioc flows. Therefore, between node 112 (V io ) and node 113 (input of operational amplifier 17), it is equivalent to having a resistance of R eq =V io /i=1/C 1 · c , and the clock When the frequency c is sufficiently higher than the passing frequency, the circuit of FIG. 2a is equivalent to the circuit of FIG. 2b, where the resistance value of the resistor 118 is Req.

第2図aにおいて、キヤパシタ115の容量値
をC2、ノード116の電位をVOUTとした時、そ
の伝達関数はVOUT/Vioc/S・C1/C2である。
この第2図aのスイツチト・キヤパシタ利用の積
分器は、c・(C1/C2)に等しいゲインを持ち、
そのフアクターはアクテイブ・フイルタ回路にお
いて、バンド幅またはピーキング周波数としての
パラメータを決定するものである。よつて、SCF
回路の重要な特性はスイツチの切換周波数cが一
定の場合、コンデンサC1,C2の容量比だけで決
定されることになり、このことが、SCFの確度と
安定度が高いという最大の優位性となつていた。
In FIG. 2a, when the capacitance value of the capacitor 115 is C 2 and the potential of the node 116 is V OUT , the transfer function is V OUT /V io = c /S·C 1 /C 2 .
This switched-capacitor integrator in Figure 2a has a gain equal to c ·(C 1 /C 2 ),
The factor determines the parameters such as bandwidth or peaking frequency in the active filter circuit. So, SCF
When the switching frequency c of the switch is constant, the important characteristics of the circuit are determined only by the capacitance ratio of capacitors C 1 and C 2 , and this gives the SCF its greatest advantage of high accuracy and stability. It had become a sexual thing.

しかるに、このフイルタの特性を決定する要因
となるコンデンサC1,C2の容量値の変動は、
SCFの優位性を損なうばかりでなく、SCFの特性
そのものを変化させることになる。一例として、
第2図aの構成の積分器を利用したバンド・パ
ス・フイルタでは、通過帯域の中心周波数pは、
pc/2π・C1/C2であるが、積分器の構成素子
であるキヤパシタC1あるいはC2のどちらか一方
の容量値が、たとえば1%変化した場合には、バ
ンド・パス・フイルタの中心周波数pも1%変動
することになる。
However, the fluctuation in the capacitance values of capacitors C 1 and C 2 , which is a factor that determines the characteristics of this filter, is
This not only impairs the superiority of SCF, but also changes the characteristics of SCF itself. As an example,
In a band pass filter using an integrator with the configuration shown in Figure 2a, the center frequency p of the passband is
p = c / 2π・C 1 /C 2 , but if the capacitance value of either capacitor C 1 or C 2 , which is a constituent element of the integrator, changes by, for example, 1%, the band pass The center frequency p of the filter will also vary by 1%.

よつて、第1図a,bで示すような構成のコン
デンサをSCFの構成素子として使つた場合には、
たとえばバンド・パス・フイルタではその中心周
波数が設計値から、たとえば1%ズレるといつた
問題が起るなど、SCFとして、そ信頼性ならびに
歩留りの低下さらにはコストアツプといつた問題
点が続出し、このようなコンデンサを用いること
はできなかつた。
Therefore, when capacitors with the configurations shown in Figure 1 a and b are used as constituent elements of the SCF,
For example, in band pass filters, problems occur when the center frequency deviates by, say, 1% from the design value, and SCFs continue to have problems such as decreased reliability and yield, as well as increased costs. It was not possible to use such a capacitor.

本発明は、これらの欠点を除去し、高精度のコ
ンデンサを提供することを目的とし、たとえば高
精度のSCFを構成しようとするものである。
The present invention aims to eliminate these drawbacks and provide a high-precision capacitor, for example, to construct a high-precision SCF.

以下、本発明の実施例を図面を用いて詳細に説
明する。第3図a,bは本発明を適用した一実施
例である。第3図において、第1図と同一部分に
は同一番号を付す。2および4は導電層で、この
2つの導電層の重ね合せ部分で容量が形成され
る。8および9はそれぞれ導電層2および4の電
位取り出し部であり、19は本発明を適用して設
けた電極4の突部で、取り出し部9の設けられた
突出部と反対の側に形成されており、すなわち突
出部と幅が同一寸法で対向する位置に形成してあ
る。したがつて、この構成によれば、重なり部1
0に対向して、19と2の重なり部20を有する
ことになる。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIGS. 3a and 3b show an embodiment to which the present invention is applied. In FIG. 3, the same parts as in FIG. 1 are given the same numbers. 2 and 4 are conductive layers, and a capacitor is formed at the overlapping portion of these two conductive layers. 8 and 9 are potential extraction parts of the conductive layers 2 and 4, respectively, and 19 is a protrusion of the electrode 4 provided by applying the present invention, which is formed on the opposite side to the protrusion where the extraction part 9 is provided. In other words, the protrusion and the width are formed at opposing positions with the same dimension. Therefore, according to this configuration, the overlapping portion 1
It has an overlapping part 20 of 19 and 2 opposite to 0.

この構造をもつた容量では、マスクガラス乾板
やマスク合せのズレにより、2と4の相対位置
が、例えばX方向にズレた場合、10および20
それぞれ面積は変化するが、その変化量は絶対値
が同一で極性が異なるから、10と20の面積和
の総変化量は零で、面積和は常に一定である。よ
つて容量値も一定である。
In a capacitor with this structure, if the relative positions of 2 and 4 shift in the X direction due to a shift in the mask glass dry plate or mask alignment, for example, 10 and 20
Although the area changes, the amount of change has the same absolute value and different polarity, so the total amount of change in the sum of areas of 10 and 20 is zero, and the sum of areas is always constant. Therefore, the capacitance value is also constant.

また本発明の構成では、X、Y方向のズレだけ
でなく、2つの導電層間の回転によるズレに対し
ても、容量値は不変である。したがつて、電位取
り出し部と同一幅の突出部を対向する位置に設け
た構造とすることにより、マスク合せ乾板やマス
ク合せのズレに影響されない、設計値通りの不変
容量を形成することができる。
Furthermore, in the configuration of the present invention, the capacitance value remains unchanged not only due to deviations in the X and Y directions but also due to rotational deviations between the two conductive layers. Therefore, by creating a structure in which a protruding portion having the same width as the potential extraction portion is provided at an opposing position, it is possible to form a constant capacitance according to the designed value, which is not affected by the misalignment of the mask-aligned dry plate or mask alignment. .

また第4図は本発明の他の実施例であり、同一
面積の単位キヤパシタを規則正しく配列して並列
接続することにより、単位キヤパシタのn倍の容
量値のキヤパシタを構成しており、複数の電位取
り出し部9x(x=a〜d)の形成された突出部
と、同一幅の突き出し19x(x=a〜d)を、
それぞれ9xと対向する位置に設けている。
FIG. 4 shows another embodiment of the present invention, in which a capacitor with a capacitance value n times that of the unit capacitor is constructed by regularly arranging unit capacitors of the same area and connecting them in parallel. The protrusion 19x (x=a to d) having the same width as the protrusion in which the take-out part 9x (x=a to d) is formed,
Each is provided at a position facing 9x.

このような、本発明の構成の容量を、たとえば
SCFに適用した場合には、設計値通りの特性の
SCFが実現でき、マスク合せ乾板やマスク合せの
ズレに影響されずに、高精度、高信頼性のSCFを
安定して低コストで提供することができる。ここ
で、実施例は、たとえば、導電体層2をn形半導
体基板に形成したPウエル拡散層または導電体層
4を多結晶シリコンとして構成される容量素子に
ついて、図面で説明してきたが、両電極は半導体
基板上の絶縁膜上に形成されたものでもよい。す
なわち電極の構成はPウエル拡散層と多結晶シリ
コン膜層に限らず、多結晶シリコン膜層とアルミ
ニウム膜層または第1多結晶シリコン膜層と第2
多結晶シリコン膜層のように、二つの導電層が、
導電層−絶縁層−導電層構成されるものであれば
よい。このようないずれの構成においても、電位
取り出し部に対向して幅が同一とされた突出部を
形成すれば本発明の効果を発揮しうる。
The capacity of such a configuration of the present invention is, for example,
When applied to SCF, it is possible to maintain the characteristics as designed.
It is possible to realize SCF, and it is possible to stably provide high-precision, highly reliable SCF at low cost without being affected by misalignment of mask-aligned dry plates or mask alignment. Here, in the embodiment, a capacitor element in which the conductor layer 2 is formed of a P-well diffusion layer formed in an n-type semiconductor substrate or the conductor layer 4 is formed of polycrystalline silicon has been described with reference to the drawings. The electrode may be formed on an insulating film on a semiconductor substrate. In other words, the structure of the electrode is not limited to a P-well diffusion layer and a polycrystalline silicon film layer, but also a polycrystalline silicon film layer and an aluminum film layer, or a first polycrystalline silicon film layer and a second polycrystalline silicon film layer.
Two conductive layers, such as polycrystalline silicon film layers,
Any structure may be used as long as it has a conductive layer-insulating layer-conductive layer structure. In any of these configurations, the effects of the present invention can be achieved by forming a protruding portion having the same width opposite the potential extraction portion.

以上説明したように、本発明に示す構成をとれ
ば、半導体装置内に、ガラスマスク乾板やマスク
合せ等の機械的なズレに影響されることなく設計
値通りの定容量を形成することができる。また、
電極取り出し部および突出部形成時の食刻作用を
考慮した場合は、両者の形状、面積、周辺長を同
一にした場合が最も定容量を形成できることが明
らかである。そして、本発明の構成の定容量をた
とえば、スイツチト・キヤパシタ・フイルタのよ
うに、高精度、高安定の容量を必要とする半導体
集積回路に用いれば、たとえばSCFの特性を設計
値通りに常に安定に実現できるから、その結果と
して、SCFの精度、信頼性および歩留りを高め、
低コストでSCFを提供できる等の利点があり、そ
の工業的価値は大である。
As explained above, by adopting the configuration shown in the present invention, a constant capacitance as designed can be formed in a semiconductor device without being affected by mechanical misalignment of glass mask dry plates, mask alignment, etc. . Also,
When considering the etching effect when forming the electrode extraction portion and the protrusion, it is clear that a constant capacitance can be formed best when the shape, area, and peripheral length of the electrode extraction portion and the protrusion portion are made the same. If the constant capacitance configured according to the present invention is used in a semiconductor integrated circuit that requires a highly accurate and highly stable capacitance, such as a switched capacitor filter, the characteristics of the SCF will always be stable as designed values. As a result, the accuracy, reliability, and yield of SCF can be improved.
It has the advantage of being able to provide SCF at low cost, and has great industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは従来の容量素子の平面、断面図
で、aはbの−′線断面図、第2図aはスイ
ツチト・キヤパシタ利用の積分器の構成図、第2
図bはRC積分器の構成図、第3図a,bは本発
明の一実施例の容量素子の概略平面図、第4図は
本発明の容量素子の他の実施例の概略平面図であ
る。 1……シリコン基板、2……導電体層(Pウエ
ル拡散層)、3……絶縁体層(二酸化シリコン
膜)、4……導電体層(多結晶シリコン膜)、5…
…絶縁体層(二酸化シリコン膜)、6,7……ア
ルミニウム電極、8……2の電位取り出し部、9
……4の電位取り出し部、10,20……重なり
部、20……突出部、114……容量値C1のキ
ヤパシタ、115……容量値C2のキヤパシタ。
Figures 1a and b are plane and cross-sectional views of conventional capacitive elements, a is a cross-sectional view taken along the line -' of b, Figure 2a is a block diagram of an integrator using a switched capacitor,
Figure b is a block diagram of an RC integrator, Figures 3a and b are schematic plan views of a capacitive element according to one embodiment of the present invention, and Figure 4 is a schematic plan view of another embodiment of a capacitive element according to the present invention. be. 1...Silicon substrate, 2...Conductor layer (P well diffusion layer), 3...Insulator layer (silicon dioxide film), 4...Conductor layer (polycrystalline silicon film), 5...
... Insulator layer (silicon dioxide film), 6, 7 ... Aluminum electrode, 8 ... Potential extraction part of 2, 9
. . . potential extraction portion of 4, 10, 20 . . . overlapping portion, 20 . . . protruding portion, 114 .

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板面に形成した第1の導電体層と、
この第1の導電体層と誘電体層を介して設置され
た第2の導電体層とから構成されるとともに、前
記第2の導電体層は前記第1の導電体層より小な
る面積を有する主体部分と、この主体部分の一方
の側に形成され前記第1の導電体層よりも外側に
まで延びる第1の長方形突出部と、この第1の長
方形突出部と反対の側に形成され前記第1の導電
体層よりも外側にまで延びる第2の長方形突出部
とから成り、前記第1の長方形突出部は前記第1
の導電体層の外側において電極と接続され、前記
第1および第2の長方形突出部は同一の幅を有す
る容量素子を含むことを特徴とする半導体装置。
1 a first conductor layer formed on a semiconductor substrate surface;
It is composed of this first conductor layer and a second conductor layer installed through a dielectric layer, and the second conductor layer has a smaller area than the first conductor layer. a first rectangular protrusion formed on one side of the main body portion and extending outward beyond the first conductor layer; and a first rectangular protrusion formed on the opposite side of the first rectangular protrusion. a second rectangular protrusion extending outward from the first conductor layer, and the first rectangular protrusion extends beyond the first conductor layer.
A semiconductor device, characterized in that the first and second rectangular protrusions include a capacitive element connected to an electrode on the outside of a conductor layer, and the first and second rectangular protrusions have the same width.
JP56084706A 1981-06-01 1981-06-01 Semiconductor device Granted JPS57199249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56084706A JPS57199249A (en) 1981-06-01 1981-06-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56084706A JPS57199249A (en) 1981-06-01 1981-06-01 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57199249A JPS57199249A (en) 1982-12-07
JPH0132659B2 true JPH0132659B2 (en) 1989-07-10

Family

ID=13838097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56084706A Granted JPS57199249A (en) 1981-06-01 1981-06-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57199249A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3714672A1 (en) * 1987-05-02 1988-11-17 Telefunken Electronic Gmbh RC LINE
US5006480A (en) * 1988-08-08 1991-04-09 Hughes Aircraft Company Metal gate capacitor fabricated with a silicon gate MOS process

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51874U (en) * 1974-06-18 1976-01-06
JPS6252952B2 (en) * 1979-09-07 1987-11-07 Ei Teii Ando Teii Tekunorojiizu Inc
JPS56112750A (en) * 1980-02-12 1981-09-05 Nec Corp Semiconductor capacitive element
JPS56119670A (en) * 1980-02-22 1981-09-19 Shin Meiwa Ind Co Ltd Position detecting sensor of groove weld line
JPS56153777A (en) * 1980-04-28 1981-11-27 Nec Corp Semiconductor capacity element

Also Published As

Publication number Publication date
JPS57199249A (en) 1982-12-07

Similar Documents

Publication Publication Date Title
US6853534B2 (en) Tunable capacitor
JPH0365016B2 (en)
JPS63308366A (en) Semiconductor integrated circuit
US20160131680A1 (en) Capacitive physical quantity sensor
JPH0132659B2 (en)
JPH0622190B2 (en) Thick film capacitors
JP2752832B2 (en) Semiconductor integrated circuit device
JPS6329962A (en) Semiconductor device
US4208641A (en) Hybrid integrated impedance converter circuit
JPH0590489A (en) Semiconductor integrated circuit
JP2508301B2 (en) Semiconductor integrated circuit
JPH01236721A (en) Ceramic resonator
JPH07202123A (en) Semiconductor coupling capacitor
JPH06103735B2 (en) Semiconductor integrated circuit
JPS6252952B2 (en)
JPH0473960A (en) Integrated circuit
JP2863760B2 (en) Semiconductor device
US4695922A (en) Constant ratio, size insensitive, capacitor structure
JPH0142149B2 (en)
WO2004021439A1 (en) Mim capacitor
JPS6066851A (en) Ic capacitor and manufacture thereof
JP2692401B2 (en) Thin film capacitors
JPH06310657A (en) Semiconductor integrated circuit device
JPS59191368A (en) semiconductor equipment
JP2567121B2 (en) Semiconductor capacitance element