JPH0132666B2 - - Google Patents
Info
- Publication number
- JPH0132666B2 JPH0132666B2 JP55106639A JP10663980A JPH0132666B2 JP H0132666 B2 JPH0132666 B2 JP H0132666B2 JP 55106639 A JP55106639 A JP 55106639A JP 10663980 A JP10663980 A JP 10663980A JP H0132666 B2 JPH0132666 B2 JP H0132666B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- epitaxial layer
- emitter
- conductivity type
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000005192 partition Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/34—Bipolar devices
- H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にエミツタ抵抗を備え
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with an emitter resistor.
従来のエミツタ抵抗を有するトランジスタは第
１図に示す如く、コレクタ領域となるＮ型シリコ
ン半導体基板１とＰ型のベース領域２とＮ型のエ
ミツタ領域３より構成され、エミツタ領域３の拡
散抵抗をエミツタ抵抗として用いていた。しかし
斯る構造ではエミツタ領域３が高不純物濃度であ
り且つあまり大面積とできないのでエミツタ抵抗
の値は高々１Ω程度しか得られず、またエミツタ
拡散のばらつきによつてエミツタ抵抗値がばらつ
く欠点を有していた。 As shown in FIG. 1, a conventional transistor with emitter resistance is composed of an N-type silicon semiconductor substrate 1 serving as a collector region, a P-type base region 2, and an N-type emitter region 3. It was used as an emitter resistance. However, in such a structure, the emitter region 3 has a high impurity concentration and cannot be made very large in area, so the emitter resistance value can only be about 1Ω at most, and it also has the disadvantage that the emitter resistance value varies due to variations in emitter diffusion. Was.
本発明は斯る欠点に鑑みてなされ、従来の欠点
を完全に除去する半導体装置を提供するものであ
る。以下に第２図を参照して本発明の一実施例を
詳述する。 The present invention has been made in view of these drawbacks, and it is an object of the present invention to provide a semiconductor device that completely eliminates the conventional drawbacks. An embodiment of the present invention will be described in detail below with reference to FIG.
本発明に依るトランジスタは第２図に示す如
く、Ｐ型の半導体基板１１と、基板１１表面に設
けられたN+型の埋込み層１２と、基板１１上に
形成されたN-型のエピタキシヤル層１３と、コ
レクタ領域１４となるエピタキシヤル層１３を区
画するＰ型の分離領域１５と、コレクタ領域１４
表面に形成されたＰ型のベース領域１６と、ベー
ス領域１６表面に形成されたＮ型エミツタ領域１
７とエミツタ領域１７と分離領域１５とを接続す
る接続手段１８より構成されている。 As shown in FIG. 2, the transistor according to the present invention includes a P-type semiconductor substrate 11, an N + type buried layer 12 provided on the surface of the substrate 11, and an N - type epitaxial layer formed on the substrate 11. layer 13 , a P-type isolation region 15 that partitions the epitaxial layer 13 that becomes the collector region 14 , and the collector region 14 .
A P-type base region 16 formed on the surface and an N-type emitter region 1 formed on the surface of the base region 16.
7, the emitter region 17, and the isolation region 15.
半導体基板１１は0.015Ωcm以下の低抵抗のＰ
型ウエフア１１０とその上に積層された約10Ωcm
の高抵抗のP-型エピタキシヤル層１１１より形
成され、このエピタキシヤル１１１がエミツタ抵
抗として働く。従つてエミツタ抵抗はエピタキシ
ヤル層１１１の比抵抗および厚みにより容易に設
計できる。具体的には100Ω以下の範囲で任意に
選択できる。 The semiconductor substrate 11 is made of P with a low resistance of 0.015Ωcm or less.
The mold wafer 110 and about 10Ωcm laminated on it
This epitaxial layer 111 functions as an emitter resistor. Therefore, the emitter resistance can be easily designed based on the resistivity and thickness of the epitaxial layer 111. Specifically, it can be arbitrarily selected within the range of 100Ω or less.
埋込み層１２はコレタク領域１４となるエピタ
キシヤル層１３の下にバイポーラ集積回路と同様
にして形成され、コレクタ抵抗を減少させてい
る。 The buried layer 12 is formed under the epitaxial layer 13, which becomes the collector region 14, in the same manner as in a bipolar integrated circuit, and reduces the collector resistance.
エピタキシヤル層１３は基板１１全面に２Ωcm
で15μｍ厚に積層される。 The epitaxial layer 13 has a thickness of 2 Ωcm over the entire surface of the substrate 11.
It is laminated to a thickness of 15 μm.
分離領域１５はエピタキシヤル層１３を貫通し
て半導体基板１１に達する様に拡散して形成さ
れ、コレクタ領域１４となるエピタキシヤル層１
３を完全に分離する。 The isolation region 15 is formed by diffusing to penetrate the epitaxial layer 13 and reach the semiconductor substrate 11, and is formed by diffusing the epitaxial layer 1 which becomes the collector region 14.
Completely separate 3.
コレクタ領域１４のほぼ下面全体に埋込み層１
２は配置されている。またコレクタ領域１４表面
から埋込み層１２に達する様にN+型のコレクタ
コンタクト領域１９が形成され、コレクタ飽和電
圧を低減させている。 A buried layer 1 is formed on almost the entire lower surface of the collector region 14.
2 is placed. In addition, an N + type collector contact region 19 is formed from the surface of the collector region 14 to the buried layer 12 to reduce the collector saturation voltage.
ベースおよびエミツタ領域１６，１７は埋込み
層１２上のコレクタ領域１４表面に形成されてい
る。 Base and emitter regions 16 and 17 are formed on the surface of collector region 14 on buried layer 12.
エピタキシヤル層１３表面にはシリコン酸化膜
２０が形成され、コレクタコンタクト領域１９ベ
ース領域１７および分離領域１５上の酸化膜２０
にコンタクト孔が形成される。そしてコレクタ電
極２１およびベース電極２２を夫々コレクタコン
タクト領域１９とベース領域１６にオーミツク接
触する様に蒸着アルミニウムを用いて酸化膜２０
上に形成し、同時に接続手段１８もその両端をエ
ミツタ領域１７および分離領域１５にオーミツク
接触させて酸化膜２０上に延在させて形成する。
またエミツタ電極２３は半導体基板１１のウエフ
ア１１０主面にオーミツク接触させて設ける。 A silicon oxide film 20 is formed on the surface of the epitaxial layer 13, and an oxide film 20 is formed on the collector contact region 19, base region 17, and isolation region 15.
A contact hole is formed in the. Then, an oxide film 20 is formed using vapor-deposited aluminum so that the collector electrode 21 and the base electrode 22 are in ohmic contact with the collector contact region 19 and the base region 16, respectively.
At the same time, connecting means 18 is also formed extending over oxide film 20 with both ends thereof in ohmic contact with emitter region 17 and isolation region 15.
Further, the emitter electrode 23 is provided in ohmic contact with the main surface of the wafer 110 of the semiconductor substrate 11.
斯る本発明のトランジスタではエミツタ電極２
３を半導体基板１１から取り出す構造にしてエミ
ツタ抵抗を半導体基板１１で形成することを特徴
としている。この結果エミツタ領域１７とエミツ
タ抵抗を完全に独立できるためエミツタ領域１７
の形成に何ら規制されることなくエミツタ抵抗を
任意に且つ大きく設定できる利点を有する。 In such a transistor of the present invention, the emitter electrode 2
3 is taken out from the semiconductor substrate 11, and the emitter resistor is formed from the semiconductor substrate 11. As a result, the emitter region 17 and the emitter resistor can be completely independent, so the emitter region 17
It has the advantage that the emitter resistance can be arbitrarily set to a large value without any restrictions on the formation of the emitter.
第３図に本発明に依るトランジスタのIc−hfe
特性を示す。第３図で実線はエミツタ抵抗が0.5
Ωの従来のトランジスタであり、点線は本発明の
エミツタ抵抗100Ωのトランジスタである。第３
図から明らかな様に従来のトランジスタでは大電
流でのhfeの減少がゆるやかであるため電流制限
機能が悪いのに対して本発明のトランジスタは
hfeを急減できるので良好な電流制限機能を実現
できる。また本発明のトランジスタはこの特性で
非常に破壊に対しても強いものとなる。 Figure 3 shows the Ic-hfe of the transistor according to the present invention.
Show characteristics. In Figure 3, the solid line indicates emitter resistance of 0.5.
The dotted line is a conventional transistor with an emitter resistance of 100 Ω, and the dotted line is a transistor with an emitter resistance of 100 Ω. Third
As is clear from the figure, in the conventional transistor, hfe decreases slowly at large currents, so the current limiting function is poor, whereas the transistor of the present invention has a poor current limiting function.
Since hfe can be rapidly reduced, good current limiting function can be achieved. Furthermore, this characteristic makes the transistor of the present invention extremely resistant to destruction.
第１図は従来例を説明する断面図、第２図は本
発明を説明する断面図、第３図は従来と本発明の
比較をする特性図である。
主な図番の説明、１１は半導体基板、１２は埋
込み層、１３はエピタキシヤル層、１４はコレク
タ領域、１５は分離領域、１６はベース領域、１
７はエミツタ領域、１８は接続手段である。
FIG. 1 is a sectional view for explaining a conventional example, FIG. 2 is a sectional view for explaining the present invention, and FIG. 3 is a characteristic diagram for comparing the conventional example and the present invention. Explanation of main figure numbers: 11 is a semiconductor substrate, 12 is a buried layer, 13 is an epitaxial layer, 14 is a collector region, 15 is an isolation region, 16 is a base region, 1
7 is an emitter region, and 18 is a connecting means.
Claims (1)
れた同導電型の第１のエピタキシヤル層と該第１
のエピタキシヤル層表面に形成された逆導電型の
第２のエピタキシヤル層と該第２のエピタキシヤ
ル層を貫通および前記第１のエピタキシヤル層に
到達しコレクタ領域となる前記第２のエピタキシ
ヤル層を区画する一導電型の分離領域と前記コレ
クタ領域表面に形成された一導電型のベース領域
と該ベース領域表面に形成された逆導電型のエミ
ツタ領域とを具備し、前記エミツタ領域と分離領
域とを接続手段で接続して前記第１のエピタキシ
ヤル層をエミツタ抵抗とすることを特徴とする半
導体装置。1 A semiconductor substrate of one conductivity type, a first epitaxial layer of the same conductivity type formed on the surface of the substrate, and a first epitaxial layer of the same conductivity type formed on the surface of the substrate.
a second epitaxial layer of opposite conductivity type formed on the surface of the epitaxial layer; and the second epitaxial layer that penetrates the second epitaxial layer and reaches the first epitaxial layer to become a collector region. a separation region of one conductivity type that partitions the layer; a base region of one conductivity type formed on the surface of the collector region; and an emitter region of the opposite conductivity type formed on the surface of the base region, the emitter region being separated from the emitter region. A semiconductor device, characterized in that the first epitaxial layer is connected to the first epitaxial layer by a connecting means, and the first epitaxial layer serves as an emitter resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10663980A JPS5731173A (en) | 1980-08-01 | 1980-08-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10663980A JPS5731173A (en) | 1980-08-01 | 1980-08-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5731173A JPS5731173A (en) | 1982-02-19 |
| JPH0132666B2 true JPH0132666B2 (en) | 1989-07-10 |
Family
ID=14438680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10663980A Granted JPS5731173A (en) | 1980-08-01 | 1980-08-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5731173A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0638471B2 (en) * | 1987-02-09 | 1994-05-18 | 三菱電機株式会社 | Semiconductor device |
| JPH088261B2 (en) * | 1988-11-17 | 1996-01-29 | 三洋電機株式会社 | Semiconductor integrated circuit |
-
1980
- 1980-08-01 JP JP10663980A patent/JPS5731173A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5731173A (en) | 1982-02-19 |
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