JPH0133849B2 - - Google Patents
Info
- Publication number
- JPH0133849B2 JPH0133849B2 JP57050776A JP5077682A JPH0133849B2 JP H0133849 B2 JPH0133849 B2 JP H0133849B2 JP 57050776 A JP57050776 A JP 57050776A JP 5077682 A JP5077682 A JP 5077682A JP H0133849 B2 JPH0133849 B2 JP H0133849B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- bits
- input
- rom
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Programmable Controllers (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は読出専用メモリ（以下ROMと称す）
とフリツプフロツプ（以下FFFと称す）で構成
され該FFの出力が現状態の出力で、これと複数
ビツトの入力条件を該ROMに入力し、その出力
が次の状態の出力となる順序回路に係り、該複数
ビツトのの入力条件の内、所定の１ビツトの状態
により、次の状態の出力を指定出来る場合、
ROMの容量を少さく出来、順序回路を安価に出
来る入力条件セレクタ付順序回路に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a read-only memory (hereinafter referred to as ROM)
This circuit consists of a flip-flop (hereinafter referred to as FFF), and the output of the FF is the output of the current state, and this and the input conditions of multiple bits are input to the ROM, and the output becomes the output of the next state. , if the output of the next state can be specified by the state of a predetermined one bit among the input conditions of the plurality of bits,
This invention relates to a sequential circuit with an input condition selector that can reduce the capacity of ROM and make the sequential circuit inexpensive.
(b) 従来技術と問題点
第１図は従来例の順序回路のブロツク図であ
る。(b) Prior art and problems FIG. 1 is a block diagram of a conventional sequential circuit.
図中、１はROM、２０はFF、１〜ＮはＮビツ
トの入力条件、Ａは現状態の出力、Ｂは次の状態
の出力を示す。 In the figure, 1 indicates ROM, 20 indicates FF, 1 to N indicate N-bit input conditions, A indicates the output of the current state, and B indicates the output of the next state.
順序回路としては、現状態の出力Ａ及び次の状
態の出力はｎビツトで構成されており、又、入力
条件はＮビツトで構成されている。又現状態の出
力Ａと、Ｎビツトの入力条件をROM１０に入力
すると、ROM１０の出力Ｂは次の状態を示すよ
うになつており、クロツクにより、FF２０に入
力した信号が次々と出力され、出力が順次状態遷
移するようになつている。 As a sequential circuit, the output A of the current state and the output of the next state are composed of n bits, and the input condition is composed of N bits. Also, when the current state output A and the N-bit input condition are input to the ROM 10, the output B of the ROM 10 indicates the next state, and the clock causes the signals input to the FF 20 to be output one after another. is designed to undergo sequential state transitions.
この動作の為にはROM１０の容量は、入力と
しては（出力Ａの信号のビツト数）＋Ｎ（入力条件
のビツト数）ビツトで、出力としてはｎ（出力Ｂ
の信号のビツト数）ビツトであるので、ｎ×
2(n+N)ビツト必要となり、入力条件ビツト数Ｎが
多くなると大容量のROM又は多数のROMが必
要になり、高価となり、ひいては順序回路が高価
となる欠点がある。 For this operation, the capacity of the ROM 10 is (number of bits of output A signal) + N (number of bits of input condition) bits as input, and n (number of bits of output B) as output.
Since the number of bits of the signal is n×
2 (n+N) bits are required, and as the number N of input condition bits increases, a large capacity ROM or a large number of ROMs are required, which is expensive, and the sequential circuit has the drawback of becoming expensive.
(c) 発明の目的
本発明の目的は、上記の欠点をなくし、複数ビ
ツトの入力条件の内、所定の１ビツトの状態によ
り、次の状態の出力を指定出来る場合、ROMの
容量を小さく出来、順序回路を安価に出来る入力
条件セレクタ付順序回路の提供にある。(c) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to reduce the capacity of the ROM when the next state of output can be specified by the state of a predetermined one bit among the input conditions of multiple bits. An object of the present invention is to provide a sequential circuit with an input condition selector that can be manufactured at low cost.
(d) 発明の構成
本発明は上記の目的を達成するために、ROM
とFFで構成され、該FFの出力が現状態の出力
で、これと、複数ビツトの入力条件を、該ROM
に入力し、その出力が次の状態の出力となる順序
回路において、該複数ビツトの入力条件の中から
所定の１ビツトを選択するセレクタと、この選択
をするための選択信号を出力する手段を該ROM
に設け、選択された１ビツトを該ROMの入力条
件とすることにより該ROMの容量を大巾に減少
出来ることを特徴とする。(d) Structure of the invention In order to achieve the above object, the present invention provides a ROM
The output of the FF is the current state output, and the input conditions of multiple bits are input to the ROM.
A sequential circuit whose output is the output of the next state includes a selector for selecting a predetermined one bit from among the input conditions of the plurality of bits, and means for outputting a selection signal for making this selection. The ROM
It is characterized in that the capacity of the ROM can be greatly reduced by providing one selected bit as an input condition for the ROM.
(e) 発明の実施例
以下本発明の１実施例につき図に従つて説明す
る。第２図は本発明の実施例の入力条件セレクタ
付順序回路のブロツク図である。(e) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a sequential circuit with an input condition selector according to an embodiment of the present invention.
図中第１図と同一機能のものは同一記号で示
す。１０′はROM、２０′はFF、３０はセレクタ
を示す。 Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 10' is a ROM, 20' is an FF, and 30 is a selector.
入力条件はＮビツトで構成されていても、其の
内の１ビツトの状態を見て、次の状態の出力を指
定出来る場合が非常に多い。本発明はこのような
場合に対処するものである。 Even if the input condition consists of N bits, there are many cases in which the output of the next state can be specified by looking at the state of one of the bits. The present invention deals with such cases.
ROM１０′には現状態において、次の状態を
決定するための必要な条件としてＮビツトの入力
条件のうちどのビツト（例えば入力条件１〜Ｎの
中２のビツト）を選択するかの選択信号を出力出
来るようにしておく。この選択信号と入力条件と
をセレクタ３０に入力することにより、Ｎビツト
の入力条件の内から、所望の１ビツトを、セレク
タ３０から出力させる。この１ビツトをROM１
０′に入力すると、この１ビツトが０か１かで、、
次の状態の出力を指定出来る。 The ROM 10' stores a selection signal for selecting which bit (for example, bit 2 among input conditions 1 to N) of the N bits of input conditions is selected as a necessary condition for determining the next state in the current state. Make it possible to output. By inputting this selection signal and the input conditions to the selector 30, a desired one bit out of the N bits of input conditions is outputted from the selector 30. This 1 bit is ROM1
When inputting to 0', whether this 1 bit is 0 or 1,
You can specify the output of the next state.
このようにすると、ROM１０′への入力ビツ
ト数は、現状態出力Ａのｎビツトと上記の１ビツ
トの和、ｎ＋１ビツトとなり、又選択信号は、入
力条件のＮビツトの内の１つを選択すればよいの
でlog2Nビツトでよく、ROM１０′の出力は（ｎ
＋log2N）ビツトとなる。従つてROM１０′の容
量は（ｎ＋log2N）×2(n+1)となり、、入力条件Ｎビ
ツトのＮの増加によるROM１０′の容量の増加
は、従来のものよりはるかに少さくなるし、Ｎが
大きい程その差は大きい。又Ｎが少さくても、従
来のものよりは少さい。又入力条件のビツト数が
多ければ、ROMを作る段階でROMのアドレス
空間の多数個所に、同じ状態出力を設定する必要
があり手間がかかるが、この場合は１個所ですむ
ので手間がかからない。又ROMの容量増加分と
セレクタと比較した場合値段としてもセレクタの
方がはるかに安価である。 In this way, the number of input bits to the ROM 10' will be the sum of the n bits of the current state output A and the above 1 bit, or n+1 bits, and the selection signal will select one of the N bits of the input condition. Therefore, log 2 N bits are enough, and the output of ROM10' is (n
+log 2 N) bits. Therefore, the capacity of the ROM 10' is (n+log 2 N)×2 (n+1) , and the increase in the capacity of the ROM 10' due to an increase in N in the input condition N bits is much smaller than in the conventional case. The larger N is, the larger the difference is. Also, even if N is small, it is smaller than the conventional one. Also, if the number of bits in the input condition is large, it is necessary to set the same status output at many locations in the ROM's address space when creating the ROM, which takes time and effort, but in this case, it only needs to be set at one location, so there is no need for effort. Also, when comparing the increased capacity of ROM with the selector, the selector is much cheaper in terms of price.
(f) 発明の効果
以上詳細に説明した如く、本発明によれば、複
数ビツトの入力条件の内、所定の１ビツトの状態
により、次の状態の出力を指定出来る場合は、
ROMの容量を大巾に少さく出来るので、順序回
路を安価に出来る効果がある。これは入力条件の
ビツト数が多い程上記の効果は大きくなる。(f) Effects of the Invention As explained in detail above, according to the present invention, when the next state of output can be specified by the state of one predetermined bit among the input conditions of multiple bits,
Since the capacity of ROM can be greatly reduced, it has the effect of making sequential circuits cheaper. The above effect becomes greater as the number of bits in the input condition increases.
第１図は従来例の順序回路のブロツク図、第２
図は本発明の実施例の入力条件セレクタ付順序回
路のブロツク図である。
図中１０，１０′は読み出し専用メモリ、２０，
２０′はFF、３０はセレクタ、１〜ＮはＮビツト
の入力条件、Ａは現状態の出力、Ｂは次の状態の
出力を示す。
Figure 1 is a block diagram of a conventional sequential circuit, and Figure 2 is a block diagram of a conventional sequential circuit.
The figure is a block diagram of a sequential circuit with an input condition selector according to an embodiment of the present invention. In the figure, 10, 10' are read-only memories, 20,
20' is an FF, 30 is a selector, 1 to N are N-bit input conditions, A is the output of the current state, and B is the output of the next state.
Claims (1)
れ、該フリツプフロツプの出力が現状態の出力
で、これと、複数ビツトの入力条件を該読出専用
メモリに入力し、その出力が次の状態の出力とな
る順序回路において、該複数ビツトの入力条件の
中から所定の１ビツトを選択するセレクタと、こ
の選択をするための選択信号を出力する手段を該
読出専用メモリに設け、選択された１ビツトを該
読出専用メモリの入力条件とすることを特徴とす
る入力条件セレクタ付順序回路。1 A sequential circuit consisting of a read-only memory and a flip-flop, where the output of the flip-flop is the current state output, this and a multi-bit input condition are input to the read-only memory, and the output becomes the next state output. The read-only memory is provided with a selector for selecting a predetermined one bit from among the input conditions of the plurality of bits and a means for outputting a selection signal for making this selection, and the selected one bit is set as the read-only memory. A sequential circuit with an input condition selector, characterized in that the input condition is an input condition of a memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050776A JPS58168143A (en) | 1982-03-29 | 1982-03-29 | Sequence circuit with input condition selector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050776A JPS58168143A (en) | 1982-03-29 | 1982-03-29 | Sequence circuit with input condition selector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58168143A JPS58168143A (en) | 1983-10-04 |
| JPH0133849B2 true JPH0133849B2 (en) | 1989-07-17 |
Family
ID=12868229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57050776A Granted JPS58168143A (en) | 1982-03-29 | 1982-03-29 | Sequence circuit with input condition selector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58168143A (en) |
-
1982
- 1982-03-29 JP JP57050776A patent/JPS58168143A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58168143A (en) | 1983-10-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5426609A (en) | Read only memory capable of writing data and method of writing/reading data therefor | |
| JP2549601B2 (en) | Register control circuit | |
| JPH0133849B2 (en) | ||
| US4388707A (en) | Memory selecting system | |
| US6092148A (en) | Microcomputer having different memory capacities that can be selected from a common chip layout | |
| JPS5892054A (en) | Programmable chip enable circuit | |
| JPS6148174B2 (en) | ||
| JPH0456492B2 (en) | ||
| JPS61134982A (en) | Memory access circuit | |
| JP2922963B2 (en) | Sequence controller | |
| JPS58218230A (en) | Selecting circuit of delay time | |
| JPH0721799A (en) | Semiconductor memory device | |
| JPS59214329A (en) | Majority decision circuit | |
| JP2001229678A (en) | Semiconductor storage device | |
| JPS59113600A (en) | Highly reliable storage circuit device | |
| JPH0233158B2 (en) | ||
| JPS59207743A (en) | General purpose logical circuit | |
| JP3251265B2 (en) | Memory output control circuit | |
| KR0178005B1 (en) | Memory Self Test Circuit | |
| JPH08180668A (en) | Memory system | |
| JPS59108128A (en) | Adjusting circuit of timing | |
| JPH0944412A (en) | Memory testing circuit | |
| JPH02116087A (en) | Semiconductor memory | |
| JPS6388657A (en) | Memory device | |
| JPH06110819A (en) | Data processing device |