JPH0133952B2 - - Google Patents
Info
- Publication number
- JPH0133952B2 JPH0133952B2 JP55046463A JP4646380A JPH0133952B2 JP H0133952 B2 JPH0133952 B2 JP H0133952B2 JP 55046463 A JP55046463 A JP 55046463A JP 4646380 A JP4646380 A JP 4646380A JP H0133952 B2 JPH0133952 B2 JP H0133952B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- semiconductor
- crystal layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0128—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising multiple local oxidation process steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
Landscapes
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に内
部に埋設絶縁層を有する半導体素子の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor element having an embedded insulating layer therein.
IC、LSI等の半導体装置を微細化し且つ高速化
する為の一つの手段として、所謂ウオールドエミ
ツタ構造が用いられている。第１図は上記ウオー
ルドエミツタ構造の半導体装置の要部を示す断面
図であつて、ｎ型シリコン基板１表面に選択酸化
法を用いて形成されたフイールド酸化膜２により
画定された素子領域に、ｐ型ベース領域３及びｎ
型エミツタ領域４が自己整合法により端部をフイ
ールド酸化膜に接して形成されている。 A so-called wall emitter structure is used as one means for miniaturizing and speeding up semiconductor devices such as ICs and LSIs. FIG. 1 is a cross-sectional view showing the main part of the semiconductor device having the wall emitter structure, and shows an element area defined by a field oxide film 2 formed on the surface of an n-type silicon substrate 1 using a selective oxidation method. , p-type base region 3 and n
A type emitter region 4 is formed by a self-alignment method so that its end portion is in contact with the field oxide film.
従つてウオールドエミツタ構造ではベース・コ
レクタ接合５はベース領域３の側面部には存在せ
ず底面部のみとなるので接合面積が小さくなり接
合容量を減少させることができる。 Therefore, in the wall emitter structure, the base-collector junction 5 does not exist on the side surfaces of the base region 3, but only on the bottom surface, so that the junction area becomes small and the junction capacitance can be reduced.
このようにしてもなおベース・コレクタ接合５
のうち、エミツタ領域４直下の部分以外はなくし
てもよい部分であるから、その分だけ不要な接合
容量が残存する。 Even with this method, the base-collector junction 5
Of these, the portions other than the portion directly below the emitter region 4 can be eliminated, so that unnecessary junction capacitance remains.
そこで第２図に示すようにフイールド酸化膜２
の底部をベース領域の底部に突出せしめたような
埋設絶縁層６を設けることができればベース・コ
レクタ接合５を必要部分にのみ局限することが可
能となり、余分な接合容量を除くことができる等
多くの利点が期待できる。 Therefore, as shown in FIG.
If it is possible to provide a buried insulating layer 6 with the bottom of the base region protruding from the bottom of the base region, it becomes possible to confine the base-collector junction 5 only to the necessary part, and eliminate excess junction capacitance, among other things. Benefits can be expected.
しかし従来の半導体装置の製造方法では半導体
素子内部に埋設絶縁層を設けることはできなかつ
た。 However, with conventional semiconductor device manufacturing methods, it has not been possible to provide a buried insulating layer inside a semiconductor element.
本発明の目的は、内部に埋設絶縁層を有する半
導体装置の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a semiconductor device having an embedded insulating layer therein.
本発明の半導体装置の特徴は、一導電型の半導
体基板表面に高濃度の反対導電型不純物を含む埋
込層と該埋込層より低濃度の反対導電型不純物を
含む半導体の単結晶層を順次形成する工程と、所
定位置に設けられた開口部を有する絶縁層を該単
結晶層表面上に形成する工程と、該単結晶層表面
上および該絶縁層表面上に半導体材料より成る薄
層を形成して該絶縁層を埋め込む工程と、該薄層
にレーザービームまたは電子ビームを照射して該
薄層を半導体結晶層に変換する工程と、該半導体
結晶層の表面から一導電型の不純物を導入して前
記開口部における該半導体結晶層の前記絶縁層の
厚さの範囲内に前記単結晶層と第１のPN接合を
生じる一導電型の不純物領域を形成する工程と、
該半導体結晶層の所定領域に反対導電型の不純物
を導入して該一導電型の不純物領域と第２のPN
接合を生じる反対導電型の不純物領域を形成する
工程とを含むことにある。 A feature of the semiconductor device of the present invention is that a buried layer containing impurities of the opposite conductivity type at a high concentration and a single crystal layer of a semiconductor containing impurities of the opposite conductivity type at a lower concentration than the buried layer are formed on the surface of a semiconductor substrate of one conductivity type. a step of forming an insulating layer having an opening provided at a predetermined position on the surface of the single crystal layer; and a thin layer made of a semiconductor material on the surface of the single crystal layer and the surface of the insulating layer. a step of irradiating the thin layer with a laser beam or an electron beam to convert the thin layer into a semiconductor crystal layer; and a step of removing impurities of one conductivity type from the surface of the semiconductor crystal layer. forming an impurity region of one conductivity type that forms a first PN junction with the single crystal layer within the thickness of the insulating layer of the semiconductor crystal layer in the opening by introducing
An impurity of opposite conductivity type is introduced into a predetermined region of the semiconductor crystal layer to form an impurity region of one conductivity type and a second PN.
forming an impurity region of opposite conductivity type to form a junction.
以下本発明の半導体装置の製造方法を一実施例
により説明する。 The method for manufacturing a semiconductor device according to the present invention will be explained below using one embodiment.
第３図は本発明の一実施例をその工程の順に示
す要部断面図である。 FIG. 3 is a sectional view of a main part showing an embodiment of the present invention in the order of its steps.
第３図ａは通常用いられるシリコン基板１１を
示す図で、１２はｐ型のシリコン支持板、１３は
n+型埋込層、１４はｎ型エピタキシヤル成長層
である。 FIG. 3a is a diagram showing a commonly used silicon substrate 11, where 12 is a p-type silicon support plate, and 13 is a p-type silicon support plate.
The n + type buried layer 14 is an n type epitaxial growth layer.
上記シリコン基板１１表面に選択酸化法を用い
て第１の厚い二酸化シリコン（SiO2）層１５を
形成し、島状領域１６，１６′を設ける。上記
SiO2層１５の厚さを前記エピタキシヤル成長層
１４より厚くしておけば島状領域１６，１６′は
他の領域と絶縁分離される。 A first thick silicon dioxide (SiO 2 ) layer 15 is formed on the surface of the silicon substrate 11 using a selective oxidation method, and island regions 16 and 16' are provided. the above
If the thickness of the SiO 2 layer 15 is made thicker than the epitaxial growth layer 14, the island regions 16, 16' can be insulated and isolated from other regions.
なおこの工程で用いる技法は通常の選択酸化法
と何ら異なる点はないが、島状領域１６の大きさ
を形成すべきエミツタ領域の大きさより僅かに大
きい程度とした。 The technique used in this step is no different from the usual selective oxidation method, but the size of the island region 16 was set to be slightly larger than the size of the emitter region to be formed.
次いで同図ｃに示すように前記SiO2層１５表
面を含むシリコン基板１１上にｎ型不純物を含む
シリコン（Si）よりなる薄層１７を形成する。該
薄層１７は化学気相成長（CVD）法、スパツタ
リング法、蒸着法等を用いて形成した多結晶シリ
コン層または非晶質シリコン層であつても、また
場合によつてはエピタキシヤル成長法を用いて島
状領域１４，１４′上は単結晶シリコン層、SiO2
層１５上は多結晶シリコン層とされた膜であつて
もよい。 Next, as shown in FIG. 3c, a thin layer 17 made of silicon (Si) containing n-type impurities is formed on the silicon substrate 11 including the surface of the SiO 2 layer 15. The thin layer 17 may be a polycrystalline silicon layer or an amorphous silicon layer formed using a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, etc., or may be an epitaxial growth method in some cases. A single crystal silicon layer, SiO 2 , is formed on the island regions 14 and 14' using
The layer 15 may be formed of a polycrystalline silicon layer.
次いで上記薄層１７にレーザビームまたは電子
ビームを照射することによりアニールを行ない、
該薄層をシリコン結晶層１７に変換する。 Next, the thin layer 17 is annealed by irradiating it with a laser beam or an electron beam,
The thin layer is converted into a silicon crystal layer 17.
次いで同図ｄに示すように該シリコン結晶層１
７を選択酸化法により選択的に酸化して素子形成
領域を開口部とするフイールド酸化膜１８を形成
する。ここでフイールド酸化膜１８の下には上記
シリコン結晶層１７を残すことなく酸化を行な
い、フイールド酸化膜１８と前記SiO2層１５が
接続するようにする。このように形成されたフイ
ールド酸化膜により画定された素子形成領域に
は、他の領域と絶縁分離されたシリコン結晶層か
らなる島状領域１９，１９′が形成される。 Next, as shown in FIG. d, the silicon crystal layer 1 is
7 is selectively oxidized by a selective oxidation method to form a field oxide film 18 having an opening in the element formation region. Here, oxidation is performed without leaving the silicon crystal layer 17 under the field oxide film 18, so that the field oxide film 18 and the SiO 2 layer 15 are connected. In the element formation region defined by the field oxide film thus formed, island regions 19 and 19' made of a silicon crystal layer are formed insulated and isolated from other regions.
ここで重要なことは島状領域１９は前記島状領
域１６より大きいものとし、島状領域１６とその
側面に接続するSiO2層１５の端部上に跨つて形
成することである。即ち本実施例でか島状領域１
９は形成すべき半導体素子のベース領域に対応す
る大きさとし、島状領域１６はほぼエミツタ領域
に対応する大きさとした。 What is important here is that the island-like region 19 is larger than the island-like region 16 and is formed so as to straddle the end of the SiO 2 layer 15 connected to the island-like region 16 and its side surface. That is, in this embodiment, the island-like region 1
9 has a size corresponding to the base region of the semiconductor element to be formed, and the island-like region 16 has a size almost corresponding to the emitter region.
以上により素子形成領域の底部に突出して形成
された埋設絶縁層を有するシリコン基板１１が得
られた。 As described above, a silicon substrate 11 having a buried insulating layer formed to protrude from the bottom of the element formation region was obtained.
このシリコン基板１１を用いて素子形成を行な
い、同図ｅに示すようなベース領域３の底部に埋
設絶縁層１５を有し、ベース・コレクタ接合５が
ほぼエミツタ領域４の直下の部分のみに局限さ
れ、接合容量を小さくされた半導体装置が得られ
る。 An element is formed using this silicon substrate 11, and has a buried insulating layer 15 at the bottom of the base region 3 as shown in FIG. Thus, a semiconductor device with reduced junction capacitance can be obtained.
その製造工程は通常の方法に従つて進めてよ
い。例えば、島状領域１９にイオン注入法により
ボロン（Ｂ）のようなｐ型不純物を選択的に導入
してベース領域３を形成し、次いでこのベース領
域の前記島状領域１６に対応する部分と島状領域
１９′に燐（Ｐ）のようなｎ型不純物を同じくイ
オン注入法により選択的に導入してエミツタ領域
４及びコレクタ電極形成領域２０を形成する。
こゝで重要なことはベース領域３の底面即ちベー
ス・コレクタ接合５の深さ方向の位置をSiO2層
１５の厚さの範囲内とすることである。 The manufacturing process may proceed according to conventional methods. For example, a p-type impurity such as boron (B) is selectively introduced into the island region 19 by ion implantation to form the base region 3, and then a portion of the base region corresponding to the island region 16 is formed. The emitter region 4 and the collector electrode forming region 20 are formed by selectively introducing an n-type impurity such as phosphorus (P) into the island region 19' by the same ion implantation method.
What is important here is that the bottom surface of the base region 3, that is, the position of the base-collector junction 5 in the depth direction is within the thickness range of the SiO 2 layer 15.
本発明は上記一実施例に限定されることなく、
更に種々変形して実施し得る。 The present invention is not limited to the above embodiment, but
Furthermore, various modifications can be made.
例えば上記一実施例ではウオールドエミツタ構
造のトランジスタを一例として掲げて説明した
が、これは本発明を用いて形成し得る半導体装置
の種類及び構造を限定するものではない。 For example, in the above-mentioned embodiment, a transistor with a wall emitter structure has been described as an example, but this is not intended to limit the type and structure of a semiconductor device that can be formed using the present invention.
また上記一実施例における各領域の導電型をす
べて反対にすることも可能である。 It is also possible to reverse the conductivity types of all the regions in the above embodiment.
更に埋設絶縁層及びフイールド絶縁膜の材質も
通常用いられるものの中から適宜選択してよい。 Furthermore, the materials for the buried insulating layer and the field insulating film may be appropriately selected from commonly used materials.
以上説明したごとく本発明によれば素子内部に
埋設絶縁層を形成することが可能となり、接合容
量の小さい半導体装置が得られる。 As explained above, according to the present invention, it is possible to form a buried insulating layer inside an element, and a semiconductor device with a small junction capacitance can be obtained.
第１図は従来の半導体装置の説明のための要部
断面図、第２図は従来の半導体装置の改良方法の
原理を示す要部断面図、第３図は本発明の半導体
装置の製造方法の一実施例を示す要部断面図であ
る。
３……ベース領域、４……エミツタ領域、５…
…ベース・コレクタ接合、１１……半導体基板、
１５……埋設絶縁層、１６，１６′……島状領域、
１７……半導体材料よりなる薄層、１８……フイ
ールド絶縁膜、１９，１９′……島状領域。
FIG. 1 is a sectional view of a main part for explaining a conventional semiconductor device, FIG. 2 is a sectional view of a main part showing the principle of a method for improving a conventional semiconductor device, and FIG. 3 is a method of manufacturing a semiconductor device of the present invention. FIG. 2 is a cross-sectional view of a main part showing one embodiment of the present invention. 3... Base area, 4... Emitter area, 5...
...Base-collector junction, 11...Semiconductor substrate,
15... Buried insulating layer, 16, 16'... Island-like region,
17... Thin layer made of semiconductor material, 18... Field insulating film, 19, 19'... Island-shaped region.
Claims (1)
電型不純物を含む埋込層と該埋込層より低濃度の
反対導電型不純物を含む半導体の単結晶層を順次
形成する工程と、 所定位置に設けられた開口部を有する絶縁層を
該単結晶層表面上に形成する工程と、 該単結晶層表面上および該絶縁層表面上に半導
体材料より成る薄層を形成して該絶縁層を埋め込
む工程と、 該薄層にレーザービームまたは電子ビームを照
射して該薄層を半導体結晶層に変換する工程と、 該半導体結晶層の表面から一導電型の不純物を
導入して前記開口部における該半導体結晶層の前
記絶縁層の厚さの範囲内に前記単結晶層と第１の
PN接合を生じる一導電型の不純物領域を形成す
る工程と、 該半導体結晶層の所定領域に反対導電型の不純
物を導入して該一導電型の不純物領域と第２の
PN接合を生じる反対導電型の不純物領域を形成
する工程 とを含むことを特徴とする半導体装置の製造方
法。[Claims] 1. On the surface of a semiconductor substrate of one conductivity type, a buried layer containing impurities of the opposite conductivity type at a high concentration and a single crystal layer of a semiconductor containing impurities of the opposite conductivity type at a lower concentration than the buried layer are sequentially formed. forming an insulating layer having openings provided at predetermined positions on the surface of the single crystal layer; and forming a thin layer of a semiconductor material on the surface of the single crystal layer and on the surface of the insulating layer. embedding the insulating layer by irradiating the thin layer with a laser beam or an electron beam to convert the thin layer into a semiconductor crystal layer; and introducing impurities of one conductivity type from the surface of the semiconductor crystal layer. and the single crystal layer and the first layer are formed within the thickness range of the insulating layer of the semiconductor crystal layer in the opening.
forming an impurity region of one conductivity type that causes a PN junction; and introducing an impurity of an opposite conductivity type into a predetermined region of the semiconductor crystal layer to form an impurity region of one conductivity type and a second impurity region.
1. A method of manufacturing a semiconductor device, comprising the step of forming an impurity region of an opposite conductivity type to form a PN junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4646380A JPS56142650A (en) | 1980-04-09 | 1980-04-09 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4646380A JPS56142650A (en) | 1980-04-09 | 1980-04-09 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56142650A JPS56142650A (en) | 1981-11-07 |
| JPH0133952B2 true JPH0133952B2 (en) | 1989-07-17 |
Family
ID=12747853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4646380A Granted JPS56142650A (en) | 1980-04-09 | 1980-04-09 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56142650A (en) |
-
1980
- 1980-04-09 JP JP4646380A patent/JPS56142650A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56142650A (en) | 1981-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5308776A (en) | Method of manufacturing SOI semiconductor device | |
| EP0552671A2 (en) | Isolation technique for silicon germanium devices | |
| JPH0355984B2 (en) | ||
| US3745647A (en) | Fabrication of semiconductor devices | |
| US4131909A (en) | Semiconductor integrated circuit isolated through dielectric material and a method for manufacturing the same | |
| EP0076106A2 (en) | Method for producing a bipolar transistor | |
| KR970011641B1 (en) | Semiconductor device and method of manufacturing the same | |
| EP0051534A2 (en) | A method of fabricating a self-aligned integrated circuit structure using differential oxide growth | |
| US4792837A (en) | Orthogonal bipolar transistor | |
| US5147809A (en) | Method of producing a bipolar transistor with a laterally graded emitter (LGE) employing a refill method of polycrystalline silicon | |
| US5256896A (en) | Polysilicon-collector-on-insulator polysilicon-emitter bipolar transistor | |
| KR950028174A (en) | Bipolar element and its manufacturing method | |
| GB1420676A (en) | Semiconductor devices | |
| US4546537A (en) | Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation | |
| JPH0133952B2 (en) | ||
| JP2869653B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0239091B2 (en) | ||
| JPH06196707A (en) | Manufacture of vertical type insulated-gate transistor | |
| JPH0423828B2 (en) | ||
| KR950008251B1 (en) | Method for manufacturing PSA bipolar device | |
| JP2546651B2 (en) | Method of manufacturing bipolar transistor | |
| JP2524079B2 (en) | Upward structure type bipolar transistor and manufacturing method thereof | |
| JPH0621077A (en) | Semiconductor device and manufacturing method thereof | |
| JPS59191380A (en) | Semiconductor device and manufacture thereof | |
| JPS60244036A (en) | Semiconductor device and manufacture thereof |