JPH0134353B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a minimum inversion interval bit length measuring device for measuring the length of a minimum inversion interval bit signal in a modulated signal read from an information record carrier.

In a reproduction device that reads recorded information from a driving information recording carrier and reproduces the recorded content, such as a digital audio disk (hereinafter referred to as DAD) reproduction device, the modulated signal waveform read from the information recording carrier is measured using a cathode ray tube oscilloscope. The control system of the DAD playback device is adjusted and inspected by detecting jitter from the displayed waveform.

However, it is not easy to detect jitter from the modulated signal waveform.

For example, in the case of a DAD playback device, the EFM (Eight to
Fourteen Modulation method) is used.

Here, the EFM method is a well-known modulation method for converting 8-bit data into 14-bit data.

In a DAD playback device using the EFM modulation method, the minimum inversion interval is is set to a length of 3 bits, and the maximum inversion interval is set to a length of 11 bits. Also as a bitrate
4.3218Mb/sec is adopted. Therefore, the length of one bit is approximately 231 nsec.

On the other hand, a DAD playback device is equipped with a control system necessary to read information from the disk, including a rotation servo system that controls the number of rotations of the disk, and a focus lens relative to the disk surface that reads information from the disk. A focus servo system that controls the position, and a tracking servo that controls the position of the light spot in the disk radial direction so that the light spot focused on the disk information recording surface by the focus lens is located on the center of the track formed by the pits. This is the system.

The pits on the disk are 0.286 μm to 0.322 μm corresponding to the length of 1 bit, and the minimum pit length is 0.858 μm to 0.966 μm for the minimum reversal interval of 3 bits, and the maximum pit length is is set to 3.15 μm to 3.54 μm for the above maximum inversion interval of 11 bits, and there are bits with lengths between this range,
forming a track.

For this reason, the modulated signal detected from the disk (hereinafter, we will explain using a DAD playback device as an example, the detected
The EFM signal) is a 3-bit signal, 4-bit signal, . When this detected EFM signal is displayed on a cathode ray tube oscilloscope, the waveform is a single bit signal that makes up the detected EFM signal, that is, a 3-bit signal, a 4-bit signal,...
If it is triggered, for example, at the rising edge of an 11-bit signal, the result will be as shown in FIG.

However, as mentioned above, even if the control system of the DAD playback device is adjusted and inspected by detecting jitter in the detected EFM signal waveform displayed on a cathode ray tube oscilloscope, as is clear from the waveform shown in FIG. It is not easy, and it not only requires skill to adjust and inspect the control system of the DAD playback device, but also
It will require a long time.

The present invention has been made in view of the above, and is capable of accurately measuring the minimum inversion interval bit length in a modulated signal read from an information record carrier.
It is an object of the present invention to provide a minimum inversion interval bit length measuring device that can be used for adjusting and inspecting the control system of a DAD reproducing device.

The present invention will be explained below using examples.

FIG. 2 is a block diagram of one embodiment of the present invention, and will be explained using an example in which the modulated signal is an EFM signal.

1 is an input terminal to which a detected EFM signal is applied. In one embodiment of the present invention, a zerox detection circuit _2A generates an output pulse when a detected EFM signal is applied through an input terminal 1 and each bit signal component in the detected EFM signal zeroxes in an increasing direction. The zero-cross detection circuit _2B generates an output pulse when each bit signal component in the EFM signal crosses zero in the decreasing direction, the clock pulse oscillator 3 generates a clock pulse with a period of 2nsec, for example, and the output pulse of the zero-cross detection circuit _2A is applied. output from flip-flop 5
a NAND gate 4 to which the output pulse of the zero-cross detection circuit _2B is applied and which applies the output to the flip-flop 5 via the NOR gate 7 to reset the flip-flop 5;
During the period when the Q output of the flip-flop 5 and the clock pulse output from the clock pulse oscillator 3 are applied and the Q output of the flip-flop 5 is generated,
An AND gate 8 whose gate is opened, a counter 9 that counts the number of clock pulses output from the AND gate 8, a display 10 that displays the counted value of the counter 9, and the counted value of the counter 9 is a predetermined value, 405 in this embodiment It is provided with a NAND gate 11 for detecting that the counter 9 has changed, and an OR gate 12 to which the output of the NAND gate 11 is applied to clear the counter 9. 5, the Q output of flip-flop 5 is applied to AND gate 6, and when flip-flop 5 is set, the gate of AND gate 6 is opened and the output pulse of zero-cross detection circuit _2B is applied. It is configured to wait.

The count value of counter 9 detected by NAND gate 11 is set to 405 because counter 9 is
When counting the time of 3.5 bits, that is, setting it to the intermediate time length between a 3-bit signal and the next 4-bit signal, a bit signal with a length of 3.5 bits or more is equal to a 4-bit signal or more. A bit signal having a length of less than 3.5 bits is determined to be a 3-bit signal. Specifically, the period of the clock pulse oscillated by the clock pulse oscillator 3 is 2nsec, and the length of 3.5 bits is 809.847nsec. By the way, the length of a 3-bit signal is 693nsec, which means that when distinguishing between a 3-bit signal and a 4-bit signal or more, a bit signal with a length of 810nsec or more is judged to be a 4-bit or more signal. There is.

Further, in one embodiment of the present invention, an AND gate 13 to which the clock pulses output from the clock pulse oscillator 3 and the output of the flip-flop 5 are applied, and a hold-off counter 14 for counting the clock pulses output from the AND gate 13 are further provided. The output of the hold-off counter 14 is applied to the NAND gate 4 and the OR gate 12, and the NAND gate 4 is closed until the count value of the hold-off counter 14 reaches a predetermined value, and the flip-flop 5 is set. The counter 9 is cleared by a signal that indicates that the hold-off counter 14 has started counting. Further, the count value of the hold-off counter 14 is cleared by the output of the NAND gate 4.

The display 10 is provided with a latch circuit 10-1 for latching the count value of the counter 9.
0 is configured to display the output of the latch circuit 10-1, and the output pulse of the NAND gate 6 is applied to the latch circuit 10-1 as a latch signal.

Note that the count value at which the hold-off counter 14 generates an output is set to a value that allows the display on the display 10 to be read sufficiently.

The operation of one embodiment of the present invention constructed as described above will be explained next.

When the trigger level is reached during the rise of the detected EFM signal applied to input terminal 1, that is, during the rise of each bit signal, zero cross detection circuit _2A
generates an output pulse, which is applied to the NAND gate 4, inverted by the NAND gate 4, and applied to the flip-flop 5, setting the flip-flop 5. With this setting, the Q output of the flip-flop 5 becomes a high potential, the AND gate 8 opens its gate, and the output clock pulse from the clock pulse oscillator 3 is supplied to the counter 9, where the number of clock pulses is counted.

On the other hand, when the bit signal applied to the input terminal 1 falls and reaches the trigger level in the middle of falling, the zero cross detection circuit _2B generates an output pulse. On the other hand, since the NAND gate 6 is opened by the Q output of the flip-flop 5, the output pulse of the zero-cross detection circuit _2B is applied to the flip-flop 5 via the NAND gate 6 and the NOR gate 7, thereby resetting the flip-flop 5. Therefore, AND gate 8 is flip-flop 5
When the Q output of the transistor becomes a low potential, its gate is closed. Therefore, the clock pulse output from the clock pulse oscillator 3 is blocked by the AND gate 8, and the supply of the clock pulse to the counter 9 is stopped.

Also, counter 9, which was counting clock pulses,
When the number of clock pulses reaches a predetermined value, which is 405 in this embodiment, the NAND gate 11 generates an output pulse. This output pulse from NAND gate 11 clears the count value of counter 9 via OR gate 12 and is simultaneously applied to flip-flop 5 via NOR gate 7 to reset flip-flop 5.

Here, the reset of the flip-flop 5 by the output pulse of the NAND gate 11 and the reset of the flip-flop 5 by the output pulse of the zero-cross detection circuit _2B are independent;
is reset by the output pulse of the NAND gate 11 or the output pulse of the zero cross detection circuit _2B , whichever occurs earlier.

Therefore, when the detected EFM signal applied to input terminal 1 is less than 3.5 bits long, NAND gate 11
The zero-cross detection circuit _2B generates an output pulse before the zero-cross detection circuit _2B generates an output pulse, and when the length is 3.5 bits or more, the NAND gate 11 generates an output pulse before the zero-cross detection circuit 2B generates an output pulse. Therefore, it is determined whether the detected EFM signal is a 3-bit signal or a 4-bit signal or more. That is, when the detected EFM signal applied to the input terminal 1 is a 4-bit signal or more, the NAND gate 11 generates an output pulse and the count value of the counter 9 is cleared when the detected EFM signal reaches approximately 3.5 bits in length. , the zero cross detection circuit 2 _B will emit an output pulse with a delay,
This means that the EFM signal being applied to input terminal 1 is determined to be a 4-bit signal or more. In addition, in this case, the output of the NAND gate 6 due to the output pulse of the zero cross detection circuit _2B causes
Even if the latch circuit 10-1 of the display 10 latches the count value of the counter 9, the count value of the counter 9 has already been cleared, so the display 10 shows zero.

Furthermore, when the detected EFM signal applied to input terminal 1 is a 3-bit signal, even if the length of the 3-bit signal fluctuates due to jitter, it will never become longer than 3.5 bits, and NAND gate 11 will output Zero cross detection circuit 2 _B
The flip-flop 5 is reset by the output pulse, and the count value of the counter 9 does not change from the count value representing the length of the 3-bit signal applied to the input terminal 1 in time. At the same time, the output pulse of the zero cross detection circuit _2B is applied to the latch circuit 10-1 of the display 10 via the NAND gate 6, the count value of the counter 9 is latched, and is applied to the latch circuit 10-1 of the display 10. The count value of the counter 9 is latched, and the display 10 displays the count value of the counter 9, that is, the length of the 3-bit signal applied to the input terminal 1.

Furthermore, when the zero cross detection circuit _2B emits an output pulse and the flip-flop 5 is reset,
AND gate 13 opens its gate and hold-off counter 14 counts the clock pulses from clock pulse oscillator 3 from this time on. The hold-off counter 14 outputs a low potential output from the start of counting until it reaches a predetermined count value, and this low potential output closes the gate of the NAND gate 4.
The output pulse of the zero-cross detection circuit _2A , which is output by the subsequently applied detection EFM signal, is not applied to the flip-flop 5. Furthermore, when the count value of the hold-off counter 14 reaches a predetermined value, the output of the hold-off counter 14 changes to a high potential output, and the NAND gate 4 opens and waits for the output pulse from the zero-cross detection circuit 2 _A to be output. . In addition, the low potential output of the hold-off counter 14 causes the counter 9 to pass through the OR gate 12.
The count value of is cleared.

Therefore, only the 3-bit signal in the detected EFM signal is detected, and the length of the 3-bit signal is displayed on the display 10 in time. Also, the difference between this time display value and 694 nsec indicates the jitter of the 3-bit signal. Alternatively, a subtraction circuit may be provided in the display 10 so that only the jitter is displayed on the display 10.

In addition, in the above explanation, the length of the 3-bit signal was measured by the time from the rising zero cross to the falling zero cross of the detected EFM signal, but conversely, the length of the 3-bit signal was measured from the falling zero cross to the rising zero cross of the detected EFM signal. The same thing can be done even if the time is detected.

In the above explanation, the length or jitter of a 3-bit signal is measured by reading the display on the display 10, but it is also possible to read the count value of the counter 9 into the microcomputer. It's okay. In this case, the latch signal to the latch circuit 10-1, that is, the output pulse of the NAND gate 6, can be outputted to the microcomputer as an interrupt request signal to read the count value of the counter 9. In addition, instead of the output of the hold-off counter 14, a confirmation signal A _Q is obtained by reading the count value of the counter 9 from the microcomputer.
It is also possible to omit the AND gate 13 and the hold-off counter 14 by using .

Next, the reason why the present invention can be used to adjust and inspect the control system of a DAD playback device by measuring the 3-bit signal length in the detected EFM signal will be explained.

As a result of analyzing the detected EFM signal, it was found that the most information dependent on the characteristics of the control system of the DAD playback device was contained in the jitter portion of the 3-bit signal in the detected EFM signal. Therefore, by measuring the length of the 3-bit signal in the detected EFM signal to obtain the jitter component, or by directly measuring the jitter of the 3-bit signal, it is possible to test the quality of the control system of the DAD reproducing device.

Furthermore, compared to the conventional case where the waveform of the detected EFM signal is displayed using a cathode ray tube oscilloscope and the control system of the DAD playback device is inspected by observing the displayed waveform, according to an embodiment of the present invention, quantitative This makes inspection and adjustment easier.

In the above description, a 3-bit signal length was measured because the minimum inversion interval was 3 bits long, but the same structure can be applied even if the minimum inversion interval is another bit length.

Further, the same applies even when the modulated signal is other than the detected EFM signal.

As explained above, according to the present invention, it is detected that the count value of the counter has reached a value corresponding to the minimum inversion interval bit length in the EFM signal and the length of the next bit after the minimum inversion interval bit and approximately the intermediate length. detecting means is provided to detect the period from the zero-crossing time in the rising direction (or falling direction) of the modulated signal to the zero-crossing time in the falling direction (or rising direction) of the modulated signal before generation of the output from the detection means. Since it is configured to count the number of clock pulses in between, it acts as if it were a time window, and the bit length of the minimum inversion interval in the modulated signal can be measured from the counted value of the clock pulses.

Therefore, for example, adjusting the control system of a DAD playback device,
It can also be used for testing to quantitatively test the quality of the control system of the DAD playback device.

[Brief explanation of drawings]

Figure 1 is a waveform diagram of the detected EFM signal displayed on a cathode ray tube oscilloscope. FIG. 2 is a block diagram of one embodiment of the present invention. 2 _A and 2 _B ... Zero cross detection circuit, 3...
Clock pulse oscillator, 5... flip-flop, 9... counter, 10... display, 11...
NAND gate as a detection means.

Claims (1)

[Claims] 1 A minimum inversion interval bit length measuring device for measuring the length of a minimum inversion interval bit signal in a modulated signal continued from an information recording carrier, comprising a clock pulse oscillator that oscillates a clock pulse of a predetermined period, and a clock pulse oscillator that oscillates a clock pulse with a predetermined period; a first zero-crossing detection circuit that detects a zero-crossing in a rising or falling direction of a signal; a second zero-crossing detection circuit that detects a zero-crossing of the modulated signal in a direction opposite to that of the first zero-crossing detection circuit; and the clock pulse. a counter for counting, and the count value of the counter reaches a value corresponding to approximately the intermediate length between the length of the minimum inversion interval bit in the modulated signal and the length of the next bit of the minimum inversion interval bit. and a detection means for detecting the output of the first zero-cross detection circuit, and guiding the clock pulse to the counter from the time when the first zero-cross detection circuit generates an output until the second zero-cross detection circuit generates an output that occurs before the output of the first zero-cross detection circuit occurs. 1. A minimum inversion interval bit length measuring device, comprising: gate means.