JPH0136256B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and mainly relates to a method for manufacturing a semiconductor device.
² Targets L (Integrated Injection Logic) type semiconductor devices.

² L-type semiconductor devices are horizontal PNP devices on the same semiconductor substrate.
The collector of the injector transistor and the base of the inverse npn transistor are integrated into one structure, which has the advantage of improving the degree of integration. By the way, as a condition for increasing the injection efficiency of the injector, the impurity concentration of the injector can be changed to reverse npn.
It needs to be higher than that of the base layer of the transistor. For this reason, in the process of manufacturing semiconductor devices, separate masks have been prepared for the injector and the base of the inverse NPN transistor to perform diffusion. This required a margin for mask alignment for separate mask processes, and this became one of the reasons for preventing an increase in the degree of integration. An injector with a memory cell using ² L as shown in Figure 1.
In a case where inverse npn transistors Q ₃ and Q ₄ are configured in a pair of dots on the left and right with Q 1 and Q ₂ as the center, if _the injector mask shifts to the left or right, the h _FE of the injector transistor will change. There were problems such as differences in the left and right sides, resulting in non-uniform characteristics of the memory cells. In addition, in the above memory cell, R/W (Read and Write) transistors are formed on the left and right sides.
It is known that the write characteristics are faster when the h _FE of Q ₅ and Q ₆ are decreased, while the retention characteristics are better when the h _FE of the holding transistors Q ₃ and Q ₄ are increased. It is difficult to control the impurity concentration when the base of the /W transistor and the base of the holding transistor are the same, and if you try to diffuse it in separate mask processes to solve this problem, the problem of mask alignment margin (mask misalignment) mentioned above will occur. It was supposed to happen.

The present invention has been made to solve the above-mentioned problems. Accordingly, one object of the present invention is to provide a manufacturing method that can reduce the number of mask alignment steps for diffusion in a semiconductor device and improve the degree of integration. Another object of the present invention is to have a high degree of integration;
No variation in characteristics and excellent characteristics
² L-shaped memory cells are provided.

One embodiment of the present invention is to pre-form a common Si ₃ N ₄ mask with window holes for injector, base and emitter (CN) diffusion of the injector, inverse npn transistor in a ² L-type memory cell, and use photoresist or SiO ₂ The required impurities are introduced by covering the window holes alternately with a system mask. Hereinafter, each process of FIGS. 3a to 3h will be described in detail in accordance with an embodiment.

(a) A high resistivity p ^- (type) Si single crystal substrate (substrate) 1 is prepared, and a SiO ₂ mask 2 for forming an embedded n ⁺ layer is formed on one main surface by surface oxidation and photoetching. ) deposit,
The buried n ⁺ layer 3 is selectively formed by diffusion.
After this, the main surface on the opposite side of the p ^- substrate 1 is back-etched.

(b) Specific resistance 0.3Ωcm to embed the above n ⁺ layer 3,
An n ^- type epitaxial Si layer 4 having a thickness of approximately 1.2 μm is grown. Next, a SiO ₂ film 5 is formed on the surface of this Si layer 4 by thermal oxidation, and subsequently a Si ₃ N ₄ (silicon nitride) film 6 is deposited.

(c) Photoetch the Si ₃ N ₄ and SiO ₂ in the isolation region, and further etch the underlying n ^- epitaxial Si layer deeply (0.5 to 0.6 μm). Thereafter, the surface of the etched portion 7 is oxidized, and B (boron) ions are implanted into the etched portion 7 to form a p ⁺ layer 8 for isolation so as to be connected to the p ^- substrate 1. In the B ion implantation at this time, the SiO ₂ film 5 and the Si ₃ N ₄ film 6 serve as masks for ion implantation.

(d) Subsequently, isolation oxidation is performed using the Si ₃ N ₄ film 6 as a mask to form a thick isolation SiO ₂ film 9. After this, the Si ₃ N ₄ film 6 mentioned above is removed by etching and further
The SiO ₂ film 5 is also etched away, and then the silicon layer 4 is oxidized again to form a SiO ₂ film 10 with a thickness of about 500 Å on the surface of the silicon layer 4.
Deposit Si ₃ N ₄ to form a film with a thickness of approximately 2100 Å.
A new Si ₃ N ₄ film 11 is formed.

(e) The Si ₃ N ₄ film 11 is selectively etched away by photoresist treatment, and the injector, base,
Impurity introduction window holes 12, 13, and 14 for CN (also used as a collar for preventing parasitic effects at the emitter extraction part of the inverse npn transistor) are opened at the same time. Here, B (boron) ions are implanted through SiO ₂ using the Si ₃ N ₄ film with the window hole as a mask. Next, the window holes 13 and 14 other than the injector are covered with a photoresist mask (indicated by broken lines) 15, and high-concentration B ⁺ ion implantation is performed through the window hole 12 of the injector. After this, annealing was performed and B (boron) was implanted.
By stretching and diffusing into Si, a p ⁺ layer 16 for an injector and a p layer 17 for a base are formed, and a p layer 18 is formed in the CN part.

(f) PSG (Phosph
A silicate glass film 19 is formed on the entire surface. After this, photoetching is performed to form the p layer.
By exposing the CN part 18 and depositing P (phosphorous) at a high concentration using the PSG film 19 as a mask, and performing stretching and diffusion, the n ⁺ layer 20, which will become the emitter extraction part of the inverse npn transistor, is formed by n ⁺
It is formed so as to be connected to the buried layer 3. Thereafter, CN oxidation is performed to form a SiO ₂ film 21 with a thickness of about 2800 Å on the surface of the CN portion.

(g) Perform emitter photo-etching to open the collector (emitter) part of the reverse npn transistor, and
(Arsenic) ion implantation (As ⁺ 80KeV, N _D : 8×
10 ¹⁵ cm ^-2 ), and the n ⁺ layer 22 is formed by stretching and diffusion. Thereafter, contact photoetching is performed to form window openings in the insulating film on each region of the p ⁺ injector 16, p base 17, n ⁺ emitter extraction portion 20, and n ⁺ collector 22.

(h) An Al (aluminum) film 23 is formed on the window opening by sputtering, and then Al is photo-etched to form a predetermined pattern of Al electrodes INJ, B, which make ohmic contact with each of the above regions.
Form CNE1 and E2 (see Figure 2).

Thereafter, various steps (not shown) such as forming an interlayer insulating film, forming through holes, forming a second layer Al wiring, and forming a final passivation film continue, but details thereof will be omitted.

According to the present invention described in the embodiments above, the diffusion positions of the base, injector, etc. in the ₂ L-type memory cell are defined by the first SiO ₂ -Si ₃ N ₄ mask, and then by the photoresist mask or glass coating. Selective diffusion can be performed using a mask, and the number of mask alignment steps is reduced, so there is no need to consider mask alignment margins, increasing the degree of integration, and at the same time, a ^2L semiconductor device with small variations in characteristics can be obtained. It will be done. Note that the first mask contains SiO ₂ -
By adopting Si ₂ N ₄ , it is possible to form a mask using a glass film as a subsequent mask.
The Si ₃ N ₄ film is not attacked by the SiO ₂ etchant and retains its function as a corrosion-resistant mask.

Another embodiment of the present invention is to preform a common Si ₃ N ₄ mask with windows for the diffusion of the injector, the base of the inverse npn transistor, and the base of the R/W transistor in ^two L-type memory cells. By alternately covering the windows with a photoresist or SiO ₂ -based mask, selective diffusion is performed through each window to a desired concentration. Hereinafter, each process of FIGS. 4a to 4e will be described in detail in conjunction with an embodiment.

(a) Perform the same steps as steps a to d in FIG. 3 described above. In other words, selectively on one main surface of the p ^- Si substrate 1.
An n ⁺ buried layer 3 is formed, an n ^- type epitaxial layer 4 is grown on one main surface of the Si substrate 1 so as to bury this buried layer 3, and a film is formed on the surface of this n ^- epitaxial layer 4. A SiO ₂ film 10 with a thickness of about 500 Å and a Si ₃ N ₄ film 11 with a thickness of about 2100 Å are formed.

(b) The Si ₃ N ₄ film 11 is selectively etched by photoresist treatment, and the injector, base (reverse npn
Window holes 12 and 13 for the mold holding transistor and R/W transistor are simultaneously opened.
Here, B (boron) ions are implanted into the n ^- layer 4 through the SiO ₂ film 10 using the Si ₃ N ₄ film 11 with the above-mentioned window holes as a mask to form a p-type introduction layer 24 in the injector and base portions.

(c) Next, a photoresist mask 25 is formed, and high concentration B ions are implanted into a portion of the injector and base, overlapping the p-type introduction layer.
After this, annealing is performed and the implanted B (boron) is stretched and diffused into the Si, and the R/W is applied to the p ⁺ layer 17 for the injector and a part of the base.
A p ⁺ base layer 26 for the transistor and a p base layer 27 for the holding transistor are formed on the other part of the base at the same time.

(d) After removing the photoresist mask 25, CVD
A PSG film 28 is formed by a method. Thereafter, a portion of the PSG film 28 is removed by photo-etching, and then As ions are implanted and the n ⁺ emitters 29 and 30 of the R/W transistor and the holding transistor are formed by stretching and diffusion.

(e) After contact photoetching, an Al film is formed and patterned using photoresist to form a predetermined pattern that makes ohmic contact with each region.
An Al electrode 31 is formed. FIG. 2 shows a planar pattern of the memory cell formed as described above. Referring to FIG. 2 above, the electrode E ₁ of the R/W transistor is connected to the n ⁺ emitter 29 formed in the heavily doped p ⁺ base region 26, and the electrode B ₁ or B ₂ is connected to this p ⁺ base region. , the electrode E ₂ of the holding transistor is connected to the n ⁺ emitter 30 on the lightly doped p base region. In FIG. 2, the dotted line indicates the diffusion region, and the solid line indicates the Al wiring.

According to the present invention described in the above embodiments, the diffusion positions of the base, injector, etc. in the ² L-type memory cell are defined by the first SiO ₂ -Si ₃ N ₄ mask, and the subsequent photoresist mask, SiO ₂ -based By performing selective diffusion using a glass film mask, the p ⁺ diffusion layer for the injector and the impurity diffusion layer of the base layer of the R/W transistor can be made to have the same impurity concentration with a small mask alignment process, while the p + diffusion layer of the holding transistor It is possible to lower the base impurity concentration than the impurity concentration of the p ⁺ layer, resulting in good write characteristics and excellent retention characteristics.
² L-shaped memory cells can be obtained.

The present invention is not limited to the above-mentioned embodiments, and has various other modifications. For example, a SiO ₂ film may be used in place of the PSG film 19 used in the step of FIG. 3f. Further, a glass film such as a PSG film may be used in place of the photoresist films 15 and 25 used in the step e in FIG. 3 and the step c in FIG. 4.

The present invention is applied to a method for manufacturing ² L-type memory cells,
In particular, the effect can be effectively obtained when applied to bipolar RAM of 16K bits or more.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of ^{a 2L} -type memory cell, and FIG. 2 is a plan view showing a planar pattern of the memory cell according to the present invention. 3a to 3h are process cross-sectional views showing the manufacturing process of a ^2L -type memory cell according to one embodiment of the present invention, and FIGS. 4a to 4e are ^2L -type memory cells according to another embodiment of the present invention. FIG. 3 is a partial process cross-sectional view showing the manufacturing process of a memory cell. 1...p ^- Si substrate, 2...SiO ₂ mask, 3...n ⁺ layer for embedding, 4...n ^- epitaxial layer, 5, 10...
SiO ₂ film, 6, 11...Si ₃ N ₄ film, 7... Etch part, 8
...P ⁺ layer for isolation, 9...Isolation SiO ₂ film, 12, 13, 14... Window hole for impurity introduction, 15, 25... Photoresist mask, 16...
P ⁺ layer for injector, 17...p layer for base, 1
9, 28...SiO ₂ glass coating, 20...CN part (n ⁺
layer), 22...n ⁺ layer, 23, 31...Al film electrode, 26
...p ⁺ base layer for B/W transistor, 27...p base layer for holding transistor, 29...n ⁺ emitter of B/W transistor, 30...n ⁺ emitter (collector) of holding transistor, 31...Al electrode.

Claims (1)

[Claims] 1. In a first conductivity type semiconductor region, an injector of a second conductivity type, a base of a second conductivity type disposed apart from the injector, and a first conductivity type disposed within the base. In a method for manufacturing a semiconductor device comprising a ² L-shaped semiconductor device having a collector of
forming a first mask made of silicon nitride that shares the impurity introduction window for the injector and base of the ^two L-shaped semiconductor devices on the surface of the first conductivity type semiconductor region; introducing a second conductivity type impurity for the base through each of the window holes using a mask;
While the base impurity introduction window of the first mask is covered with a second mask made of an insulator other than silicon nitride, the second conductivity type impurity is introduced from the injector window of the first mask. A third mask made of an insulator other than silicon nitride covers the impurity introduction window hole of the injector of the first mask, and
The collector impurity introduction window of the third mask is partially covered so as to form a collector impurity introduction window in the impurity introduction window of the base of the third mask. forming a first conductivity type collector in the base region by introducing impurities of a first conductivity type; and forming an electrode extending on the first mask without removing the first mask; 1. A method for manufacturing a semiconductor device, comprising the steps of forming a semiconductor device. 2 The second mask is made of photoresist,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the third mask is made of an insulator containing silicon oxide.