JPH0136287B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switch circuit in which a single switch has multiple switch functions.

A conventional switch circuit requires the installation of a plurality of switches in order to perform a plurality of functions, and has a circuit configuration as shown in FIG. That is, SW1 to SWn are a plurality of switches, and 11 to 1n are RS flip-flops.
R is a bias resistor connected to the power supply +V.
When one of these switches, for example SWn, is pressed, the corresponding switch signal 2n changes, and the subsystem is configured to detect that the switch has been pressed and perform a corresponding functional operation.

However, in conventional switch circuits with this type of configuration, when a switch is pressed, it performs only a specific function, so in order to perform multiple functions, multiple switches must be activated. , and the number of signal lines for the interface increases, resulting in high cost and the need for a large amount of space.

The present invention has been made in view of the above circumstances, and its purpose is to perform a corresponding processing function depending on how many times the same switch is pressed within a certain period of time when a single installed switch is pressed. It is an object of the present invention to provide a switch circuit that eliminates the need for installing a plurality of switches.

Next, an embodiment of the switch circuit of the present invention will be explained with reference to the circuit diagram of FIG. 2. SW is a single installed switch, 1 is an RS flip-flop (hereinafter referred to as F/
2 is a shift register, 3 is a one-shot F/F, and 4 is a gate for the trigger signal of this one-shot F/F 3. 51 to 5n are outputs 21 to 2n of shift register 2 and one shot F/
This is an AND gate with the output of F. The CLR signal is a clear signal that is output when the subsystem detects a change in the output signals 61 to 6n of the gates 51 to 5n due to the depression of a switch. The PRC signal is being processed by the subsystem, and is used to ensure that the signals 61 to 6n do not change even if the switch is pressed again. 7 is an AND gate between the output of the one-shot F/F and the PRC signal.

FIG. 3 is a timing diagram of the switch circuit constructed in this manner.

The operation of the switch circuit of the present invention configured as described above will be explained below with reference to FIGS. 2 and 3. When SW is pressed, the output of RSF/F1 rises and the PRC signal becomes high level. For,
The output signal SWS of gate 7 is while SW is pressed.
(A) Fall down. This becomes the clock for the shift register 2, and its output 21 becomes high level. on the other hand
Since 3OUT is currently at high level, the output of gate 4 is
One-shot F/F due to SWS level changes
Set 3. If SW is pressed again before 3OUT rises, the output signal SWS will remain as long as SW is pressed.
(B) Output 2 of shift register 2 as before falling
2 becomes 1. Since 3OUT is at low level at this time, one shot F/F3 will not be set again. After the SW is pressed for the first time and a certain period of time has elapsed, the output 3OUT of the one-shot F/F3 rises.
At this time, the gates 51-5n are opened, and the outputs 21-2n of the shift register 2 are inverted and output as outputs 61-6n. When the SW is pressed twice as described above, the output signal 62 of the gate 52 becomes low level. The subsystem performs the corresponding processing. When the subsystem detects that one of the signals 61 to 6n goes low and the SW is pressed, it immediately sends a PRC signal. It also sends the CLR signal, raises the signals CLR and PRC when the processing is completely completed, and waits for the next SW button to be pressed.

As is clear from the above description, according to the present invention, a single switch has the functions of multiple switches that were required in the past, so there is no need for a large number of interface signal lines as in the past. , it is possible to eliminate the disadvantages of high cost and large space requirements, and has great practical value.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram of a conventional switch circuit, FIG. 2 is a wiring diagram of a switch circuit according to the present invention, and FIG. 3 is a timing chart of signals of each part thereof. 1, 11, 1n...RS flip-flop, 2
...Shift register, 3...One-shot flip-flop.

Claims (1)

[Claims] 1 means for monitoring a certain period of time after a single switch is first pressed; means for monitoring how many times the single switch has been pressed within this certain period of time; output signals for specifying means for processing different functions corresponding to the number of valid times detected by the number of valid times detected by the number of valid times detected by the number of times monitoring means when the predetermined period of time has elapsed; an output means for outputting;
a switch circuit comprising disabling means for disabling the input of the single switch when the means for processing the function specified by the output means is in process;